ichsmb.c revision 1.27.6.1
1 /* $NetBSD: ichsmb.c,v 1.27.6.1 2013/02/25 00:29:17 tls Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.18 2007/05/03 09:36:26 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.27.6.1 2013/02/25 00:29:17 tls Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/ic/i82801lpcreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #ifdef ICHIIC_DEBUG 45 #define DPRINTF(x) printf x 46 #else 47 #define DPRINTF(x) 48 #endif 49 50 #define ICHIIC_DELAY 100 51 #define ICHIIC_TIMEOUT 1 52 53 struct ichsmb_softc { 54 device_t sc_dev; 55 56 bus_space_tag_t sc_iot; 57 bus_space_handle_t sc_ioh; 58 void * sc_ih; 59 int sc_poll; 60 61 struct i2c_controller sc_i2c_tag; 62 kmutex_t sc_i2c_mutex; 63 struct { 64 i2c_op_t op; 65 void * buf; 66 size_t len; 67 int flags; 68 volatile int error; 69 } sc_i2c_xfer; 70 }; 71 72 static int ichsmb_match(device_t, cfdata_t, void *); 73 static void ichsmb_attach(device_t, device_t, void *); 74 75 static int ichsmb_i2c_acquire_bus(void *, int); 76 static void ichsmb_i2c_release_bus(void *, int); 77 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 78 size_t, void *, size_t, int); 79 80 static int ichsmb_intr(void *); 81 82 83 CFATTACH_DECL_NEW(ichsmb, sizeof(struct ichsmb_softc), 84 ichsmb_match, ichsmb_attach, NULL, NULL); 85 86 87 static int 88 ichsmb_match(device_t parent, cfdata_t match, void *aux) 89 { 90 struct pci_attach_args *pa = aux; 91 92 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 93 switch (PCI_PRODUCT(pa->pa_id)) { 94 case PCI_PRODUCT_INTEL_6300ESB_SMB: 95 case PCI_PRODUCT_INTEL_63XXESB_SMB: 96 case PCI_PRODUCT_INTEL_82801AA_SMB: 97 case PCI_PRODUCT_INTEL_82801AB_SMB: 98 case PCI_PRODUCT_INTEL_82801BA_SMB: 99 case PCI_PRODUCT_INTEL_82801CA_SMB: 100 case PCI_PRODUCT_INTEL_82801DB_SMB: 101 case PCI_PRODUCT_INTEL_82801E_SMB: 102 case PCI_PRODUCT_INTEL_82801EB_SMB: 103 case PCI_PRODUCT_INTEL_82801FB_SMB: 104 case PCI_PRODUCT_INTEL_82801G_SMB: 105 case PCI_PRODUCT_INTEL_82801H_SMB: 106 case PCI_PRODUCT_INTEL_82801I_SMB: 107 case PCI_PRODUCT_INTEL_82801JD_SMB: 108 case PCI_PRODUCT_INTEL_82801JI_SMB: 109 case PCI_PRODUCT_INTEL_3400_SMB: 110 case PCI_PRODUCT_INTEL_6SERIES_SMB: 111 case PCI_PRODUCT_INTEL_7SERIES_SMB: 112 case PCI_PRODUCT_INTEL_C600_SMBUS: 113 case PCI_PRODUCT_INTEL_C600_SMB_0: 114 case PCI_PRODUCT_INTEL_C600_SMB_1: 115 case PCI_PRODUCT_INTEL_C600_SMB_2: 116 return 1; 117 } 118 } 119 return 0; 120 } 121 122 static void 123 ichsmb_attach(device_t parent, device_t self, void *aux) 124 { 125 struct ichsmb_softc *sc = device_private(self); 126 struct pci_attach_args *pa = aux; 127 struct i2cbus_attach_args iba; 128 pcireg_t conf; 129 bus_size_t iosize; 130 pci_intr_handle_t ih; 131 const char *intrstr = NULL; 132 133 sc->sc_dev = self; 134 135 pci_aprint_devinfo(pa, NULL); 136 137 /* Read configuration */ 138 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 139 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 140 141 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 142 aprint_error_dev(self, "SMBus disabled\n"); 143 return; 144 } 145 146 /* Map I/O space */ 147 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 148 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize)) { 149 aprint_error_dev(self, "can't map I/O space\n"); 150 return; 151 } 152 153 sc->sc_poll = 1; 154 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 155 /* No PCI IRQ */ 156 aprint_normal_dev(self, "interrupting at SMI\n"); 157 } else { 158 /* Install interrupt handler */ 159 if (pci_intr_map(pa, &ih) == 0) { 160 intrstr = pci_intr_string(pa->pa_pc, ih); 161 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 162 ichsmb_intr, sc); 163 if (sc->sc_ih != NULL) { 164 aprint_normal_dev(self, "interrupting at %s\n", 165 intrstr); 166 sc->sc_poll = 0; 167 } 168 } 169 if (sc->sc_poll) 170 aprint_normal_dev(self, "polling\n"); 171 } 172 173 /* Attach I2C bus */ 174 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 175 sc->sc_i2c_tag.ic_cookie = sc; 176 sc->sc_i2c_tag.ic_acquire_bus = ichsmb_i2c_acquire_bus; 177 sc->sc_i2c_tag.ic_release_bus = ichsmb_i2c_release_bus; 178 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 179 180 memset(&iba, 0, sizeof(iba)); 181 iba.iba_type = I2C_TYPE_SMBUS; 182 iba.iba_tag = &sc->sc_i2c_tag; 183 config_found(self, &iba, iicbus_print); 184 185 if (!pmf_device_register(self, NULL, NULL)) 186 aprint_error_dev(self, "couldn't establish power handler\n"); 187 } 188 189 static int 190 ichsmb_i2c_acquire_bus(void *cookie, int flags) 191 { 192 struct ichsmb_softc *sc = cookie; 193 194 if (cold) 195 return 0; 196 197 mutex_enter(&sc->sc_i2c_mutex); 198 return 0; 199 } 200 201 static void 202 ichsmb_i2c_release_bus(void *cookie, int flags) 203 { 204 struct ichsmb_softc *sc = cookie; 205 206 if (cold) 207 return; 208 209 mutex_exit(&sc->sc_i2c_mutex); 210 } 211 212 static int 213 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 214 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 215 { 216 struct ichsmb_softc *sc = cookie; 217 const uint8_t *b; 218 uint8_t ctl = 0, st; 219 int retries; 220 char fbuf[64]; 221 222 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 223 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 224 len, flags)); 225 226 /* Wait for bus to be idle */ 227 for (retries = 100; retries > 0; retries--) { 228 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 229 if (!(st & LPCIB_SMB_HS_BUSY)) 230 break; 231 DELAY(ICHIIC_DELAY); 232 } 233 #ifdef ICHIIC_DEBUG 234 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 235 printf("%s: exec: st 0x%s\n", device_xname(sc->sc_dev), fbuf); 236 #endif 237 if (st & LPCIB_SMB_HS_BUSY) 238 return (1); 239 240 if (cold || sc->sc_poll) 241 flags |= I2C_F_POLL; 242 243 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 244 (cmdlen == 0 && len > 1)) 245 return (1); 246 247 /* Setup transfer */ 248 sc->sc_i2c_xfer.op = op; 249 sc->sc_i2c_xfer.buf = buf; 250 sc->sc_i2c_xfer.len = len; 251 sc->sc_i2c_xfer.flags = flags; 252 sc->sc_i2c_xfer.error = 0; 253 254 /* Set slave address and transfer direction */ 255 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 256 LPCIB_SMB_TXSLVA_ADDR(addr) | 257 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 258 259 b = (const uint8_t *)cmdbuf; 260 if (cmdlen > 0) 261 /* Set command byte */ 262 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 263 264 if (I2C_OP_WRITE_P(op)) { 265 /* Write data */ 266 b = buf; 267 if (cmdlen == 0 && len == 1) 268 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 269 LPCIB_SMB_HCMD, b[0]); 270 else if (len > 0) 271 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 272 LPCIB_SMB_HD0, b[0]); 273 if (len > 1) 274 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 275 LPCIB_SMB_HD1, b[1]); 276 } 277 278 /* Set SMBus command */ 279 if (cmdlen == 0) { 280 if (len == 0) 281 ctl = LPCIB_SMB_HC_CMD_QUICK; 282 else 283 ctl = LPCIB_SMB_HC_CMD_BYTE; 284 } else if (len == 1) 285 ctl = LPCIB_SMB_HC_CMD_BDATA; 286 else if (len == 2) 287 ctl = LPCIB_SMB_HC_CMD_WDATA; 288 289 if ((flags & I2C_F_POLL) == 0) 290 ctl |= LPCIB_SMB_HC_INTREN; 291 292 /* Start transaction */ 293 ctl |= LPCIB_SMB_HC_START; 294 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 295 296 if (flags & I2C_F_POLL) { 297 /* Poll for completion */ 298 DELAY(ICHIIC_DELAY); 299 for (retries = 1000; retries > 0; retries--) { 300 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 301 LPCIB_SMB_HS); 302 if ((st & LPCIB_SMB_HS_BUSY) == 0) 303 break; 304 DELAY(ICHIIC_DELAY); 305 } 306 if (st & LPCIB_SMB_HS_BUSY) 307 goto timeout; 308 ichsmb_intr(sc); 309 } else { 310 /* Wait for interrupt */ 311 if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz)) 312 goto timeout; 313 } 314 315 if (sc->sc_i2c_xfer.error) 316 return (1); 317 318 return (0); 319 320 timeout: 321 /* 322 * Transfer timeout. Kill the transaction and clear status bits. 323 */ 324 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 325 aprint_error_dev(sc->sc_dev, 326 "exec: op %d, addr 0x%02x, cmdlen %zd, len %zd, " 327 "flags 0x%02x: timeout, status 0x%s\n", 328 op, addr, cmdlen, len, flags, fbuf); 329 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 330 LPCIB_SMB_HC_KILL); 331 DELAY(ICHIIC_DELAY); 332 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 333 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 334 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 335 aprint_error_dev(sc->sc_dev, "abort failed, status 0x%s\n", 336 fbuf); 337 } 338 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 339 return (1); 340 } 341 342 static int 343 ichsmb_intr(void *arg) 344 { 345 struct ichsmb_softc *sc = arg; 346 uint8_t st; 347 uint8_t *b; 348 size_t len; 349 #ifdef ICHIIC_DEBUG 350 char fbuf[64]; 351 #endif 352 353 /* Read status */ 354 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 355 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 356 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 357 LPCIB_SMB_HS_SMBAL | LPCIB_SMB_HS_BDONE)) == 0) 358 /* Interrupt was not for us */ 359 return (0); 360 361 #ifdef ICHIIC_DEBUG 362 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 363 printf("%s: intr st 0x%s\n", device_xname(sc->sc_dev), fbuf); 364 #endif 365 366 /* Clear status bits */ 367 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 368 369 /* Check for errors */ 370 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 371 sc->sc_i2c_xfer.error = 1; 372 goto done; 373 } 374 375 if (st & LPCIB_SMB_HS_INTR) { 376 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 377 goto done; 378 379 /* Read data */ 380 b = sc->sc_i2c_xfer.buf; 381 len = sc->sc_i2c_xfer.len; 382 if (len > 0) 383 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 384 LPCIB_SMB_HD0); 385 if (len > 1) 386 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 387 LPCIB_SMB_HD1); 388 } 389 390 done: 391 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 392 wakeup(sc); 393 return (1); 394 } 395
Indexes created Thu Oct 02 14:10:14 GMT 2025