ichsmb.c revision 1.29
1 /* $NetBSD: ichsmb.c,v 1.29 2012/11/29 18:48:26 msaitoh Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.18 2007/05/03 09:36:26 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.29 2012/11/29 18:48:26 msaitoh Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/ic/i82801lpcreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #ifdef ICHIIC_DEBUG 45 #define DPRINTF(x) printf x 46 #else 47 #define DPRINTF(x) 48 #endif 49 50 #define ICHIIC_DELAY 100 51 #define ICHIIC_TIMEOUT 1 52 53 struct ichsmb_softc { 54 device_t sc_dev; 55 56 bus_space_tag_t sc_iot; 57 bus_space_handle_t sc_ioh; 58 void * sc_ih; 59 int sc_poll; 60 61 struct i2c_controller sc_i2c_tag; 62 kmutex_t sc_i2c_mutex; 63 struct { 64 i2c_op_t op; 65 void * buf; 66 size_t len; 67 int flags; 68 volatile int error; 69 } sc_i2c_xfer; 70 }; 71 72 static int ichsmb_match(device_t, cfdata_t, void *); 73 static void ichsmb_attach(device_t, device_t, void *); 74 75 static int ichsmb_i2c_acquire_bus(void *, int); 76 static void ichsmb_i2c_release_bus(void *, int); 77 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 78 size_t, void *, size_t, int); 79 80 static int ichsmb_intr(void *); 81 82 83 CFATTACH_DECL_NEW(ichsmb, sizeof(struct ichsmb_softc), 84 ichsmb_match, ichsmb_attach, NULL, NULL); 85 86 87 static int 88 ichsmb_match(device_t parent, cfdata_t match, void *aux) 89 { 90 struct pci_attach_args *pa = aux; 91 92 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 93 switch (PCI_PRODUCT(pa->pa_id)) { 94 case PCI_PRODUCT_INTEL_6300ESB_SMB: 95 case PCI_PRODUCT_INTEL_63XXESB_SMB: 96 case PCI_PRODUCT_INTEL_82801AA_SMB: 97 case PCI_PRODUCT_INTEL_82801AB_SMB: 98 case PCI_PRODUCT_INTEL_82801BA_SMB: 99 case PCI_PRODUCT_INTEL_82801CA_SMB: 100 case PCI_PRODUCT_INTEL_82801DB_SMB: 101 case PCI_PRODUCT_INTEL_82801E_SMB: 102 case PCI_PRODUCT_INTEL_82801EB_SMB: 103 case PCI_PRODUCT_INTEL_82801FB_SMB: 104 case PCI_PRODUCT_INTEL_82801G_SMB: 105 case PCI_PRODUCT_INTEL_82801H_SMB: 106 case PCI_PRODUCT_INTEL_82801I_SMB: 107 case PCI_PRODUCT_INTEL_82801JD_SMB: 108 case PCI_PRODUCT_INTEL_82801JI_SMB: 109 case PCI_PRODUCT_INTEL_3400_SMB: 110 case PCI_PRODUCT_INTEL_6SERIES_SMB: 111 case PCI_PRODUCT_INTEL_7SERIES_SMB: 112 case PCI_PRODUCT_INTEL_C600_SMB_0: 113 case PCI_PRODUCT_INTEL_C600_SMB_1: 114 case PCI_PRODUCT_INTEL_C600_SMB_2: 115 return 1; 116 } 117 } 118 return 0; 119 } 120 121 static void 122 ichsmb_attach(device_t parent, device_t self, void *aux) 123 { 124 struct ichsmb_softc *sc = device_private(self); 125 struct pci_attach_args *pa = aux; 126 struct i2cbus_attach_args iba; 127 pcireg_t conf; 128 bus_size_t iosize; 129 pci_intr_handle_t ih; 130 const char *intrstr = NULL; 131 132 sc->sc_dev = self; 133 134 pci_aprint_devinfo(pa, NULL); 135 136 /* Read configuration */ 137 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 138 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 139 140 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 141 aprint_error_dev(self, "SMBus disabled\n"); 142 return; 143 } 144 145 /* Map I/O space */ 146 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 147 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize)) { 148 aprint_error_dev(self, "can't map I/O space\n"); 149 return; 150 } 151 152 sc->sc_poll = 1; 153 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 154 /* No PCI IRQ */ 155 aprint_normal_dev(self, "interrupting at SMI\n"); 156 } else { 157 /* Install interrupt handler */ 158 if (pci_intr_map(pa, &ih) == 0) { 159 intrstr = pci_intr_string(pa->pa_pc, ih); 160 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 161 ichsmb_intr, sc); 162 if (sc->sc_ih != NULL) { 163 aprint_normal_dev(self, "interrupting at %s\n", 164 intrstr); 165 sc->sc_poll = 0; 166 } 167 } 168 if (sc->sc_poll) 169 aprint_normal_dev(self, "polling\n"); 170 } 171 172 /* Attach I2C bus */ 173 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 174 sc->sc_i2c_tag.ic_cookie = sc; 175 sc->sc_i2c_tag.ic_acquire_bus = ichsmb_i2c_acquire_bus; 176 sc->sc_i2c_tag.ic_release_bus = ichsmb_i2c_release_bus; 177 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 178 179 memset(&iba, 0, sizeof(iba)); 180 iba.iba_type = I2C_TYPE_SMBUS; 181 iba.iba_tag = &sc->sc_i2c_tag; 182 config_found(self, &iba, iicbus_print); 183 184 if (!pmf_device_register(self, NULL, NULL)) 185 aprint_error_dev(self, "couldn't establish power handler\n"); 186 } 187 188 static int 189 ichsmb_i2c_acquire_bus(void *cookie, int flags) 190 { 191 struct ichsmb_softc *sc = cookie; 192 193 if (cold) 194 return 0; 195 196 mutex_enter(&sc->sc_i2c_mutex); 197 return 0; 198 } 199 200 static void 201 ichsmb_i2c_release_bus(void *cookie, int flags) 202 { 203 struct ichsmb_softc *sc = cookie; 204 205 if (cold) 206 return; 207 208 mutex_exit(&sc->sc_i2c_mutex); 209 } 210 211 static int 212 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 213 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 214 { 215 struct ichsmb_softc *sc = cookie; 216 const uint8_t *b; 217 uint8_t ctl = 0, st; 218 int retries; 219 char fbuf[64]; 220 221 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 222 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 223 len, flags)); 224 225 /* Wait for bus to be idle */ 226 for (retries = 100; retries > 0; retries--) { 227 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 228 if (!(st & LPCIB_SMB_HS_BUSY)) 229 break; 230 DELAY(ICHIIC_DELAY); 231 } 232 #ifdef ICHIIC_DEBUG 233 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 234 printf("%s: exec: st 0x%s\n", device_xname(sc->sc_dev), fbuf); 235 #endif 236 if (st & LPCIB_SMB_HS_BUSY) 237 return (1); 238 239 if (cold || sc->sc_poll) 240 flags |= I2C_F_POLL; 241 242 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 243 (cmdlen == 0 && len > 1)) 244 return (1); 245 246 /* Setup transfer */ 247 sc->sc_i2c_xfer.op = op; 248 sc->sc_i2c_xfer.buf = buf; 249 sc->sc_i2c_xfer.len = len; 250 sc->sc_i2c_xfer.flags = flags; 251 sc->sc_i2c_xfer.error = 0; 252 253 /* Set slave address and transfer direction */ 254 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 255 LPCIB_SMB_TXSLVA_ADDR(addr) | 256 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 257 258 b = (const uint8_t *)cmdbuf; 259 if (cmdlen > 0) 260 /* Set command byte */ 261 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 262 263 if (I2C_OP_WRITE_P(op)) { 264 /* Write data */ 265 b = buf; 266 if (cmdlen == 0 && len == 1) 267 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 268 LPCIB_SMB_HCMD, b[0]); 269 else if (len > 0) 270 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 271 LPCIB_SMB_HD0, b[0]); 272 if (len > 1) 273 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 274 LPCIB_SMB_HD1, b[1]); 275 } 276 277 /* Set SMBus command */ 278 if (cmdlen == 0) { 279 if (len == 0) 280 ctl = LPCIB_SMB_HC_CMD_QUICK; 281 else 282 ctl = LPCIB_SMB_HC_CMD_BYTE; 283 } else if (len == 1) 284 ctl = LPCIB_SMB_HC_CMD_BDATA; 285 else if (len == 2) 286 ctl = LPCIB_SMB_HC_CMD_WDATA; 287 288 if ((flags & I2C_F_POLL) == 0) 289 ctl |= LPCIB_SMB_HC_INTREN; 290 291 /* Start transaction */ 292 ctl |= LPCIB_SMB_HC_START; 293 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 294 295 if (flags & I2C_F_POLL) { 296 /* Poll for completion */ 297 DELAY(ICHIIC_DELAY); 298 for (retries = 1000; retries > 0; retries--) { 299 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 300 LPCIB_SMB_HS); 301 if ((st & LPCIB_SMB_HS_BUSY) == 0) 302 break; 303 DELAY(ICHIIC_DELAY); 304 } 305 if (st & LPCIB_SMB_HS_BUSY) 306 goto timeout; 307 ichsmb_intr(sc); 308 } else { 309 /* Wait for interrupt */ 310 if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz)) 311 goto timeout; 312 } 313 314 if (sc->sc_i2c_xfer.error) 315 return (1); 316 317 return (0); 318 319 timeout: 320 /* 321 * Transfer timeout. Kill the transaction and clear status bits. 322 */ 323 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 324 aprint_error_dev(sc->sc_dev, 325 "exec: op %d, addr 0x%02x, cmdlen %zd, len %zd, " 326 "flags 0x%02x: timeout, status 0x%s\n", 327 op, addr, cmdlen, len, flags, fbuf); 328 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 329 LPCIB_SMB_HC_KILL); 330 DELAY(ICHIIC_DELAY); 331 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 332 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 333 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 334 aprint_error_dev(sc->sc_dev, "abort failed, status 0x%s\n", 335 fbuf); 336 } 337 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 338 return (1); 339 } 340 341 static int 342 ichsmb_intr(void *arg) 343 { 344 struct ichsmb_softc *sc = arg; 345 uint8_t st; 346 uint8_t *b; 347 size_t len; 348 #ifdef ICHIIC_DEBUG 349 char fbuf[64]; 350 #endif 351 352 /* Read status */ 353 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 354 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 355 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 356 LPCIB_SMB_HS_SMBAL | LPCIB_SMB_HS_BDONE)) == 0) 357 /* Interrupt was not for us */ 358 return (0); 359 360 #ifdef ICHIIC_DEBUG 361 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 362 printf("%s: intr st 0x%s\n", device_xname(sc->sc_dev), fbuf); 363 #endif 364 365 /* Clear status bits */ 366 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 367 368 /* Check for errors */ 369 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 370 sc->sc_i2c_xfer.error = 1; 371 goto done; 372 } 373 374 if (st & LPCIB_SMB_HS_INTR) { 375 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 376 goto done; 377 378 /* Read data */ 379 b = sc->sc_i2c_xfer.buf; 380 len = sc->sc_i2c_xfer.len; 381 if (len > 0) 382 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 383 LPCIB_SMB_HD0); 384 if (len > 1) 385 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 386 LPCIB_SMB_HD1); 387 } 388 389 done: 390 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 391 wakeup(sc); 392 return (1); 393 } 394
Indexes created Thu Oct 02 14:10:14 GMT 2025