ichsmb.c revision 1.30.2.2
1 /* $NetBSD: ichsmb.c,v 1.30.2.2 2014/05/18 17:45:40 rmind Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.18 2007/05/03 09:36:26 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.30.2.2 2014/05/18 17:45:40 rmind Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/ic/i82801lpcreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #ifdef ICHIIC_DEBUG 45 #define DPRINTF(x) printf x 46 #else 47 #define DPRINTF(x) 48 #endif 49 50 #define ICHIIC_DELAY 100 51 #define ICHIIC_TIMEOUT 1 52 53 struct ichsmb_softc { 54 device_t sc_dev; 55 56 bus_space_tag_t sc_iot; 57 bus_space_handle_t sc_ioh; 58 void * sc_ih; 59 int sc_poll; 60 61 struct i2c_controller sc_i2c_tag; 62 kmutex_t sc_i2c_mutex; 63 struct { 64 i2c_op_t op; 65 void * buf; 66 size_t len; 67 int flags; 68 volatile int error; 69 } sc_i2c_xfer; 70 }; 71 72 static int ichsmb_match(device_t, cfdata_t, void *); 73 static void ichsmb_attach(device_t, device_t, void *); 74 75 static int ichsmb_i2c_acquire_bus(void *, int); 76 static void ichsmb_i2c_release_bus(void *, int); 77 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 78 size_t, void *, size_t, int); 79 80 static int ichsmb_intr(void *); 81 82 83 CFATTACH_DECL_NEW(ichsmb, sizeof(struct ichsmb_softc), 84 ichsmb_match, ichsmb_attach, NULL, NULL); 85 86 87 static int 88 ichsmb_match(device_t parent, cfdata_t match, void *aux) 89 { 90 struct pci_attach_args *pa = aux; 91 92 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 93 switch (PCI_PRODUCT(pa->pa_id)) { 94 case PCI_PRODUCT_INTEL_6300ESB_SMB: 95 case PCI_PRODUCT_INTEL_63XXESB_SMB: 96 case PCI_PRODUCT_INTEL_82801AA_SMB: 97 case PCI_PRODUCT_INTEL_82801AB_SMB: 98 case PCI_PRODUCT_INTEL_82801BA_SMB: 99 case PCI_PRODUCT_INTEL_82801CA_SMB: 100 case PCI_PRODUCT_INTEL_82801DB_SMB: 101 case PCI_PRODUCT_INTEL_82801E_SMB: 102 case PCI_PRODUCT_INTEL_82801EB_SMB: 103 case PCI_PRODUCT_INTEL_82801FB_SMB: 104 case PCI_PRODUCT_INTEL_82801G_SMB: 105 case PCI_PRODUCT_INTEL_82801H_SMB: 106 case PCI_PRODUCT_INTEL_82801I_SMB: 107 case PCI_PRODUCT_INTEL_82801JD_SMB: 108 case PCI_PRODUCT_INTEL_82801JI_SMB: 109 case PCI_PRODUCT_INTEL_3400_SMB: 110 case PCI_PRODUCT_INTEL_6SERIES_SMB: 111 case PCI_PRODUCT_INTEL_7SERIES_SMB: 112 case PCI_PRODUCT_INTEL_8SERIES_SMB: 113 case PCI_PRODUCT_INTEL_CORE4G_M_SMB: 114 case PCI_PRODUCT_INTEL_C600_SMBUS: 115 case PCI_PRODUCT_INTEL_C600_SMB_0: 116 case PCI_PRODUCT_INTEL_C600_SMB_1: 117 case PCI_PRODUCT_INTEL_C600_SMB_2: 118 case PCI_PRODUCT_INTEL_C2000_PCU_SMBUS: 119 return 1; 120 } 121 } 122 return 0; 123 } 124 125 static void 126 ichsmb_attach(device_t parent, device_t self, void *aux) 127 { 128 struct ichsmb_softc *sc = device_private(self); 129 struct pci_attach_args *pa = aux; 130 struct i2cbus_attach_args iba; 131 pcireg_t conf; 132 bus_size_t iosize; 133 pci_intr_handle_t ih; 134 const char *intrstr = NULL; 135 char intrbuf[PCI_INTRSTR_LEN]; 136 137 sc->sc_dev = self; 138 139 pci_aprint_devinfo(pa, NULL); 140 141 /* Read configuration */ 142 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 143 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 144 145 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 146 aprint_error_dev(self, "SMBus disabled\n"); 147 return; 148 } 149 150 /* Map I/O space */ 151 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 152 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize)) { 153 aprint_error_dev(self, "can't map I/O space\n"); 154 return; 155 } 156 157 sc->sc_poll = 1; 158 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 159 /* No PCI IRQ */ 160 aprint_normal_dev(self, "interrupting at SMI\n"); 161 } else { 162 /* Install interrupt handler */ 163 if (pci_intr_map(pa, &ih) == 0) { 164 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf)); 165 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 166 ichsmb_intr, sc); 167 if (sc->sc_ih != NULL) { 168 aprint_normal_dev(self, "interrupting at %s\n", 169 intrstr); 170 sc->sc_poll = 0; 171 } 172 } 173 if (sc->sc_poll) 174 aprint_normal_dev(self, "polling\n"); 175 } 176 177 /* Attach I2C bus */ 178 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 179 sc->sc_i2c_tag.ic_cookie = sc; 180 sc->sc_i2c_tag.ic_acquire_bus = ichsmb_i2c_acquire_bus; 181 sc->sc_i2c_tag.ic_release_bus = ichsmb_i2c_release_bus; 182 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 183 184 memset(&iba, 0, sizeof(iba)); 185 iba.iba_type = I2C_TYPE_SMBUS; 186 iba.iba_tag = &sc->sc_i2c_tag; 187 config_found(self, &iba, iicbus_print); 188 189 if (!pmf_device_register(self, NULL, NULL)) 190 aprint_error_dev(self, "couldn't establish power handler\n"); 191 } 192 193 static int 194 ichsmb_i2c_acquire_bus(void *cookie, int flags) 195 { 196 struct ichsmb_softc *sc = cookie; 197 198 if (cold) 199 return 0; 200 201 mutex_enter(&sc->sc_i2c_mutex); 202 return 0; 203 } 204 205 static void 206 ichsmb_i2c_release_bus(void *cookie, int flags) 207 { 208 struct ichsmb_softc *sc = cookie; 209 210 if (cold) 211 return; 212 213 mutex_exit(&sc->sc_i2c_mutex); 214 } 215 216 static int 217 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 218 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 219 { 220 struct ichsmb_softc *sc = cookie; 221 const uint8_t *b; 222 uint8_t ctl = 0, st; 223 int retries; 224 char fbuf[64]; 225 226 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 227 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 228 len, flags)); 229 230 /* Clear status bits */ 231 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 232 LPCIB_SMB_HS_INTR | LPCIB_SMB_HS_DEVERR | 233 LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED); 234 bus_space_barrier(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 1, 235 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 236 237 /* Wait for bus to be idle */ 238 for (retries = 100; retries > 0; retries--) { 239 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 240 if (!(st & LPCIB_SMB_HS_BUSY)) 241 break; 242 DELAY(ICHIIC_DELAY); 243 } 244 #ifdef ICHIIC_DEBUG 245 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 246 printf("%s: exec: st 0x%s\n", device_xname(sc->sc_dev), fbuf); 247 #endif 248 if (st & LPCIB_SMB_HS_BUSY) 249 return (1); 250 251 if (cold || sc->sc_poll) 252 flags |= I2C_F_POLL; 253 254 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 255 (cmdlen == 0 && len > 1)) 256 return (1); 257 258 /* Setup transfer */ 259 sc->sc_i2c_xfer.op = op; 260 sc->sc_i2c_xfer.buf = buf; 261 sc->sc_i2c_xfer.len = len; 262 sc->sc_i2c_xfer.flags = flags; 263 sc->sc_i2c_xfer.error = 0; 264 265 /* Set slave address and transfer direction */ 266 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 267 LPCIB_SMB_TXSLVA_ADDR(addr) | 268 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 269 270 b = (const uint8_t *)cmdbuf; 271 if (cmdlen > 0) 272 /* Set command byte */ 273 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 274 275 if (I2C_OP_WRITE_P(op)) { 276 /* Write data */ 277 b = buf; 278 if (cmdlen == 0 && len == 1) 279 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 280 LPCIB_SMB_HCMD, b[0]); 281 else if (len > 0) 282 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 283 LPCIB_SMB_HD0, b[0]); 284 if (len > 1) 285 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 286 LPCIB_SMB_HD1, b[1]); 287 } 288 289 /* Set SMBus command */ 290 if (cmdlen == 0) { 291 if (len == 0) 292 ctl = LPCIB_SMB_HC_CMD_QUICK; 293 else 294 ctl = LPCIB_SMB_HC_CMD_BYTE; 295 } else if (len == 1) 296 ctl = LPCIB_SMB_HC_CMD_BDATA; 297 else if (len == 2) 298 ctl = LPCIB_SMB_HC_CMD_WDATA; 299 300 if ((flags & I2C_F_POLL) == 0) 301 ctl |= LPCIB_SMB_HC_INTREN; 302 303 /* Start transaction */ 304 ctl |= LPCIB_SMB_HC_START; 305 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 306 307 if (flags & I2C_F_POLL) { 308 /* Poll for completion */ 309 DELAY(ICHIIC_DELAY); 310 for (retries = 1000; retries > 0; retries--) { 311 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 312 LPCIB_SMB_HS); 313 if ((st & LPCIB_SMB_HS_BUSY) == 0) 314 break; 315 DELAY(ICHIIC_DELAY); 316 } 317 if (st & LPCIB_SMB_HS_BUSY) 318 goto timeout; 319 ichsmb_intr(sc); 320 } else { 321 /* Wait for interrupt */ 322 if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz)) 323 goto timeout; 324 } 325 326 if (sc->sc_i2c_xfer.error) 327 return (1); 328 329 return (0); 330 331 timeout: 332 /* 333 * Transfer timeout. Kill the transaction and clear status bits. 334 */ 335 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 336 aprint_error_dev(sc->sc_dev, 337 "exec: op %d, addr 0x%02x, cmdlen %zd, len %zd, " 338 "flags 0x%02x: timeout, status 0x%s\n", 339 op, addr, cmdlen, len, flags, fbuf); 340 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 341 LPCIB_SMB_HC_KILL); 342 DELAY(ICHIIC_DELAY); 343 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 344 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 345 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 346 aprint_error_dev(sc->sc_dev, "abort failed, status 0x%s\n", 347 fbuf); 348 } 349 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 350 return (1); 351 } 352 353 static int 354 ichsmb_intr(void *arg) 355 { 356 struct ichsmb_softc *sc = arg; 357 uint8_t st; 358 uint8_t *b; 359 size_t len; 360 #ifdef ICHIIC_DEBUG 361 char fbuf[64]; 362 #endif 363 364 /* Read status */ 365 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 366 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 367 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 368 LPCIB_SMB_HS_SMBAL | LPCIB_SMB_HS_BDONE)) == 0) 369 /* Interrupt was not for us */ 370 return (0); 371 372 #ifdef ICHIIC_DEBUG 373 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 374 printf("%s: intr st 0x%s\n", device_xname(sc->sc_dev), fbuf); 375 #endif 376 377 /* Clear status bits */ 378 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 379 380 /* Check for errors */ 381 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 382 sc->sc_i2c_xfer.error = 1; 383 goto done; 384 } 385 386 if (st & LPCIB_SMB_HS_INTR) { 387 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 388 goto done; 389 390 /* Read data */ 391 b = sc->sc_i2c_xfer.buf; 392 len = sc->sc_i2c_xfer.len; 393 if (len > 0) 394 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 395 LPCIB_SMB_HD0); 396 if (len > 1) 397 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 398 LPCIB_SMB_HD1); 399 } 400 401 done: 402 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 403 wakeup(sc); 404 return (1); 405 } 406
Indexes created Thu Oct 02 14:10:14 GMT 2025