ichsmb.c revision 1.31
1 /* $NetBSD: ichsmb.c,v 1.31 2013/07/18 03:14:09 msaitoh Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.18 2007/05/03 09:36:26 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.31 2013/07/18 03:14:09 msaitoh Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/ic/i82801lpcreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #ifdef ICHIIC_DEBUG 45 #define DPRINTF(x) printf x 46 #else 47 #define DPRINTF(x) 48 #endif 49 50 #define ICHIIC_DELAY 100 51 #define ICHIIC_TIMEOUT 1 52 53 struct ichsmb_softc { 54 device_t sc_dev; 55 56 bus_space_tag_t sc_iot; 57 bus_space_handle_t sc_ioh; 58 void * sc_ih; 59 int sc_poll; 60 61 struct i2c_controller sc_i2c_tag; 62 kmutex_t sc_i2c_mutex; 63 struct { 64 i2c_op_t op; 65 void * buf; 66 size_t len; 67 int flags; 68 volatile int error; 69 } sc_i2c_xfer; 70 }; 71 72 static int ichsmb_match(device_t, cfdata_t, void *); 73 static void ichsmb_attach(device_t, device_t, void *); 74 75 static int ichsmb_i2c_acquire_bus(void *, int); 76 static void ichsmb_i2c_release_bus(void *, int); 77 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 78 size_t, void *, size_t, int); 79 80 static int ichsmb_intr(void *); 81 82 83 CFATTACH_DECL_NEW(ichsmb, sizeof(struct ichsmb_softc), 84 ichsmb_match, ichsmb_attach, NULL, NULL); 85 86 87 static int 88 ichsmb_match(device_t parent, cfdata_t match, void *aux) 89 { 90 struct pci_attach_args *pa = aux; 91 92 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 93 switch (PCI_PRODUCT(pa->pa_id)) { 94 case PCI_PRODUCT_INTEL_6300ESB_SMB: 95 case PCI_PRODUCT_INTEL_63XXESB_SMB: 96 case PCI_PRODUCT_INTEL_82801AA_SMB: 97 case PCI_PRODUCT_INTEL_82801AB_SMB: 98 case PCI_PRODUCT_INTEL_82801BA_SMB: 99 case PCI_PRODUCT_INTEL_82801CA_SMB: 100 case PCI_PRODUCT_INTEL_82801DB_SMB: 101 case PCI_PRODUCT_INTEL_82801E_SMB: 102 case PCI_PRODUCT_INTEL_82801EB_SMB: 103 case PCI_PRODUCT_INTEL_82801FB_SMB: 104 case PCI_PRODUCT_INTEL_82801G_SMB: 105 case PCI_PRODUCT_INTEL_82801H_SMB: 106 case PCI_PRODUCT_INTEL_82801I_SMB: 107 case PCI_PRODUCT_INTEL_82801JD_SMB: 108 case PCI_PRODUCT_INTEL_82801JI_SMB: 109 case PCI_PRODUCT_INTEL_3400_SMB: 110 case PCI_PRODUCT_INTEL_6SERIES_SMB: 111 case PCI_PRODUCT_INTEL_7SERIES_SMB: 112 case PCI_PRODUCT_INTEL_8SERIES_SMB: 113 case PCI_PRODUCT_INTEL_C600_SMBUS: 114 case PCI_PRODUCT_INTEL_C600_SMB_0: 115 case PCI_PRODUCT_INTEL_C600_SMB_1: 116 case PCI_PRODUCT_INTEL_C600_SMB_2: 117 return 1; 118 } 119 } 120 return 0; 121 } 122 123 static void 124 ichsmb_attach(device_t parent, device_t self, void *aux) 125 { 126 struct ichsmb_softc *sc = device_private(self); 127 struct pci_attach_args *pa = aux; 128 struct i2cbus_attach_args iba; 129 pcireg_t conf; 130 bus_size_t iosize; 131 pci_intr_handle_t ih; 132 const char *intrstr = NULL; 133 134 sc->sc_dev = self; 135 136 pci_aprint_devinfo(pa, NULL); 137 138 /* Read configuration */ 139 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 140 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 141 142 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 143 aprint_error_dev(self, "SMBus disabled\n"); 144 return; 145 } 146 147 /* Map I/O space */ 148 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 149 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize)) { 150 aprint_error_dev(self, "can't map I/O space\n"); 151 return; 152 } 153 154 sc->sc_poll = 1; 155 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 156 /* No PCI IRQ */ 157 aprint_normal_dev(self, "interrupting at SMI\n"); 158 } else { 159 /* Install interrupt handler */ 160 if (pci_intr_map(pa, &ih) == 0) { 161 intrstr = pci_intr_string(pa->pa_pc, ih); 162 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 163 ichsmb_intr, sc); 164 if (sc->sc_ih != NULL) { 165 aprint_normal_dev(self, "interrupting at %s\n", 166 intrstr); 167 sc->sc_poll = 0; 168 } 169 } 170 if (sc->sc_poll) 171 aprint_normal_dev(self, "polling\n"); 172 } 173 174 /* Attach I2C bus */ 175 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 176 sc->sc_i2c_tag.ic_cookie = sc; 177 sc->sc_i2c_tag.ic_acquire_bus = ichsmb_i2c_acquire_bus; 178 sc->sc_i2c_tag.ic_release_bus = ichsmb_i2c_release_bus; 179 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 180 181 memset(&iba, 0, sizeof(iba)); 182 iba.iba_type = I2C_TYPE_SMBUS; 183 iba.iba_tag = &sc->sc_i2c_tag; 184 config_found(self, &iba, iicbus_print); 185 186 if (!pmf_device_register(self, NULL, NULL)) 187 aprint_error_dev(self, "couldn't establish power handler\n"); 188 } 189 190 static int 191 ichsmb_i2c_acquire_bus(void *cookie, int flags) 192 { 193 struct ichsmb_softc *sc = cookie; 194 195 if (cold) 196 return 0; 197 198 mutex_enter(&sc->sc_i2c_mutex); 199 return 0; 200 } 201 202 static void 203 ichsmb_i2c_release_bus(void *cookie, int flags) 204 { 205 struct ichsmb_softc *sc = cookie; 206 207 if (cold) 208 return; 209 210 mutex_exit(&sc->sc_i2c_mutex); 211 } 212 213 static int 214 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 215 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 216 { 217 struct ichsmb_softc *sc = cookie; 218 const uint8_t *b; 219 uint8_t ctl = 0, st; 220 int retries; 221 char fbuf[64]; 222 223 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 224 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 225 len, flags)); 226 227 /* Wait for bus to be idle */ 228 for (retries = 100; retries > 0; retries--) { 229 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 230 if (!(st & LPCIB_SMB_HS_BUSY)) 231 break; 232 DELAY(ICHIIC_DELAY); 233 } 234 #ifdef ICHIIC_DEBUG 235 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 236 printf("%s: exec: st 0x%s\n", device_xname(sc->sc_dev), fbuf); 237 #endif 238 if (st & LPCIB_SMB_HS_BUSY) 239 return (1); 240 241 if (cold || sc->sc_poll) 242 flags |= I2C_F_POLL; 243 244 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 245 (cmdlen == 0 && len > 1)) 246 return (1); 247 248 /* Setup transfer */ 249 sc->sc_i2c_xfer.op = op; 250 sc->sc_i2c_xfer.buf = buf; 251 sc->sc_i2c_xfer.len = len; 252 sc->sc_i2c_xfer.flags = flags; 253 sc->sc_i2c_xfer.error = 0; 254 255 /* Set slave address and transfer direction */ 256 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 257 LPCIB_SMB_TXSLVA_ADDR(addr) | 258 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 259 260 b = (const uint8_t *)cmdbuf; 261 if (cmdlen > 0) 262 /* Set command byte */ 263 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 264 265 if (I2C_OP_WRITE_P(op)) { 266 /* Write data */ 267 b = buf; 268 if (cmdlen == 0 && len == 1) 269 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 270 LPCIB_SMB_HCMD, b[0]); 271 else if (len > 0) 272 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 273 LPCIB_SMB_HD0, b[0]); 274 if (len > 1) 275 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 276 LPCIB_SMB_HD1, b[1]); 277 } 278 279 /* Set SMBus command */ 280 if (cmdlen == 0) { 281 if (len == 0) 282 ctl = LPCIB_SMB_HC_CMD_QUICK; 283 else 284 ctl = LPCIB_SMB_HC_CMD_BYTE; 285 } else if (len == 1) 286 ctl = LPCIB_SMB_HC_CMD_BDATA; 287 else if (len == 2) 288 ctl = LPCIB_SMB_HC_CMD_WDATA; 289 290 if ((flags & I2C_F_POLL) == 0) 291 ctl |= LPCIB_SMB_HC_INTREN; 292 293 /* Start transaction */ 294 ctl |= LPCIB_SMB_HC_START; 295 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 296 297 if (flags & I2C_F_POLL) { 298 /* Poll for completion */ 299 DELAY(ICHIIC_DELAY); 300 for (retries = 1000; retries > 0; retries--) { 301 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 302 LPCIB_SMB_HS); 303 if ((st & LPCIB_SMB_HS_BUSY) == 0) 304 break; 305 DELAY(ICHIIC_DELAY); 306 } 307 if (st & LPCIB_SMB_HS_BUSY) 308 goto timeout; 309 ichsmb_intr(sc); 310 } else { 311 /* Wait for interrupt */ 312 if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz)) 313 goto timeout; 314 } 315 316 if (sc->sc_i2c_xfer.error) 317 return (1); 318 319 return (0); 320 321 timeout: 322 /* 323 * Transfer timeout. Kill the transaction and clear status bits. 324 */ 325 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 326 aprint_error_dev(sc->sc_dev, 327 "exec: op %d, addr 0x%02x, cmdlen %zd, len %zd, " 328 "flags 0x%02x: timeout, status 0x%s\n", 329 op, addr, cmdlen, len, flags, fbuf); 330 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 331 LPCIB_SMB_HC_KILL); 332 DELAY(ICHIIC_DELAY); 333 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 334 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 335 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 336 aprint_error_dev(sc->sc_dev, "abort failed, status 0x%s\n", 337 fbuf); 338 } 339 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 340 return (1); 341 } 342 343 static int 344 ichsmb_intr(void *arg) 345 { 346 struct ichsmb_softc *sc = arg; 347 uint8_t st; 348 uint8_t *b; 349 size_t len; 350 #ifdef ICHIIC_DEBUG 351 char fbuf[64]; 352 #endif 353 354 /* Read status */ 355 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 356 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 357 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 358 LPCIB_SMB_HS_SMBAL | LPCIB_SMB_HS_BDONE)) == 0) 359 /* Interrupt was not for us */ 360 return (0); 361 362 #ifdef ICHIIC_DEBUG 363 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 364 printf("%s: intr st 0x%s\n", device_xname(sc->sc_dev), fbuf); 365 #endif 366 367 /* Clear status bits */ 368 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 369 370 /* Check for errors */ 371 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 372 sc->sc_i2c_xfer.error = 1; 373 goto done; 374 } 375 376 if (st & LPCIB_SMB_HS_INTR) { 377 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 378 goto done; 379 380 /* Read data */ 381 b = sc->sc_i2c_xfer.buf; 382 len = sc->sc_i2c_xfer.len; 383 if (len > 0) 384 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 385 LPCIB_SMB_HD0); 386 if (len > 1) 387 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 388 LPCIB_SMB_HD1); 389 } 390 391 done: 392 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 393 wakeup(sc); 394 return (1); 395 } 396
Indexes created Thu Oct 02 14:10:14 GMT 2025