ichsmb.c revision 1.32
1 /* $NetBSD: ichsmb.c,v 1.32 2013/07/18 22:14:54 soren Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.18 2007/05/03 09:36:26 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.32 2013/07/18 22:14:54 soren Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/ic/i82801lpcreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #ifdef ICHIIC_DEBUG 45 #define DPRINTF(x) printf x 46 #else 47 #define DPRINTF(x) 48 #endif 49 50 #define ICHIIC_DELAY 100 51 #define ICHIIC_TIMEOUT 1 52 53 struct ichsmb_softc { 54 device_t sc_dev; 55 56 bus_space_tag_t sc_iot; 57 bus_space_handle_t sc_ioh; 58 void * sc_ih; 59 int sc_poll; 60 61 struct i2c_controller sc_i2c_tag; 62 kmutex_t sc_i2c_mutex; 63 struct { 64 i2c_op_t op; 65 void * buf; 66 size_t len; 67 int flags; 68 volatile int error; 69 } sc_i2c_xfer; 70 }; 71 72 static int ichsmb_match(device_t, cfdata_t, void *); 73 static void ichsmb_attach(device_t, device_t, void *); 74 75 static int ichsmb_i2c_acquire_bus(void *, int); 76 static void ichsmb_i2c_release_bus(void *, int); 77 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 78 size_t, void *, size_t, int); 79 80 static int ichsmb_intr(void *); 81 82 83 CFATTACH_DECL_NEW(ichsmb, sizeof(struct ichsmb_softc), 84 ichsmb_match, ichsmb_attach, NULL, NULL); 85 86 87 static int 88 ichsmb_match(device_t parent, cfdata_t match, void *aux) 89 { 90 struct pci_attach_args *pa = aux; 91 92 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 93 switch (PCI_PRODUCT(pa->pa_id)) { 94 case PCI_PRODUCT_INTEL_6300ESB_SMB: 95 case PCI_PRODUCT_INTEL_63XXESB_SMB: 96 case PCI_PRODUCT_INTEL_82801AA_SMB: 97 case PCI_PRODUCT_INTEL_82801AB_SMB: 98 case PCI_PRODUCT_INTEL_82801BA_SMB: 99 case PCI_PRODUCT_INTEL_82801CA_SMB: 100 case PCI_PRODUCT_INTEL_82801DB_SMB: 101 case PCI_PRODUCT_INTEL_82801E_SMB: 102 case PCI_PRODUCT_INTEL_82801EB_SMB: 103 case PCI_PRODUCT_INTEL_82801FB_SMB: 104 case PCI_PRODUCT_INTEL_82801G_SMB: 105 case PCI_PRODUCT_INTEL_82801H_SMB: 106 case PCI_PRODUCT_INTEL_82801I_SMB: 107 case PCI_PRODUCT_INTEL_82801JD_SMB: 108 case PCI_PRODUCT_INTEL_82801JI_SMB: 109 case PCI_PRODUCT_INTEL_3400_SMB: 110 case PCI_PRODUCT_INTEL_6SERIES_SMB: 111 case PCI_PRODUCT_INTEL_7SERIES_SMB: 112 case PCI_PRODUCT_INTEL_8SERIES_SMB: 113 case PCI_PRODUCT_INTEL_C600_SMBUS: 114 case PCI_PRODUCT_INTEL_C600_SMB_0: 115 case PCI_PRODUCT_INTEL_C600_SMB_1: 116 case PCI_PRODUCT_INTEL_C600_SMB_2: 117 return 1; 118 } 119 } 120 return 0; 121 } 122 123 static void 124 ichsmb_attach(device_t parent, device_t self, void *aux) 125 { 126 struct ichsmb_softc *sc = device_private(self); 127 struct pci_attach_args *pa = aux; 128 struct i2cbus_attach_args iba; 129 pcireg_t conf; 130 bus_size_t iosize; 131 pci_intr_handle_t ih; 132 const char *intrstr = NULL; 133 134 sc->sc_dev = self; 135 136 pci_aprint_devinfo(pa, NULL); 137 138 /* Read configuration */ 139 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 140 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 141 142 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 143 aprint_error_dev(self, "SMBus disabled\n"); 144 return; 145 } 146 147 /* Map I/O space */ 148 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 149 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize)) { 150 aprint_error_dev(self, "can't map I/O space\n"); 151 return; 152 } 153 154 sc->sc_poll = 1; 155 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 156 /* No PCI IRQ */ 157 aprint_normal_dev(self, "interrupting at SMI\n"); 158 } else { 159 /* Install interrupt handler */ 160 if (pci_intr_map(pa, &ih) == 0) { 161 intrstr = pci_intr_string(pa->pa_pc, ih); 162 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 163 ichsmb_intr, sc); 164 if (sc->sc_ih != NULL) { 165 aprint_normal_dev(self, "interrupting at %s\n", 166 intrstr); 167 sc->sc_poll = 0; 168 } 169 } 170 if (sc->sc_poll) 171 aprint_normal_dev(self, "polling\n"); 172 } 173 174 /* Attach I2C bus */ 175 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 176 sc->sc_i2c_tag.ic_cookie = sc; 177 sc->sc_i2c_tag.ic_acquire_bus = ichsmb_i2c_acquire_bus; 178 sc->sc_i2c_tag.ic_release_bus = ichsmb_i2c_release_bus; 179 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 180 181 memset(&iba, 0, sizeof(iba)); 182 iba.iba_type = I2C_TYPE_SMBUS; 183 iba.iba_tag = &sc->sc_i2c_tag; 184 config_found(self, &iba, iicbus_print); 185 186 if (!pmf_device_register(self, NULL, NULL)) 187 aprint_error_dev(self, "couldn't establish power handler\n"); 188 } 189 190 static int 191 ichsmb_i2c_acquire_bus(void *cookie, int flags) 192 { 193 struct ichsmb_softc *sc = cookie; 194 195 if (cold) 196 return 0; 197 198 mutex_enter(&sc->sc_i2c_mutex); 199 return 0; 200 } 201 202 static void 203 ichsmb_i2c_release_bus(void *cookie, int flags) 204 { 205 struct ichsmb_softc *sc = cookie; 206 207 if (cold) 208 return; 209 210 mutex_exit(&sc->sc_i2c_mutex); 211 } 212 213 static int 214 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 215 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 216 { 217 struct ichsmb_softc *sc = cookie; 218 const uint8_t *b; 219 uint8_t ctl = 0, st; 220 int retries; 221 char fbuf[64]; 222 223 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 224 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 225 len, flags)); 226 227 /* Clear status bits */ 228 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 229 LPCIB_SMB_HS_INTR | LPCIB_SMB_HS_DEVERR | 230 LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED); 231 bus_space_barrier(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 1, 232 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 233 234 /* Wait for bus to be idle */ 235 for (retries = 100; retries > 0; retries--) { 236 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 237 if (!(st & LPCIB_SMB_HS_BUSY)) 238 break; 239 DELAY(ICHIIC_DELAY); 240 } 241 #ifdef ICHIIC_DEBUG 242 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 243 printf("%s: exec: st 0x%s\n", device_xname(sc->sc_dev), fbuf); 244 #endif 245 if (st & LPCIB_SMB_HS_BUSY) 246 return (1); 247 248 if (cold || sc->sc_poll) 249 flags |= I2C_F_POLL; 250 251 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 252 (cmdlen == 0 && len > 1)) 253 return (1); 254 255 /* Setup transfer */ 256 sc->sc_i2c_xfer.op = op; 257 sc->sc_i2c_xfer.buf = buf; 258 sc->sc_i2c_xfer.len = len; 259 sc->sc_i2c_xfer.flags = flags; 260 sc->sc_i2c_xfer.error = 0; 261 262 /* Set slave address and transfer direction */ 263 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 264 LPCIB_SMB_TXSLVA_ADDR(addr) | 265 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 266 267 b = (const uint8_t *)cmdbuf; 268 if (cmdlen > 0) 269 /* Set command byte */ 270 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 271 272 if (I2C_OP_WRITE_P(op)) { 273 /* Write data */ 274 b = buf; 275 if (cmdlen == 0 && len == 1) 276 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 277 LPCIB_SMB_HCMD, b[0]); 278 else if (len > 0) 279 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 280 LPCIB_SMB_HD0, b[0]); 281 if (len > 1) 282 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 283 LPCIB_SMB_HD1, b[1]); 284 } 285 286 /* Set SMBus command */ 287 if (cmdlen == 0) { 288 if (len == 0) 289 ctl = LPCIB_SMB_HC_CMD_QUICK; 290 else 291 ctl = LPCIB_SMB_HC_CMD_BYTE; 292 } else if (len == 1) 293 ctl = LPCIB_SMB_HC_CMD_BDATA; 294 else if (len == 2) 295 ctl = LPCIB_SMB_HC_CMD_WDATA; 296 297 if ((flags & I2C_F_POLL) == 0) 298 ctl |= LPCIB_SMB_HC_INTREN; 299 300 /* Start transaction */ 301 ctl |= LPCIB_SMB_HC_START; 302 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 303 304 if (flags & I2C_F_POLL) { 305 /* Poll for completion */ 306 DELAY(ICHIIC_DELAY); 307 for (retries = 1000; retries > 0; retries--) { 308 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 309 LPCIB_SMB_HS); 310 if ((st & LPCIB_SMB_HS_BUSY) == 0) 311 break; 312 DELAY(ICHIIC_DELAY); 313 } 314 if (st & LPCIB_SMB_HS_BUSY) 315 goto timeout; 316 ichsmb_intr(sc); 317 } else { 318 /* Wait for interrupt */ 319 if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz)) 320 goto timeout; 321 } 322 323 if (sc->sc_i2c_xfer.error) 324 return (1); 325 326 return (0); 327 328 timeout: 329 /* 330 * Transfer timeout. Kill the transaction and clear status bits. 331 */ 332 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 333 aprint_error_dev(sc->sc_dev, 334 "exec: op %d, addr 0x%02x, cmdlen %zd, len %zd, " 335 "flags 0x%02x: timeout, status 0x%s\n", 336 op, addr, cmdlen, len, flags, fbuf); 337 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 338 LPCIB_SMB_HC_KILL); 339 DELAY(ICHIIC_DELAY); 340 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 341 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 342 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 343 aprint_error_dev(sc->sc_dev, "abort failed, status 0x%s\n", 344 fbuf); 345 } 346 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 347 return (1); 348 } 349 350 static int 351 ichsmb_intr(void *arg) 352 { 353 struct ichsmb_softc *sc = arg; 354 uint8_t st; 355 uint8_t *b; 356 size_t len; 357 #ifdef ICHIIC_DEBUG 358 char fbuf[64]; 359 #endif 360 361 /* Read status */ 362 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 363 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 364 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 365 LPCIB_SMB_HS_SMBAL | LPCIB_SMB_HS_BDONE)) == 0) 366 /* Interrupt was not for us */ 367 return (0); 368 369 #ifdef ICHIIC_DEBUG 370 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 371 printf("%s: intr st 0x%s\n", device_xname(sc->sc_dev), fbuf); 372 #endif 373 374 /* Clear status bits */ 375 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 376 377 /* Check for errors */ 378 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 379 sc->sc_i2c_xfer.error = 1; 380 goto done; 381 } 382 383 if (st & LPCIB_SMB_HS_INTR) { 384 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 385 goto done; 386 387 /* Read data */ 388 b = sc->sc_i2c_xfer.buf; 389 len = sc->sc_i2c_xfer.len; 390 if (len > 0) 391 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 392 LPCIB_SMB_HD0); 393 if (len > 1) 394 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 395 LPCIB_SMB_HD1); 396 } 397 398 done: 399 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 400 wakeup(sc); 401 return (1); 402 } 403
Indexes created Thu Oct 02 14:10:14 GMT 2025