ichsmb.c revision 1.34
1 /* $NetBSD: ichsmb.c,v 1.34 2013/12/28 11:15:43 msaitoh Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.18 2007/05/03 09:36:26 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.34 2013/12/28 11:15:43 msaitoh Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/ic/i82801lpcreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #ifdef ICHIIC_DEBUG 45 #define DPRINTF(x) printf x 46 #else 47 #define DPRINTF(x) 48 #endif 49 50 #define ICHIIC_DELAY 100 51 #define ICHIIC_TIMEOUT 1 52 53 struct ichsmb_softc { 54 device_t sc_dev; 55 56 bus_space_tag_t sc_iot; 57 bus_space_handle_t sc_ioh; 58 void * sc_ih; 59 int sc_poll; 60 61 struct i2c_controller sc_i2c_tag; 62 kmutex_t sc_i2c_mutex; 63 struct { 64 i2c_op_t op; 65 void * buf; 66 size_t len; 67 int flags; 68 volatile int error; 69 } sc_i2c_xfer; 70 }; 71 72 static int ichsmb_match(device_t, cfdata_t, void *); 73 static void ichsmb_attach(device_t, device_t, void *); 74 75 static int ichsmb_i2c_acquire_bus(void *, int); 76 static void ichsmb_i2c_release_bus(void *, int); 77 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 78 size_t, void *, size_t, int); 79 80 static int ichsmb_intr(void *); 81 82 83 CFATTACH_DECL_NEW(ichsmb, sizeof(struct ichsmb_softc), 84 ichsmb_match, ichsmb_attach, NULL, NULL); 85 86 87 static int 88 ichsmb_match(device_t parent, cfdata_t match, void *aux) 89 { 90 struct pci_attach_args *pa = aux; 91 92 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 93 switch (PCI_PRODUCT(pa->pa_id)) { 94 case PCI_PRODUCT_INTEL_6300ESB_SMB: 95 case PCI_PRODUCT_INTEL_63XXESB_SMB: 96 case PCI_PRODUCT_INTEL_82801AA_SMB: 97 case PCI_PRODUCT_INTEL_82801AB_SMB: 98 case PCI_PRODUCT_INTEL_82801BA_SMB: 99 case PCI_PRODUCT_INTEL_82801CA_SMB: 100 case PCI_PRODUCT_INTEL_82801DB_SMB: 101 case PCI_PRODUCT_INTEL_82801E_SMB: 102 case PCI_PRODUCT_INTEL_82801EB_SMB: 103 case PCI_PRODUCT_INTEL_82801FB_SMB: 104 case PCI_PRODUCT_INTEL_82801G_SMB: 105 case PCI_PRODUCT_INTEL_82801H_SMB: 106 case PCI_PRODUCT_INTEL_82801I_SMB: 107 case PCI_PRODUCT_INTEL_82801JD_SMB: 108 case PCI_PRODUCT_INTEL_82801JI_SMB: 109 case PCI_PRODUCT_INTEL_3400_SMB: 110 case PCI_PRODUCT_INTEL_6SERIES_SMB: 111 case PCI_PRODUCT_INTEL_7SERIES_SMB: 112 case PCI_PRODUCT_INTEL_8SERIES_SMB: 113 case PCI_PRODUCT_INTEL_CORE4G_M_SMB: 114 case PCI_PRODUCT_INTEL_C600_SMBUS: 115 case PCI_PRODUCT_INTEL_C600_SMB_0: 116 case PCI_PRODUCT_INTEL_C600_SMB_1: 117 case PCI_PRODUCT_INTEL_C600_SMB_2: 118 case PCI_PRODUCT_INTEL_C2000_PCU_SMBUS: 119 return 1; 120 } 121 } 122 return 0; 123 } 124 125 static void 126 ichsmb_attach(device_t parent, device_t self, void *aux) 127 { 128 struct ichsmb_softc *sc = device_private(self); 129 struct pci_attach_args *pa = aux; 130 struct i2cbus_attach_args iba; 131 pcireg_t conf; 132 bus_size_t iosize; 133 pci_intr_handle_t ih; 134 const char *intrstr = NULL; 135 136 sc->sc_dev = self; 137 138 pci_aprint_devinfo(pa, NULL); 139 140 /* Read configuration */ 141 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 142 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 143 144 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 145 aprint_error_dev(self, "SMBus disabled\n"); 146 return; 147 } 148 149 /* Map I/O space */ 150 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 151 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize)) { 152 aprint_error_dev(self, "can't map I/O space\n"); 153 return; 154 } 155 156 sc->sc_poll = 1; 157 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 158 /* No PCI IRQ */ 159 aprint_normal_dev(self, "interrupting at SMI\n"); 160 } else { 161 /* Install interrupt handler */ 162 if (pci_intr_map(pa, &ih) == 0) { 163 intrstr = pci_intr_string(pa->pa_pc, ih); 164 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 165 ichsmb_intr, sc); 166 if (sc->sc_ih != NULL) { 167 aprint_normal_dev(self, "interrupting at %s\n", 168 intrstr); 169 sc->sc_poll = 0; 170 } 171 } 172 if (sc->sc_poll) 173 aprint_normal_dev(self, "polling\n"); 174 } 175 176 /* Attach I2C bus */ 177 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 178 sc->sc_i2c_tag.ic_cookie = sc; 179 sc->sc_i2c_tag.ic_acquire_bus = ichsmb_i2c_acquire_bus; 180 sc->sc_i2c_tag.ic_release_bus = ichsmb_i2c_release_bus; 181 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 182 183 memset(&iba, 0, sizeof(iba)); 184 iba.iba_type = I2C_TYPE_SMBUS; 185 iba.iba_tag = &sc->sc_i2c_tag; 186 config_found(self, &iba, iicbus_print); 187 188 if (!pmf_device_register(self, NULL, NULL)) 189 aprint_error_dev(self, "couldn't establish power handler\n"); 190 } 191 192 static int 193 ichsmb_i2c_acquire_bus(void *cookie, int flags) 194 { 195 struct ichsmb_softc *sc = cookie; 196 197 if (cold) 198 return 0; 199 200 mutex_enter(&sc->sc_i2c_mutex); 201 return 0; 202 } 203 204 static void 205 ichsmb_i2c_release_bus(void *cookie, int flags) 206 { 207 struct ichsmb_softc *sc = cookie; 208 209 if (cold) 210 return; 211 212 mutex_exit(&sc->sc_i2c_mutex); 213 } 214 215 static int 216 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 217 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 218 { 219 struct ichsmb_softc *sc = cookie; 220 const uint8_t *b; 221 uint8_t ctl = 0, st; 222 int retries; 223 char fbuf[64]; 224 225 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 226 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 227 len, flags)); 228 229 /* Clear status bits */ 230 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 231 LPCIB_SMB_HS_INTR | LPCIB_SMB_HS_DEVERR | 232 LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED); 233 bus_space_barrier(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 1, 234 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 235 236 /* Wait for bus to be idle */ 237 for (retries = 100; retries > 0; retries--) { 238 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 239 if (!(st & LPCIB_SMB_HS_BUSY)) 240 break; 241 DELAY(ICHIIC_DELAY); 242 } 243 #ifdef ICHIIC_DEBUG 244 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 245 printf("%s: exec: st 0x%s\n", device_xname(sc->sc_dev), fbuf); 246 #endif 247 if (st & LPCIB_SMB_HS_BUSY) 248 return (1); 249 250 if (cold || sc->sc_poll) 251 flags |= I2C_F_POLL; 252 253 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 254 (cmdlen == 0 && len > 1)) 255 return (1); 256 257 /* Setup transfer */ 258 sc->sc_i2c_xfer.op = op; 259 sc->sc_i2c_xfer.buf = buf; 260 sc->sc_i2c_xfer.len = len; 261 sc->sc_i2c_xfer.flags = flags; 262 sc->sc_i2c_xfer.error = 0; 263 264 /* Set slave address and transfer direction */ 265 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 266 LPCIB_SMB_TXSLVA_ADDR(addr) | 267 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 268 269 b = (const uint8_t *)cmdbuf; 270 if (cmdlen > 0) 271 /* Set command byte */ 272 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 273 274 if (I2C_OP_WRITE_P(op)) { 275 /* Write data */ 276 b = buf; 277 if (cmdlen == 0 && len == 1) 278 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 279 LPCIB_SMB_HCMD, b[0]); 280 else if (len > 0) 281 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 282 LPCIB_SMB_HD0, b[0]); 283 if (len > 1) 284 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 285 LPCIB_SMB_HD1, b[1]); 286 } 287 288 /* Set SMBus command */ 289 if (cmdlen == 0) { 290 if (len == 0) 291 ctl = LPCIB_SMB_HC_CMD_QUICK; 292 else 293 ctl = LPCIB_SMB_HC_CMD_BYTE; 294 } else if (len == 1) 295 ctl = LPCIB_SMB_HC_CMD_BDATA; 296 else if (len == 2) 297 ctl = LPCIB_SMB_HC_CMD_WDATA; 298 299 if ((flags & I2C_F_POLL) == 0) 300 ctl |= LPCIB_SMB_HC_INTREN; 301 302 /* Start transaction */ 303 ctl |= LPCIB_SMB_HC_START; 304 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 305 306 if (flags & I2C_F_POLL) { 307 /* Poll for completion */ 308 DELAY(ICHIIC_DELAY); 309 for (retries = 1000; retries > 0; retries--) { 310 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 311 LPCIB_SMB_HS); 312 if ((st & LPCIB_SMB_HS_BUSY) == 0) 313 break; 314 DELAY(ICHIIC_DELAY); 315 } 316 if (st & LPCIB_SMB_HS_BUSY) 317 goto timeout; 318 ichsmb_intr(sc); 319 } else { 320 /* Wait for interrupt */ 321 if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz)) 322 goto timeout; 323 } 324 325 if (sc->sc_i2c_xfer.error) 326 return (1); 327 328 return (0); 329 330 timeout: 331 /* 332 * Transfer timeout. Kill the transaction and clear status bits. 333 */ 334 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 335 aprint_error_dev(sc->sc_dev, 336 "exec: op %d, addr 0x%02x, cmdlen %zd, len %zd, " 337 "flags 0x%02x: timeout, status 0x%s\n", 338 op, addr, cmdlen, len, flags, fbuf); 339 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 340 LPCIB_SMB_HC_KILL); 341 DELAY(ICHIIC_DELAY); 342 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 343 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 344 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 345 aprint_error_dev(sc->sc_dev, "abort failed, status 0x%s\n", 346 fbuf); 347 } 348 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 349 return (1); 350 } 351 352 static int 353 ichsmb_intr(void *arg) 354 { 355 struct ichsmb_softc *sc = arg; 356 uint8_t st; 357 uint8_t *b; 358 size_t len; 359 #ifdef ICHIIC_DEBUG 360 char fbuf[64]; 361 #endif 362 363 /* Read status */ 364 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 365 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 366 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 367 LPCIB_SMB_HS_SMBAL | LPCIB_SMB_HS_BDONE)) == 0) 368 /* Interrupt was not for us */ 369 return (0); 370 371 #ifdef ICHIIC_DEBUG 372 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 373 printf("%s: intr st 0x%s\n", device_xname(sc->sc_dev), fbuf); 374 #endif 375 376 /* Clear status bits */ 377 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 378 379 /* Check for errors */ 380 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 381 sc->sc_i2c_xfer.error = 1; 382 goto done; 383 } 384 385 if (st & LPCIB_SMB_HS_INTR) { 386 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 387 goto done; 388 389 /* Read data */ 390 b = sc->sc_i2c_xfer.buf; 391 len = sc->sc_i2c_xfer.len; 392 if (len > 0) 393 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 394 LPCIB_SMB_HD0); 395 if (len > 1) 396 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 397 LPCIB_SMB_HD1); 398 } 399 400 done: 401 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 402 wakeup(sc); 403 return (1); 404 } 405
Indexes created Thu Oct 02 14:10:14 GMT 2025