ichsmb.c revision 1.35.2.1
1 /* $NetBSD: ichsmb.c,v 1.35.2.1 2014/08/10 06:54:54 tls Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.18 2007/05/03 09:36:26 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.35.2.1 2014/08/10 06:54:54 tls Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/ic/i82801lpcreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #ifdef ICHIIC_DEBUG 45 #define DPRINTF(x) printf x 46 #else 47 #define DPRINTF(x) 48 #endif 49 50 #define ICHIIC_DELAY 100 51 #define ICHIIC_TIMEOUT 1 52 53 struct ichsmb_softc { 54 device_t sc_dev; 55 56 bus_space_tag_t sc_iot; 57 bus_space_handle_t sc_ioh; 58 void * sc_ih; 59 int sc_poll; 60 61 struct i2c_controller sc_i2c_tag; 62 kmutex_t sc_i2c_mutex; 63 struct { 64 i2c_op_t op; 65 void * buf; 66 size_t len; 67 int flags; 68 volatile int error; 69 } sc_i2c_xfer; 70 }; 71 72 static int ichsmb_match(device_t, cfdata_t, void *); 73 static void ichsmb_attach(device_t, device_t, void *); 74 75 static int ichsmb_i2c_acquire_bus(void *, int); 76 static void ichsmb_i2c_release_bus(void *, int); 77 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 78 size_t, void *, size_t, int); 79 80 static int ichsmb_intr(void *); 81 82 83 CFATTACH_DECL_NEW(ichsmb, sizeof(struct ichsmb_softc), 84 ichsmb_match, ichsmb_attach, NULL, NULL); 85 86 87 static int 88 ichsmb_match(device_t parent, cfdata_t match, void *aux) 89 { 90 struct pci_attach_args *pa = aux; 91 92 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 93 switch (PCI_PRODUCT(pa->pa_id)) { 94 case PCI_PRODUCT_INTEL_6300ESB_SMB: 95 case PCI_PRODUCT_INTEL_63XXESB_SMB: 96 case PCI_PRODUCT_INTEL_82801AA_SMB: 97 case PCI_PRODUCT_INTEL_82801AB_SMB: 98 case PCI_PRODUCT_INTEL_82801BA_SMB: 99 case PCI_PRODUCT_INTEL_82801CA_SMB: 100 case PCI_PRODUCT_INTEL_82801DB_SMB: 101 case PCI_PRODUCT_INTEL_82801E_SMB: 102 case PCI_PRODUCT_INTEL_82801EB_SMB: 103 case PCI_PRODUCT_INTEL_82801FB_SMB: 104 case PCI_PRODUCT_INTEL_82801G_SMB: 105 case PCI_PRODUCT_INTEL_82801H_SMB: 106 case PCI_PRODUCT_INTEL_82801I_SMB: 107 case PCI_PRODUCT_INTEL_82801JD_SMB: 108 case PCI_PRODUCT_INTEL_82801JI_SMB: 109 case PCI_PRODUCT_INTEL_3400_SMB: 110 case PCI_PRODUCT_INTEL_6SERIES_SMB: 111 case PCI_PRODUCT_INTEL_7SERIES_SMB: 112 case PCI_PRODUCT_INTEL_8SERIES_SMB: 113 case PCI_PRODUCT_INTEL_CORE4G_M_SMB: 114 case PCI_PRODUCT_INTEL_BAYTRAIL_PCU_SMB: 115 case PCI_PRODUCT_INTEL_C600_SMBUS: 116 case PCI_PRODUCT_INTEL_C600_SMB_0: 117 case PCI_PRODUCT_INTEL_C600_SMB_1: 118 case PCI_PRODUCT_INTEL_C600_SMB_2: 119 case PCI_PRODUCT_INTEL_EP80579_SMB: 120 case PCI_PRODUCT_INTEL_DH89XX_SMB: 121 case PCI_PRODUCT_INTEL_C2000_PCU_SMBUS: 122 return 1; 123 } 124 } 125 return 0; 126 } 127 128 static void 129 ichsmb_attach(device_t parent, device_t self, void *aux) 130 { 131 struct ichsmb_softc *sc = device_private(self); 132 struct pci_attach_args *pa = aux; 133 struct i2cbus_attach_args iba; 134 pcireg_t conf; 135 bus_size_t iosize; 136 pci_intr_handle_t ih; 137 const char *intrstr = NULL; 138 char intrbuf[PCI_INTRSTR_LEN]; 139 140 sc->sc_dev = self; 141 142 pci_aprint_devinfo(pa, NULL); 143 144 /* Read configuration */ 145 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 146 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 147 148 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 149 aprint_error_dev(self, "SMBus disabled\n"); 150 goto out; 151 } 152 153 /* Map I/O space */ 154 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 155 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize)) { 156 aprint_error_dev(self, "can't map I/O space\n"); 157 goto out; 158 } 159 160 sc->sc_poll = 1; 161 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 162 /* No PCI IRQ */ 163 aprint_normal_dev(self, "interrupting at SMI\n"); 164 } else { 165 /* Install interrupt handler */ 166 if (pci_intr_map(pa, &ih) == 0) { 167 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf)); 168 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 169 ichsmb_intr, sc); 170 if (sc->sc_ih != NULL) { 171 aprint_normal_dev(self, "interrupting at %s\n", 172 intrstr); 173 sc->sc_poll = 0; 174 } 175 } 176 if (sc->sc_poll) 177 aprint_normal_dev(self, "polling\n"); 178 } 179 180 /* Attach I2C bus */ 181 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 182 sc->sc_i2c_tag.ic_cookie = sc; 183 sc->sc_i2c_tag.ic_acquire_bus = ichsmb_i2c_acquire_bus; 184 sc->sc_i2c_tag.ic_release_bus = ichsmb_i2c_release_bus; 185 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 186 187 memset(&iba, 0, sizeof(iba)); 188 iba.iba_type = I2C_TYPE_SMBUS; 189 iba.iba_tag = &sc->sc_i2c_tag; 190 config_found(self, &iba, iicbus_print); 191 192 out: if (!pmf_device_register(self, NULL, NULL)) 193 aprint_error_dev(self, "couldn't establish power handler\n"); 194 } 195 196 static int 197 ichsmb_i2c_acquire_bus(void *cookie, int flags) 198 { 199 struct ichsmb_softc *sc = cookie; 200 201 if (cold) 202 return 0; 203 204 mutex_enter(&sc->sc_i2c_mutex); 205 return 0; 206 } 207 208 static void 209 ichsmb_i2c_release_bus(void *cookie, int flags) 210 { 211 struct ichsmb_softc *sc = cookie; 212 213 if (cold) 214 return; 215 216 mutex_exit(&sc->sc_i2c_mutex); 217 } 218 219 static int 220 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 221 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 222 { 223 struct ichsmb_softc *sc = cookie; 224 const uint8_t *b; 225 uint8_t ctl = 0, st; 226 int retries; 227 char fbuf[64]; 228 229 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 230 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 231 len, flags)); 232 233 /* Clear status bits */ 234 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 235 LPCIB_SMB_HS_INTR | LPCIB_SMB_HS_DEVERR | 236 LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED); 237 bus_space_barrier(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 1, 238 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 239 240 /* Wait for bus to be idle */ 241 for (retries = 100; retries > 0; retries--) { 242 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 243 if (!(st & LPCIB_SMB_HS_BUSY)) 244 break; 245 DELAY(ICHIIC_DELAY); 246 } 247 #ifdef ICHIIC_DEBUG 248 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 249 printf("%s: exec: st 0x%s\n", device_xname(sc->sc_dev), fbuf); 250 #endif 251 if (st & LPCIB_SMB_HS_BUSY) 252 return (1); 253 254 if (cold || sc->sc_poll) 255 flags |= I2C_F_POLL; 256 257 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 258 (cmdlen == 0 && len > 1)) 259 return (1); 260 261 /* Setup transfer */ 262 sc->sc_i2c_xfer.op = op; 263 sc->sc_i2c_xfer.buf = buf; 264 sc->sc_i2c_xfer.len = len; 265 sc->sc_i2c_xfer.flags = flags; 266 sc->sc_i2c_xfer.error = 0; 267 268 /* Set slave address and transfer direction */ 269 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 270 LPCIB_SMB_TXSLVA_ADDR(addr) | 271 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 272 273 b = (const uint8_t *)cmdbuf; 274 if (cmdlen > 0) 275 /* Set command byte */ 276 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 277 278 if (I2C_OP_WRITE_P(op)) { 279 /* Write data */ 280 b = buf; 281 if (cmdlen == 0 && len == 1) 282 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 283 LPCIB_SMB_HCMD, b[0]); 284 else if (len > 0) 285 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 286 LPCIB_SMB_HD0, b[0]); 287 if (len > 1) 288 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 289 LPCIB_SMB_HD1, b[1]); 290 } 291 292 /* Set SMBus command */ 293 if (cmdlen == 0) { 294 if (len == 0) 295 ctl = LPCIB_SMB_HC_CMD_QUICK; 296 else 297 ctl = LPCIB_SMB_HC_CMD_BYTE; 298 } else if (len == 1) 299 ctl = LPCIB_SMB_HC_CMD_BDATA; 300 else if (len == 2) 301 ctl = LPCIB_SMB_HC_CMD_WDATA; 302 303 if ((flags & I2C_F_POLL) == 0) 304 ctl |= LPCIB_SMB_HC_INTREN; 305 306 /* Start transaction */ 307 ctl |= LPCIB_SMB_HC_START; 308 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 309 310 if (flags & I2C_F_POLL) { 311 /* Poll for completion */ 312 DELAY(ICHIIC_DELAY); 313 for (retries = 1000; retries > 0; retries--) { 314 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 315 LPCIB_SMB_HS); 316 if ((st & LPCIB_SMB_HS_BUSY) == 0) 317 break; 318 DELAY(ICHIIC_DELAY); 319 } 320 if (st & LPCIB_SMB_HS_BUSY) 321 goto timeout; 322 ichsmb_intr(sc); 323 } else { 324 /* Wait for interrupt */ 325 if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz)) 326 goto timeout; 327 } 328 329 if (sc->sc_i2c_xfer.error) 330 return (1); 331 332 return (0); 333 334 timeout: 335 /* 336 * Transfer timeout. Kill the transaction and clear status bits. 337 */ 338 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 339 aprint_error_dev(sc->sc_dev, 340 "exec: op %d, addr 0x%02x, cmdlen %zd, len %zd, " 341 "flags 0x%02x: timeout, status 0x%s\n", 342 op, addr, cmdlen, len, flags, fbuf); 343 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 344 LPCIB_SMB_HC_KILL); 345 DELAY(ICHIIC_DELAY); 346 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 347 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 348 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 349 aprint_error_dev(sc->sc_dev, "abort failed, status 0x%s\n", 350 fbuf); 351 } 352 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 353 return (1); 354 } 355 356 static int 357 ichsmb_intr(void *arg) 358 { 359 struct ichsmb_softc *sc = arg; 360 uint8_t st; 361 uint8_t *b; 362 size_t len; 363 #ifdef ICHIIC_DEBUG 364 char fbuf[64]; 365 #endif 366 367 /* Read status */ 368 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 369 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 370 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 371 LPCIB_SMB_HS_SMBAL | LPCIB_SMB_HS_BDONE)) == 0) 372 /* Interrupt was not for us */ 373 return (0); 374 375 #ifdef ICHIIC_DEBUG 376 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 377 printf("%s: intr st 0x%s\n", device_xname(sc->sc_dev), fbuf); 378 #endif 379 380 /* Clear status bits */ 381 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 382 383 /* Check for errors */ 384 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 385 sc->sc_i2c_xfer.error = 1; 386 goto done; 387 } 388 389 if (st & LPCIB_SMB_HS_INTR) { 390 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 391 goto done; 392 393 /* Read data */ 394 b = sc->sc_i2c_xfer.buf; 395 len = sc->sc_i2c_xfer.len; 396 if (len > 0) 397 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 398 LPCIB_SMB_HD0); 399 if (len > 1) 400 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 401 LPCIB_SMB_HD1); 402 } 403 404 done: 405 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 406 wakeup(sc); 407 return (1); 408 } 409
Indexes created Thu Oct 02 14:10:14 GMT 2025