ichsmb.c revision 1.37.2.2
1 /* $NetBSD: ichsmb.c,v 1.37.2.2 2015/04/30 19:27:20 snj Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.18 2007/05/03 09:36:26 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.37.2.2 2015/04/30 19:27:20 snj Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/ic/i82801lpcreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #ifdef ICHIIC_DEBUG 45 #define DPRINTF(x) printf x 46 #else 47 #define DPRINTF(x) 48 #endif 49 50 #define ICHIIC_DELAY 100 51 #define ICHIIC_TIMEOUT 1 52 53 struct ichsmb_softc { 54 device_t sc_dev; 55 56 bus_space_tag_t sc_iot; 57 bus_space_handle_t sc_ioh; 58 void * sc_ih; 59 int sc_poll; 60 61 struct i2c_controller sc_i2c_tag; 62 kmutex_t sc_i2c_mutex; 63 struct { 64 i2c_op_t op; 65 void * buf; 66 size_t len; 67 int flags; 68 volatile int error; 69 } sc_i2c_xfer; 70 }; 71 72 static int ichsmb_match(device_t, cfdata_t, void *); 73 static void ichsmb_attach(device_t, device_t, void *); 74 75 static int ichsmb_i2c_acquire_bus(void *, int); 76 static void ichsmb_i2c_release_bus(void *, int); 77 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 78 size_t, void *, size_t, int); 79 80 static int ichsmb_intr(void *); 81 82 83 CFATTACH_DECL_NEW(ichsmb, sizeof(struct ichsmb_softc), 84 ichsmb_match, ichsmb_attach, NULL, NULL); 85 86 87 static int 88 ichsmb_match(device_t parent, cfdata_t match, void *aux) 89 { 90 struct pci_attach_args *pa = aux; 91 92 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 93 switch (PCI_PRODUCT(pa->pa_id)) { 94 case PCI_PRODUCT_INTEL_6300ESB_SMB: 95 case PCI_PRODUCT_INTEL_63XXESB_SMB: 96 case PCI_PRODUCT_INTEL_82801AA_SMB: 97 case PCI_PRODUCT_INTEL_82801AB_SMB: 98 case PCI_PRODUCT_INTEL_82801BA_SMB: 99 case PCI_PRODUCT_INTEL_82801CA_SMB: 100 case PCI_PRODUCT_INTEL_82801DB_SMB: 101 case PCI_PRODUCT_INTEL_82801E_SMB: 102 case PCI_PRODUCT_INTEL_82801EB_SMB: 103 case PCI_PRODUCT_INTEL_82801FB_SMB: 104 case PCI_PRODUCT_INTEL_82801G_SMB: 105 case PCI_PRODUCT_INTEL_82801H_SMB: 106 case PCI_PRODUCT_INTEL_82801I_SMB: 107 case PCI_PRODUCT_INTEL_82801JD_SMB: 108 case PCI_PRODUCT_INTEL_82801JI_SMB: 109 case PCI_PRODUCT_INTEL_3400_SMB: 110 case PCI_PRODUCT_INTEL_6SERIES_SMB: 111 case PCI_PRODUCT_INTEL_7SERIES_SMB: 112 case PCI_PRODUCT_INTEL_8SERIES_SMB: 113 case PCI_PRODUCT_INTEL_9SERIES_SMB: 114 case PCI_PRODUCT_INTEL_CORE4G_M_SMB: 115 case PCI_PRODUCT_INTEL_CORE5G_M_SMB: 116 case PCI_PRODUCT_INTEL_BAYTRAIL_PCU_SMB: 117 case PCI_PRODUCT_INTEL_C600_SMBUS: 118 case PCI_PRODUCT_INTEL_C600_SMB_0: 119 case PCI_PRODUCT_INTEL_C600_SMB_1: 120 case PCI_PRODUCT_INTEL_C600_SMB_2: 121 case PCI_PRODUCT_INTEL_C610_SMB: 122 case PCI_PRODUCT_INTEL_EP80579_SMB: 123 case PCI_PRODUCT_INTEL_DH89XXCC_SMB: 124 case PCI_PRODUCT_INTEL_DH89XXCL_SMB: 125 case PCI_PRODUCT_INTEL_C2000_PCU_SMBUS: 126 return 1; 127 } 128 } 129 return 0; 130 } 131 132 static void 133 ichsmb_attach(device_t parent, device_t self, void *aux) 134 { 135 struct ichsmb_softc *sc = device_private(self); 136 struct pci_attach_args *pa = aux; 137 struct i2cbus_attach_args iba; 138 pcireg_t conf; 139 bus_size_t iosize; 140 pci_intr_handle_t ih; 141 const char *intrstr = NULL; 142 char intrbuf[PCI_INTRSTR_LEN]; 143 144 sc->sc_dev = self; 145 146 pci_aprint_devinfo(pa, NULL); 147 148 /* Read configuration */ 149 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 150 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 151 152 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 153 aprint_error_dev(self, "SMBus disabled\n"); 154 goto out; 155 } 156 157 /* Map I/O space */ 158 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 159 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize)) { 160 aprint_error_dev(self, "can't map I/O space\n"); 161 goto out; 162 } 163 164 sc->sc_poll = 1; 165 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 166 /* No PCI IRQ */ 167 aprint_normal_dev(self, "interrupting at SMI\n"); 168 } else { 169 /* Install interrupt handler */ 170 if (pci_intr_map(pa, &ih) == 0) { 171 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf)); 172 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 173 ichsmb_intr, sc); 174 if (sc->sc_ih != NULL) { 175 aprint_normal_dev(self, "interrupting at %s\n", 176 intrstr); 177 sc->sc_poll = 0; 178 } 179 } 180 if (sc->sc_poll) 181 aprint_normal_dev(self, "polling\n"); 182 } 183 184 /* Attach I2C bus */ 185 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 186 sc->sc_i2c_tag.ic_cookie = sc; 187 sc->sc_i2c_tag.ic_acquire_bus = ichsmb_i2c_acquire_bus; 188 sc->sc_i2c_tag.ic_release_bus = ichsmb_i2c_release_bus; 189 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 190 191 memset(&iba, 0, sizeof(iba)); 192 iba.iba_type = I2C_TYPE_SMBUS; 193 iba.iba_tag = &sc->sc_i2c_tag; 194 config_found(self, &iba, iicbus_print); 195 196 out: if (!pmf_device_register(self, NULL, NULL)) 197 aprint_error_dev(self, "couldn't establish power handler\n"); 198 } 199 200 static int 201 ichsmb_i2c_acquire_bus(void *cookie, int flags) 202 { 203 struct ichsmb_softc *sc = cookie; 204 205 if (cold) 206 return 0; 207 208 mutex_enter(&sc->sc_i2c_mutex); 209 return 0; 210 } 211 212 static void 213 ichsmb_i2c_release_bus(void *cookie, int flags) 214 { 215 struct ichsmb_softc *sc = cookie; 216 217 if (cold) 218 return; 219 220 mutex_exit(&sc->sc_i2c_mutex); 221 } 222 223 static int 224 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 225 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 226 { 227 struct ichsmb_softc *sc = cookie; 228 const uint8_t *b; 229 uint8_t ctl = 0, st; 230 int retries; 231 char fbuf[64]; 232 233 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 234 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 235 len, flags)); 236 237 /* Clear status bits */ 238 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 239 LPCIB_SMB_HS_INTR | LPCIB_SMB_HS_DEVERR | 240 LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED); 241 bus_space_barrier(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 1, 242 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 243 244 /* Wait for bus to be idle */ 245 for (retries = 100; retries > 0; retries--) { 246 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 247 if (!(st & LPCIB_SMB_HS_BUSY)) 248 break; 249 DELAY(ICHIIC_DELAY); 250 } 251 #ifdef ICHIIC_DEBUG 252 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 253 printf("%s: exec: st 0x%s\n", device_xname(sc->sc_dev), fbuf); 254 #endif 255 if (st & LPCIB_SMB_HS_BUSY) 256 return (1); 257 258 if (cold || sc->sc_poll) 259 flags |= I2C_F_POLL; 260 261 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 262 (cmdlen == 0 && len > 1)) 263 return (1); 264 265 /* Setup transfer */ 266 sc->sc_i2c_xfer.op = op; 267 sc->sc_i2c_xfer.buf = buf; 268 sc->sc_i2c_xfer.len = len; 269 sc->sc_i2c_xfer.flags = flags; 270 sc->sc_i2c_xfer.error = 0; 271 272 /* Set slave address and transfer direction */ 273 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 274 LPCIB_SMB_TXSLVA_ADDR(addr) | 275 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 276 277 b = (const uint8_t *)cmdbuf; 278 if (cmdlen > 0) 279 /* Set command byte */ 280 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 281 282 if (I2C_OP_WRITE_P(op)) { 283 /* Write data */ 284 b = buf; 285 if (cmdlen == 0 && len == 1) 286 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 287 LPCIB_SMB_HCMD, b[0]); 288 else if (len > 0) 289 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 290 LPCIB_SMB_HD0, b[0]); 291 if (len > 1) 292 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 293 LPCIB_SMB_HD1, b[1]); 294 } 295 296 /* Set SMBus command */ 297 if (cmdlen == 0) { 298 if (len == 0) 299 ctl = LPCIB_SMB_HC_CMD_QUICK; 300 else 301 ctl = LPCIB_SMB_HC_CMD_BYTE; 302 } else if (len == 1) 303 ctl = LPCIB_SMB_HC_CMD_BDATA; 304 else if (len == 2) 305 ctl = LPCIB_SMB_HC_CMD_WDATA; 306 307 if ((flags & I2C_F_POLL) == 0) 308 ctl |= LPCIB_SMB_HC_INTREN; 309 310 /* Start transaction */ 311 ctl |= LPCIB_SMB_HC_START; 312 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 313 314 if (flags & I2C_F_POLL) { 315 /* Poll for completion */ 316 DELAY(ICHIIC_DELAY); 317 for (retries = 1000; retries > 0; retries--) { 318 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 319 LPCIB_SMB_HS); 320 if ((st & LPCIB_SMB_HS_BUSY) == 0) 321 break; 322 DELAY(ICHIIC_DELAY); 323 } 324 if (st & LPCIB_SMB_HS_BUSY) 325 goto timeout; 326 ichsmb_intr(sc); 327 } else { 328 /* Wait for interrupt */ 329 if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz)) 330 goto timeout; 331 } 332 333 if (sc->sc_i2c_xfer.error) 334 return (1); 335 336 return (0); 337 338 timeout: 339 /* 340 * Transfer timeout. Kill the transaction and clear status bits. 341 */ 342 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 343 aprint_error_dev(sc->sc_dev, 344 "exec: op %d, addr 0x%02x, cmdlen %zd, len %zd, " 345 "flags 0x%02x: timeout, status 0x%s\n", 346 op, addr, cmdlen, len, flags, fbuf); 347 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 348 LPCIB_SMB_HC_KILL); 349 DELAY(ICHIIC_DELAY); 350 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 351 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 352 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 353 aprint_error_dev(sc->sc_dev, "abort failed, status 0x%s\n", 354 fbuf); 355 } 356 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 357 return (1); 358 } 359 360 static int 361 ichsmb_intr(void *arg) 362 { 363 struct ichsmb_softc *sc = arg; 364 uint8_t st; 365 uint8_t *b; 366 size_t len; 367 #ifdef ICHIIC_DEBUG 368 char fbuf[64]; 369 #endif 370 371 /* Read status */ 372 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 373 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 374 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 375 LPCIB_SMB_HS_SMBAL | LPCIB_SMB_HS_BDONE)) == 0) 376 /* Interrupt was not for us */ 377 return (0); 378 379 #ifdef ICHIIC_DEBUG 380 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 381 printf("%s: intr st 0x%s\n", device_xname(sc->sc_dev), fbuf); 382 #endif 383 384 /* Clear status bits */ 385 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 386 387 /* Check for errors */ 388 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 389 sc->sc_i2c_xfer.error = 1; 390 goto done; 391 } 392 393 if (st & LPCIB_SMB_HS_INTR) { 394 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 395 goto done; 396 397 /* Read data */ 398 b = sc->sc_i2c_xfer.buf; 399 len = sc->sc_i2c_xfer.len; 400 if (len > 0) 401 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 402 LPCIB_SMB_HD0); 403 if (len > 1) 404 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 405 LPCIB_SMB_HD1); 406 } 407 408 done: 409 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 410 wakeup(sc); 411 return (1); 412 } 413
Indexes created Thu Oct 02 14:10:14 GMT 2025