ichsmb.c revision 1.37.2.2.4.1
1 /* $NetBSD: ichsmb.c,v 1.37.2.2.4.1 2017/01/18 08:46:27 skrll Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.18 2007/05/03 09:36:26 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.37.2.2.4.1 2017/01/18 08:46:27 skrll Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/ic/i82801lpcreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #ifdef ICHIIC_DEBUG 45 #define DPRINTF(x) printf x 46 #else 47 #define DPRINTF(x) 48 #endif 49 50 #define ICHIIC_DELAY 100 51 #define ICHIIC_TIMEOUT 1 52 53 struct ichsmb_softc { 54 device_t sc_dev; 55 56 bus_space_tag_t sc_iot; 57 bus_space_handle_t sc_ioh; 58 void * sc_ih; 59 int sc_poll; 60 61 struct i2c_controller sc_i2c_tag; 62 kmutex_t sc_i2c_mutex; 63 struct { 64 i2c_op_t op; 65 void * buf; 66 size_t len; 67 int flags; 68 volatile int error; 69 } sc_i2c_xfer; 70 }; 71 72 static int ichsmb_match(device_t, cfdata_t, void *); 73 static void ichsmb_attach(device_t, device_t, void *); 74 75 static int ichsmb_i2c_acquire_bus(void *, int); 76 static void ichsmb_i2c_release_bus(void *, int); 77 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 78 size_t, void *, size_t, int); 79 80 static int ichsmb_intr(void *); 81 82 83 CFATTACH_DECL_NEW(ichsmb, sizeof(struct ichsmb_softc), 84 ichsmb_match, ichsmb_attach, NULL, NULL); 85 86 87 static int 88 ichsmb_match(device_t parent, cfdata_t match, void *aux) 89 { 90 struct pci_attach_args *pa = aux; 91 92 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 93 switch (PCI_PRODUCT(pa->pa_id)) { 94 case PCI_PRODUCT_INTEL_6300ESB_SMB: 95 case PCI_PRODUCT_INTEL_63XXESB_SMB: 96 case PCI_PRODUCT_INTEL_82801AA_SMB: 97 case PCI_PRODUCT_INTEL_82801AB_SMB: 98 case PCI_PRODUCT_INTEL_82801BA_SMB: 99 case PCI_PRODUCT_INTEL_82801CA_SMB: 100 case PCI_PRODUCT_INTEL_82801DB_SMB: 101 case PCI_PRODUCT_INTEL_82801E_SMB: 102 case PCI_PRODUCT_INTEL_82801EB_SMB: 103 case PCI_PRODUCT_INTEL_82801FB_SMB: 104 case PCI_PRODUCT_INTEL_82801G_SMB: 105 case PCI_PRODUCT_INTEL_82801H_SMB: 106 case PCI_PRODUCT_INTEL_82801I_SMB: 107 case PCI_PRODUCT_INTEL_82801JD_SMB: 108 case PCI_PRODUCT_INTEL_82801JI_SMB: 109 case PCI_PRODUCT_INTEL_3400_SMB: 110 case PCI_PRODUCT_INTEL_6SERIES_SMB: 111 case PCI_PRODUCT_INTEL_7SERIES_SMB: 112 case PCI_PRODUCT_INTEL_8SERIES_SMB: 113 case PCI_PRODUCT_INTEL_9SERIES_SMB: 114 case PCI_PRODUCT_INTEL_100SERIES_SMB: 115 case PCI_PRODUCT_INTEL_CORE4G_M_SMB: 116 case PCI_PRODUCT_INTEL_CORE5G_M_SMB: 117 case PCI_PRODUCT_INTEL_BAYTRAIL_PCU_SMB: 118 case PCI_PRODUCT_INTEL_BSW_PCU_SMB: 119 case PCI_PRODUCT_INTEL_C600_SMBUS: 120 case PCI_PRODUCT_INTEL_C600_SMB_0: 121 case PCI_PRODUCT_INTEL_C600_SMB_1: 122 case PCI_PRODUCT_INTEL_C600_SMB_2: 123 case PCI_PRODUCT_INTEL_C610_SMB: 124 case PCI_PRODUCT_INTEL_EP80579_SMB: 125 case PCI_PRODUCT_INTEL_DH89XXCC_SMB: 126 case PCI_PRODUCT_INTEL_DH89XXCL_SMB: 127 case PCI_PRODUCT_INTEL_C2000_PCU_SMBUS: 128 return 1; 129 } 130 } 131 return 0; 132 } 133 134 static void 135 ichsmb_attach(device_t parent, device_t self, void *aux) 136 { 137 struct ichsmb_softc *sc = device_private(self); 138 struct pci_attach_args *pa = aux; 139 struct i2cbus_attach_args iba; 140 pcireg_t conf; 141 bus_size_t iosize; 142 pci_intr_handle_t ih; 143 const char *intrstr = NULL; 144 char intrbuf[PCI_INTRSTR_LEN]; 145 146 sc->sc_dev = self; 147 148 pci_aprint_devinfo(pa, NULL); 149 150 /* Read configuration */ 151 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 152 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 153 154 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 155 aprint_error_dev(self, "SMBus disabled\n"); 156 goto out; 157 } 158 159 /* Map I/O space */ 160 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 161 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize)) { 162 aprint_error_dev(self, "can't map I/O space\n"); 163 goto out; 164 } 165 166 sc->sc_poll = 1; 167 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 168 /* No PCI IRQ */ 169 aprint_normal_dev(self, "interrupting at SMI\n"); 170 } else { 171 /* Install interrupt handler */ 172 if (pci_intr_map(pa, &ih) == 0) { 173 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf)); 174 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 175 ichsmb_intr, sc); 176 if (sc->sc_ih != NULL) { 177 aprint_normal_dev(self, "interrupting at %s\n", 178 intrstr); 179 sc->sc_poll = 0; 180 } 181 } 182 if (sc->sc_poll) 183 aprint_normal_dev(self, "polling\n"); 184 } 185 186 /* Attach I2C bus */ 187 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 188 sc->sc_i2c_tag.ic_cookie = sc; 189 sc->sc_i2c_tag.ic_acquire_bus = ichsmb_i2c_acquire_bus; 190 sc->sc_i2c_tag.ic_release_bus = ichsmb_i2c_release_bus; 191 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 192 193 memset(&iba, 0, sizeof(iba)); 194 iba.iba_type = I2C_TYPE_SMBUS; 195 iba.iba_tag = &sc->sc_i2c_tag; 196 config_found(self, &iba, iicbus_print); 197 198 out: if (!pmf_device_register(self, NULL, NULL)) 199 aprint_error_dev(self, "couldn't establish power handler\n"); 200 } 201 202 static int 203 ichsmb_i2c_acquire_bus(void *cookie, int flags) 204 { 205 struct ichsmb_softc *sc = cookie; 206 207 if (cold) 208 return 0; 209 210 mutex_enter(&sc->sc_i2c_mutex); 211 return 0; 212 } 213 214 static void 215 ichsmb_i2c_release_bus(void *cookie, int flags) 216 { 217 struct ichsmb_softc *sc = cookie; 218 219 if (cold) 220 return; 221 222 mutex_exit(&sc->sc_i2c_mutex); 223 } 224 225 static int 226 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 227 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 228 { 229 struct ichsmb_softc *sc = cookie; 230 const uint8_t *b; 231 uint8_t ctl = 0, st; 232 int retries; 233 char fbuf[64]; 234 235 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 236 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 237 len, flags)); 238 239 /* Clear status bits */ 240 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 241 LPCIB_SMB_HS_INTR | LPCIB_SMB_HS_DEVERR | 242 LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED); 243 bus_space_barrier(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 1, 244 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 245 246 /* Wait for bus to be idle */ 247 for (retries = 100; retries > 0; retries--) { 248 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 249 if (!(st & LPCIB_SMB_HS_BUSY)) 250 break; 251 DELAY(ICHIIC_DELAY); 252 } 253 #ifdef ICHIIC_DEBUG 254 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 255 printf("%s: exec: st 0x%s\n", device_xname(sc->sc_dev), fbuf); 256 #endif 257 if (st & LPCIB_SMB_HS_BUSY) 258 return (1); 259 260 if (cold || sc->sc_poll) 261 flags |= I2C_F_POLL; 262 263 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 264 (cmdlen == 0 && len > 1)) 265 return (1); 266 267 /* Setup transfer */ 268 sc->sc_i2c_xfer.op = op; 269 sc->sc_i2c_xfer.buf = buf; 270 sc->sc_i2c_xfer.len = len; 271 sc->sc_i2c_xfer.flags = flags; 272 sc->sc_i2c_xfer.error = 0; 273 274 /* Set slave address and transfer direction */ 275 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 276 LPCIB_SMB_TXSLVA_ADDR(addr) | 277 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 278 279 b = (const uint8_t *)cmdbuf; 280 if (cmdlen > 0) 281 /* Set command byte */ 282 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 283 284 if (I2C_OP_WRITE_P(op)) { 285 /* Write data */ 286 b = buf; 287 if (cmdlen == 0 && len == 1) 288 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 289 LPCIB_SMB_HCMD, b[0]); 290 else if (len > 0) 291 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 292 LPCIB_SMB_HD0, b[0]); 293 if (len > 1) 294 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 295 LPCIB_SMB_HD1, b[1]); 296 } 297 298 /* Set SMBus command */ 299 if (cmdlen == 0) { 300 if (len == 0) 301 ctl = LPCIB_SMB_HC_CMD_QUICK; 302 else 303 ctl = LPCIB_SMB_HC_CMD_BYTE; 304 } else if (len == 1) 305 ctl = LPCIB_SMB_HC_CMD_BDATA; 306 else if (len == 2) 307 ctl = LPCIB_SMB_HC_CMD_WDATA; 308 309 if ((flags & I2C_F_POLL) == 0) 310 ctl |= LPCIB_SMB_HC_INTREN; 311 312 /* Start transaction */ 313 ctl |= LPCIB_SMB_HC_START; 314 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 315 316 if (flags & I2C_F_POLL) { 317 /* Poll for completion */ 318 DELAY(ICHIIC_DELAY); 319 for (retries = 1000; retries > 0; retries--) { 320 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 321 LPCIB_SMB_HS); 322 if ((st & LPCIB_SMB_HS_BUSY) == 0) 323 break; 324 DELAY(ICHIIC_DELAY); 325 } 326 if (st & LPCIB_SMB_HS_BUSY) 327 goto timeout; 328 ichsmb_intr(sc); 329 } else { 330 /* Wait for interrupt */ 331 if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz)) 332 goto timeout; 333 } 334 335 if (sc->sc_i2c_xfer.error) 336 return (1); 337 338 return (0); 339 340 timeout: 341 /* 342 * Transfer timeout. Kill the transaction and clear status bits. 343 */ 344 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 345 aprint_error_dev(sc->sc_dev, 346 "exec: op %d, addr 0x%02x, cmdlen %zd, len %zd, " 347 "flags 0x%02x: timeout, status 0x%s\n", 348 op, addr, cmdlen, len, flags, fbuf); 349 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 350 LPCIB_SMB_HC_KILL); 351 DELAY(ICHIIC_DELAY); 352 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 353 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 354 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 355 aprint_error_dev(sc->sc_dev, "abort failed, status 0x%s\n", 356 fbuf); 357 } 358 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 359 return (1); 360 } 361 362 static int 363 ichsmb_intr(void *arg) 364 { 365 struct ichsmb_softc *sc = arg; 366 uint8_t st; 367 uint8_t *b; 368 size_t len; 369 #ifdef ICHIIC_DEBUG 370 char fbuf[64]; 371 #endif 372 373 /* Read status */ 374 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 375 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 376 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 377 LPCIB_SMB_HS_SMBAL | LPCIB_SMB_HS_BDONE)) == 0) 378 /* Interrupt was not for us */ 379 return (0); 380 381 #ifdef ICHIIC_DEBUG 382 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 383 printf("%s: intr st 0x%s\n", device_xname(sc->sc_dev), fbuf); 384 #endif 385 386 /* Clear status bits */ 387 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 388 389 /* Check for errors */ 390 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 391 sc->sc_i2c_xfer.error = 1; 392 goto done; 393 } 394 395 if (st & LPCIB_SMB_HS_INTR) { 396 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 397 goto done; 398 399 /* Read data */ 400 b = sc->sc_i2c_xfer.buf; 401 len = sc->sc_i2c_xfer.len; 402 if (len > 0) 403 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 404 LPCIB_SMB_HD0); 405 if (len > 1) 406 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 407 LPCIB_SMB_HD1); 408 } 409 410 done: 411 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 412 wakeup(sc); 413 return (1); 414 } 415
Indexes created Thu Oct 02 14:10:14 GMT 2025