ichsmb.c revision 1.37.4.2
1 /* $NetBSD: ichsmb.c,v 1.37.4.2 2015/06/06 14:40:09 skrll Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.18 2007/05/03 09:36:26 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.37.4.2 2015/06/06 14:40:09 skrll Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/ic/i82801lpcreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #ifdef ICHIIC_DEBUG 45 #define DPRINTF(x) printf x 46 #else 47 #define DPRINTF(x) 48 #endif 49 50 #define ICHIIC_DELAY 100 51 #define ICHIIC_TIMEOUT 1 52 53 struct ichsmb_softc { 54 device_t sc_dev; 55 56 bus_space_tag_t sc_iot; 57 bus_space_handle_t sc_ioh; 58 void * sc_ih; 59 int sc_poll; 60 61 struct i2c_controller sc_i2c_tag; 62 kmutex_t sc_i2c_mutex; 63 struct { 64 i2c_op_t op; 65 void * buf; 66 size_t len; 67 int flags; 68 volatile int error; 69 } sc_i2c_xfer; 70 device_t sc_i2c_device; 71 }; 72 73 static int ichsmb_match(device_t, cfdata_t, void *); 74 static void ichsmb_attach(device_t, device_t, void *); 75 static int ichsmb_rescan(device_t, const char *, const int *); 76 static void ichsmb_chdet(device_t, device_t); 77 78 static int ichsmb_i2c_acquire_bus(void *, int); 79 static void ichsmb_i2c_release_bus(void *, int); 80 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 81 size_t, void *, size_t, int); 82 83 static int ichsmb_intr(void *); 84 85 86 CFATTACH_DECL3_NEW(ichsmb, sizeof(struct ichsmb_softc), 87 ichsmb_match, ichsmb_attach, NULL, NULL, ichsmb_rescan, ichsmb_chdet, 0); 88 89 90 static int 91 ichsmb_match(device_t parent, cfdata_t match, void *aux) 92 { 93 struct pci_attach_args *pa = aux; 94 95 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 96 switch (PCI_PRODUCT(pa->pa_id)) { 97 case PCI_PRODUCT_INTEL_6300ESB_SMB: 98 case PCI_PRODUCT_INTEL_63XXESB_SMB: 99 case PCI_PRODUCT_INTEL_82801AA_SMB: 100 case PCI_PRODUCT_INTEL_82801AB_SMB: 101 case PCI_PRODUCT_INTEL_82801BA_SMB: 102 case PCI_PRODUCT_INTEL_82801CA_SMB: 103 case PCI_PRODUCT_INTEL_82801DB_SMB: 104 case PCI_PRODUCT_INTEL_82801E_SMB: 105 case PCI_PRODUCT_INTEL_82801EB_SMB: 106 case PCI_PRODUCT_INTEL_82801FB_SMB: 107 case PCI_PRODUCT_INTEL_82801G_SMB: 108 case PCI_PRODUCT_INTEL_82801H_SMB: 109 case PCI_PRODUCT_INTEL_82801I_SMB: 110 case PCI_PRODUCT_INTEL_82801JD_SMB: 111 case PCI_PRODUCT_INTEL_82801JI_SMB: 112 case PCI_PRODUCT_INTEL_3400_SMB: 113 case PCI_PRODUCT_INTEL_6SERIES_SMB: 114 case PCI_PRODUCT_INTEL_7SERIES_SMB: 115 case PCI_PRODUCT_INTEL_8SERIES_SMB: 116 case PCI_PRODUCT_INTEL_9SERIES_SMB: 117 case PCI_PRODUCT_INTEL_CORE4G_M_SMB: 118 case PCI_PRODUCT_INTEL_CORE5G_M_SMB: 119 case PCI_PRODUCT_INTEL_BAYTRAIL_PCU_SMB: 120 case PCI_PRODUCT_INTEL_C600_SMBUS: 121 case PCI_PRODUCT_INTEL_C600_SMB_0: 122 case PCI_PRODUCT_INTEL_C600_SMB_1: 123 case PCI_PRODUCT_INTEL_C600_SMB_2: 124 case PCI_PRODUCT_INTEL_C610_SMB: 125 case PCI_PRODUCT_INTEL_EP80579_SMB: 126 case PCI_PRODUCT_INTEL_DH89XXCC_SMB: 127 case PCI_PRODUCT_INTEL_DH89XXCL_SMB: 128 case PCI_PRODUCT_INTEL_C2000_PCU_SMBUS: 129 return 1; 130 } 131 } 132 return 0; 133 } 134 135 static void 136 ichsmb_attach(device_t parent, device_t self, void *aux) 137 { 138 struct ichsmb_softc *sc = device_private(self); 139 struct pci_attach_args *pa = aux; 140 pcireg_t conf; 141 bus_size_t iosize; 142 pci_intr_handle_t ih; 143 const char *intrstr = NULL; 144 char intrbuf[PCI_INTRSTR_LEN]; 145 int flags; 146 147 sc->sc_dev = self; 148 149 pci_aprint_devinfo(pa, NULL); 150 151 /* Read configuration */ 152 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 153 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 154 155 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 156 aprint_error_dev(self, "SMBus disabled\n"); 157 goto out; 158 } 159 160 /* Map I/O space */ 161 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 162 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize)) { 163 aprint_error_dev(self, "can't map I/O space\n"); 164 goto out; 165 } 166 167 sc->sc_poll = 1; 168 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 169 /* No PCI IRQ */ 170 aprint_normal_dev(self, "interrupting at SMI\n"); 171 } else { 172 /* Install interrupt handler */ 173 if (pci_intr_map(pa, &ih) == 0) { 174 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf)); 175 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 176 ichsmb_intr, sc); 177 if (sc->sc_ih != NULL) { 178 aprint_normal_dev(self, "interrupting at %s\n", 179 intrstr); 180 sc->sc_poll = 0; 181 } 182 } 183 if (sc->sc_poll) 184 aprint_normal_dev(self, "polling\n"); 185 } 186 187 sc->sc_i2c_device = NULL; 188 flags = 0; 189 ichsmb_rescan(self, "i2cbus", &flags); 190 191 out: if (!pmf_device_register(self, NULL, NULL)) 192 aprint_error_dev(self, "couldn't establish power handler\n"); 193 } 194 195 static int 196 ichsmb_rescan(device_t self, const char *ifattr, const int *flags) 197 { 198 struct ichsmb_softc *sc = device_private(self); 199 struct i2cbus_attach_args iba; 200 201 if (!ifattr_match(ifattr, "i2cbus")) 202 return 0; 203 204 if (sc->sc_i2c_device) 205 return 0; 206 207 /* Attach I2C bus */ 208 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 209 sc->sc_i2c_tag.ic_cookie = sc; 210 sc->sc_i2c_tag.ic_acquire_bus = ichsmb_i2c_acquire_bus; 211 sc->sc_i2c_tag.ic_release_bus = ichsmb_i2c_release_bus; 212 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 213 214 memset(&iba, 0, sizeof(iba)); 215 iba.iba_type = I2C_TYPE_SMBUS; 216 iba.iba_tag = &sc->sc_i2c_tag; 217 sc->sc_i2c_device = config_found_ia(self, ifattr, &iba, iicbus_print); 218 219 return 0; 220 } 221 222 static void 223 ichsmb_chdet(device_t self, device_t child) 224 { 225 struct ichsmb_softc *sc = device_private(self); 226 227 if (sc->sc_i2c_device == child) 228 sc->sc_i2c_device = NULL; 229 230 } 231 232 static int 233 ichsmb_i2c_acquire_bus(void *cookie, int flags) 234 { 235 struct ichsmb_softc *sc = cookie; 236 237 if (cold) 238 return 0; 239 240 mutex_enter(&sc->sc_i2c_mutex); 241 return 0; 242 } 243 244 static void 245 ichsmb_i2c_release_bus(void *cookie, int flags) 246 { 247 struct ichsmb_softc *sc = cookie; 248 249 if (cold) 250 return; 251 252 mutex_exit(&sc->sc_i2c_mutex); 253 } 254 255 static int 256 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 257 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 258 { 259 struct ichsmb_softc *sc = cookie; 260 const uint8_t *b; 261 uint8_t ctl = 0, st; 262 int retries; 263 char fbuf[64]; 264 265 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 266 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 267 len, flags)); 268 269 /* Clear status bits */ 270 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 271 LPCIB_SMB_HS_INTR | LPCIB_SMB_HS_DEVERR | 272 LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED); 273 bus_space_barrier(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 1, 274 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 275 276 /* Wait for bus to be idle */ 277 for (retries = 100; retries > 0; retries--) { 278 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 279 if (!(st & LPCIB_SMB_HS_BUSY)) 280 break; 281 DELAY(ICHIIC_DELAY); 282 } 283 #ifdef ICHIIC_DEBUG 284 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 285 printf("%s: exec: st 0x%s\n", device_xname(sc->sc_dev), fbuf); 286 #endif 287 if (st & LPCIB_SMB_HS_BUSY) 288 return (1); 289 290 if (cold || sc->sc_poll) 291 flags |= I2C_F_POLL; 292 293 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 294 (cmdlen == 0 && len > 1)) 295 return (1); 296 297 /* Setup transfer */ 298 sc->sc_i2c_xfer.op = op; 299 sc->sc_i2c_xfer.buf = buf; 300 sc->sc_i2c_xfer.len = len; 301 sc->sc_i2c_xfer.flags = flags; 302 sc->sc_i2c_xfer.error = 0; 303 304 /* Set slave address and transfer direction */ 305 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 306 LPCIB_SMB_TXSLVA_ADDR(addr) | 307 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 308 309 b = (const uint8_t *)cmdbuf; 310 if (cmdlen > 0) 311 /* Set command byte */ 312 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 313 314 if (I2C_OP_WRITE_P(op)) { 315 /* Write data */ 316 b = buf; 317 if (cmdlen == 0 && len == 1) 318 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 319 LPCIB_SMB_HCMD, b[0]); 320 else if (len > 0) 321 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 322 LPCIB_SMB_HD0, b[0]); 323 if (len > 1) 324 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 325 LPCIB_SMB_HD1, b[1]); 326 } 327 328 /* Set SMBus command */ 329 if (cmdlen == 0) { 330 if (len == 0) 331 ctl = LPCIB_SMB_HC_CMD_QUICK; 332 else 333 ctl = LPCIB_SMB_HC_CMD_BYTE; 334 } else if (len == 1) 335 ctl = LPCIB_SMB_HC_CMD_BDATA; 336 else if (len == 2) 337 ctl = LPCIB_SMB_HC_CMD_WDATA; 338 339 if ((flags & I2C_F_POLL) == 0) 340 ctl |= LPCIB_SMB_HC_INTREN; 341 342 /* Start transaction */ 343 ctl |= LPCIB_SMB_HC_START; 344 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 345 346 if (flags & I2C_F_POLL) { 347 /* Poll for completion */ 348 DELAY(ICHIIC_DELAY); 349 for (retries = 1000; retries > 0; retries--) { 350 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 351 LPCIB_SMB_HS); 352 if ((st & LPCIB_SMB_HS_BUSY) == 0) 353 break; 354 DELAY(ICHIIC_DELAY); 355 } 356 if (st & LPCIB_SMB_HS_BUSY) 357 goto timeout; 358 ichsmb_intr(sc); 359 } else { 360 /* Wait for interrupt */ 361 if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz)) 362 goto timeout; 363 } 364 365 if (sc->sc_i2c_xfer.error) 366 return (1); 367 368 return (0); 369 370 timeout: 371 /* 372 * Transfer timeout. Kill the transaction and clear status bits. 373 */ 374 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 375 aprint_error_dev(sc->sc_dev, 376 "exec: op %d, addr 0x%02x, cmdlen %zd, len %zd, " 377 "flags 0x%02x: timeout, status 0x%s\n", 378 op, addr, cmdlen, len, flags, fbuf); 379 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 380 LPCIB_SMB_HC_KILL); 381 DELAY(ICHIIC_DELAY); 382 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 383 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 384 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 385 aprint_error_dev(sc->sc_dev, "abort failed, status 0x%s\n", 386 fbuf); 387 } 388 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 389 return (1); 390 } 391 392 static int 393 ichsmb_intr(void *arg) 394 { 395 struct ichsmb_softc *sc = arg; 396 uint8_t st; 397 uint8_t *b; 398 size_t len; 399 #ifdef ICHIIC_DEBUG 400 char fbuf[64]; 401 #endif 402 403 /* Read status */ 404 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 405 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 406 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 407 LPCIB_SMB_HS_SMBAL | LPCIB_SMB_HS_BDONE)) == 0) 408 /* Interrupt was not for us */ 409 return (0); 410 411 #ifdef ICHIIC_DEBUG 412 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 413 printf("%s: intr st 0x%s\n", device_xname(sc->sc_dev), fbuf); 414 #endif 415 416 /* Clear status bits */ 417 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 418 419 /* Check for errors */ 420 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 421 sc->sc_i2c_xfer.error = 1; 422 goto done; 423 } 424 425 if (st & LPCIB_SMB_HS_INTR) { 426 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 427 goto done; 428 429 /* Read data */ 430 b = sc->sc_i2c_xfer.buf; 431 len = sc->sc_i2c_xfer.len; 432 if (len > 0) 433 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 434 LPCIB_SMB_HD0); 435 if (len > 1) 436 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 437 LPCIB_SMB_HD1); 438 } 439 440 done: 441 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 442 wakeup(sc); 443 return (1); 444 } 445
Indexes created Thu Oct 02 14:10:14 GMT 2025