ichsmb.c revision 1.37.4.6
1 /* $NetBSD: ichsmb.c,v 1.37.4.6 2017/02/05 13:40:29 skrll Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.18 2007/05/03 09:36:26 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.37.4.6 2017/02/05 13:40:29 skrll Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/ic/i82801lpcreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #ifdef ICHIIC_DEBUG 45 #define DPRINTF(x) printf x 46 #else 47 #define DPRINTF(x) 48 #endif 49 50 #define ICHIIC_DELAY 100 51 #define ICHIIC_TIMEOUT 1 52 53 struct ichsmb_softc { 54 device_t sc_dev; 55 56 bus_space_tag_t sc_iot; 57 bus_space_handle_t sc_ioh; 58 void * sc_ih; 59 int sc_poll; 60 61 struct i2c_controller sc_i2c_tag; 62 kmutex_t sc_i2c_mutex; 63 struct { 64 i2c_op_t op; 65 void * buf; 66 size_t len; 67 int flags; 68 volatile int error; 69 } sc_i2c_xfer; 70 device_t sc_i2c_device; 71 }; 72 73 static int ichsmb_match(device_t, cfdata_t, void *); 74 static void ichsmb_attach(device_t, device_t, void *); 75 static int ichsmb_rescan(device_t, const char *, const int *); 76 static void ichsmb_chdet(device_t, device_t); 77 78 static int ichsmb_i2c_acquire_bus(void *, int); 79 static void ichsmb_i2c_release_bus(void *, int); 80 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 81 size_t, void *, size_t, int); 82 83 static int ichsmb_intr(void *); 84 85 86 CFATTACH_DECL3_NEW(ichsmb, sizeof(struct ichsmb_softc), 87 ichsmb_match, ichsmb_attach, NULL, NULL, ichsmb_rescan, ichsmb_chdet, 0); 88 89 90 static int 91 ichsmb_match(device_t parent, cfdata_t match, void *aux) 92 { 93 struct pci_attach_args *pa = aux; 94 95 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 96 switch (PCI_PRODUCT(pa->pa_id)) { 97 case PCI_PRODUCT_INTEL_6300ESB_SMB: 98 case PCI_PRODUCT_INTEL_63XXESB_SMB: 99 case PCI_PRODUCT_INTEL_82801AA_SMB: 100 case PCI_PRODUCT_INTEL_82801AB_SMB: 101 case PCI_PRODUCT_INTEL_82801BA_SMB: 102 case PCI_PRODUCT_INTEL_82801CA_SMB: 103 case PCI_PRODUCT_INTEL_82801DB_SMB: 104 case PCI_PRODUCT_INTEL_82801E_SMB: 105 case PCI_PRODUCT_INTEL_82801EB_SMB: 106 case PCI_PRODUCT_INTEL_82801FB_SMB: 107 case PCI_PRODUCT_INTEL_82801G_SMB: 108 case PCI_PRODUCT_INTEL_82801H_SMB: 109 case PCI_PRODUCT_INTEL_82801I_SMB: 110 case PCI_PRODUCT_INTEL_82801JD_SMB: 111 case PCI_PRODUCT_INTEL_82801JI_SMB: 112 case PCI_PRODUCT_INTEL_3400_SMB: 113 case PCI_PRODUCT_INTEL_6SERIES_SMB: 114 case PCI_PRODUCT_INTEL_7SERIES_SMB: 115 case PCI_PRODUCT_INTEL_8SERIES_SMB: 116 case PCI_PRODUCT_INTEL_9SERIES_SMB: 117 case PCI_PRODUCT_INTEL_100SERIES_SMB: 118 case PCI_PRODUCT_INTEL_2HS_SMB: 119 case PCI_PRODUCT_INTEL_CORE4G_M_SMB: 120 case PCI_PRODUCT_INTEL_CORE5G_M_SMB: 121 case PCI_PRODUCT_INTEL_BAYTRAIL_PCU_SMB: 122 case PCI_PRODUCT_INTEL_BSW_PCU_SMB: 123 case PCI_PRODUCT_INTEL_C600_SMBUS: 124 case PCI_PRODUCT_INTEL_C600_SMB_0: 125 case PCI_PRODUCT_INTEL_C600_SMB_1: 126 case PCI_PRODUCT_INTEL_C600_SMB_2: 127 case PCI_PRODUCT_INTEL_C610_SMB: 128 case PCI_PRODUCT_INTEL_EP80579_SMB: 129 case PCI_PRODUCT_INTEL_DH89XXCC_SMB: 130 case PCI_PRODUCT_INTEL_DH89XXCL_SMB: 131 case PCI_PRODUCT_INTEL_C2000_PCU_SMBUS: 132 return 1; 133 } 134 } 135 return 0; 136 } 137 138 static void 139 ichsmb_attach(device_t parent, device_t self, void *aux) 140 { 141 struct ichsmb_softc *sc = device_private(self); 142 struct pci_attach_args *pa = aux; 143 pcireg_t conf; 144 bus_size_t iosize; 145 pci_intr_handle_t ih; 146 const char *intrstr = NULL; 147 char intrbuf[PCI_INTRSTR_LEN]; 148 int flags; 149 150 sc->sc_dev = self; 151 152 pci_aprint_devinfo(pa, NULL); 153 154 /* Read configuration */ 155 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 156 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 157 158 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 159 aprint_error_dev(self, "SMBus disabled\n"); 160 goto out; 161 } 162 163 /* Map I/O space */ 164 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 165 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize)) { 166 aprint_error_dev(self, "can't map I/O space\n"); 167 goto out; 168 } 169 170 sc->sc_poll = 1; 171 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 172 /* No PCI IRQ */ 173 aprint_normal_dev(self, "interrupting at SMI\n"); 174 } else { 175 /* Install interrupt handler */ 176 if (pci_intr_map(pa, &ih) == 0) { 177 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, 178 sizeof(intrbuf)); 179 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, ih, 180 IPL_BIO, ichsmb_intr, sc, device_xname(sc->sc_dev)); 181 if (sc->sc_ih != NULL) { 182 aprint_normal_dev(self, "interrupting at %s\n", 183 intrstr); 184 sc->sc_poll = 0; 185 } 186 } 187 if (sc->sc_poll) 188 aprint_normal_dev(self, "polling\n"); 189 } 190 191 sc->sc_i2c_device = NULL; 192 flags = 0; 193 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 194 ichsmb_rescan(self, "i2cbus", &flags); 195 196 out: if (!pmf_device_register(self, NULL, NULL)) 197 aprint_error_dev(self, "couldn't establish power handler\n"); 198 } 199 200 static int 201 ichsmb_rescan(device_t self, const char *ifattr, const int *flags) 202 { 203 struct ichsmb_softc *sc = device_private(self); 204 struct i2cbus_attach_args iba; 205 206 if (!ifattr_match(ifattr, "i2cbus")) 207 return 0; 208 209 if (sc->sc_i2c_device) 210 return 0; 211 212 /* Attach I2C bus */ 213 sc->sc_i2c_tag.ic_cookie = sc; 214 sc->sc_i2c_tag.ic_acquire_bus = ichsmb_i2c_acquire_bus; 215 sc->sc_i2c_tag.ic_release_bus = ichsmb_i2c_release_bus; 216 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 217 218 memset(&iba, 0, sizeof(iba)); 219 iba.iba_type = I2C_TYPE_SMBUS; 220 iba.iba_tag = &sc->sc_i2c_tag; 221 sc->sc_i2c_device = config_found_ia(self, ifattr, &iba, iicbus_print); 222 223 return 0; 224 } 225 226 static void 227 ichsmb_chdet(device_t self, device_t child) 228 { 229 struct ichsmb_softc *sc = device_private(self); 230 231 if (sc->sc_i2c_device == child) 232 sc->sc_i2c_device = NULL; 233 234 } 235 236 static int 237 ichsmb_i2c_acquire_bus(void *cookie, int flags) 238 { 239 struct ichsmb_softc *sc = cookie; 240 241 if (cold) 242 return 0; 243 244 mutex_enter(&sc->sc_i2c_mutex); 245 return 0; 246 } 247 248 static void 249 ichsmb_i2c_release_bus(void *cookie, int flags) 250 { 251 struct ichsmb_softc *sc = cookie; 252 253 if (cold) 254 return; 255 256 mutex_exit(&sc->sc_i2c_mutex); 257 } 258 259 static int 260 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 261 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 262 { 263 struct ichsmb_softc *sc = cookie; 264 const uint8_t *b; 265 uint8_t ctl = 0, st; 266 int retries; 267 char fbuf[64]; 268 269 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 270 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 271 len, flags)); 272 273 /* Clear status bits */ 274 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 275 LPCIB_SMB_HS_INTR | LPCIB_SMB_HS_DEVERR | 276 LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED); 277 bus_space_barrier(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 1, 278 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 279 280 /* Wait for bus to be idle */ 281 for (retries = 100; retries > 0; retries--) { 282 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 283 if (!(st & LPCIB_SMB_HS_BUSY)) 284 break; 285 DELAY(ICHIIC_DELAY); 286 } 287 #ifdef ICHIIC_DEBUG 288 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 289 printf("%s: exec: st 0x%s\n", device_xname(sc->sc_dev), fbuf); 290 #endif 291 if (st & LPCIB_SMB_HS_BUSY) 292 return (1); 293 294 if (cold || sc->sc_poll) 295 flags |= I2C_F_POLL; 296 297 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 298 (cmdlen == 0 && len > 1)) 299 return (1); 300 301 /* Setup transfer */ 302 sc->sc_i2c_xfer.op = op; 303 sc->sc_i2c_xfer.buf = buf; 304 sc->sc_i2c_xfer.len = len; 305 sc->sc_i2c_xfer.flags = flags; 306 sc->sc_i2c_xfer.error = 0; 307 308 /* Set slave address and transfer direction */ 309 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 310 LPCIB_SMB_TXSLVA_ADDR(addr) | 311 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 312 313 b = (const uint8_t *)cmdbuf; 314 if (cmdlen > 0) 315 /* Set command byte */ 316 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 317 318 if (I2C_OP_WRITE_P(op)) { 319 /* Write data */ 320 b = buf; 321 if (cmdlen == 0 && len == 1) 322 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 323 LPCIB_SMB_HCMD, b[0]); 324 else if (len > 0) 325 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 326 LPCIB_SMB_HD0, b[0]); 327 if (len > 1) 328 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 329 LPCIB_SMB_HD1, b[1]); 330 } 331 332 /* Set SMBus command */ 333 if (cmdlen == 0) { 334 if (len == 0) 335 ctl = LPCIB_SMB_HC_CMD_QUICK; 336 else 337 ctl = LPCIB_SMB_HC_CMD_BYTE; 338 } else if (len == 1) 339 ctl = LPCIB_SMB_HC_CMD_BDATA; 340 else if (len == 2) 341 ctl = LPCIB_SMB_HC_CMD_WDATA; 342 343 if ((flags & I2C_F_POLL) == 0) 344 ctl |= LPCIB_SMB_HC_INTREN; 345 346 /* Start transaction */ 347 ctl |= LPCIB_SMB_HC_START; 348 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 349 350 if (flags & I2C_F_POLL) { 351 /* Poll for completion */ 352 DELAY(ICHIIC_DELAY); 353 for (retries = 1000; retries > 0; retries--) { 354 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 355 LPCIB_SMB_HS); 356 if ((st & LPCIB_SMB_HS_BUSY) == 0) 357 break; 358 DELAY(ICHIIC_DELAY); 359 } 360 if (st & LPCIB_SMB_HS_BUSY) 361 goto timeout; 362 ichsmb_intr(sc); 363 } else { 364 /* Wait for interrupt */ 365 if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz)) 366 goto timeout; 367 } 368 369 if (sc->sc_i2c_xfer.error) 370 return (1); 371 372 return (0); 373 374 timeout: 375 /* 376 * Transfer timeout. Kill the transaction and clear status bits. 377 */ 378 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 379 aprint_error_dev(sc->sc_dev, 380 "exec: op %d, addr 0x%02x, cmdlen %zd, len %zd, " 381 "flags 0x%02x: timeout, status 0x%s\n", 382 op, addr, cmdlen, len, flags, fbuf); 383 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 384 LPCIB_SMB_HC_KILL); 385 DELAY(ICHIIC_DELAY); 386 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 387 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 388 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 389 aprint_error_dev(sc->sc_dev, "abort failed, status 0x%s\n", 390 fbuf); 391 } 392 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 393 return (1); 394 } 395 396 static int 397 ichsmb_intr(void *arg) 398 { 399 struct ichsmb_softc *sc = arg; 400 uint8_t st; 401 uint8_t *b; 402 size_t len; 403 #ifdef ICHIIC_DEBUG 404 char fbuf[64]; 405 #endif 406 407 /* Read status */ 408 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 409 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 410 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 411 LPCIB_SMB_HS_SMBAL | LPCIB_SMB_HS_BDONE)) == 0) 412 /* Interrupt was not for us */ 413 return (0); 414 415 #ifdef ICHIIC_DEBUG 416 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 417 printf("%s: intr st 0x%s\n", device_xname(sc->sc_dev), fbuf); 418 #endif 419 420 /* Clear status bits */ 421 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 422 423 /* Check for errors */ 424 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 425 sc->sc_i2c_xfer.error = 1; 426 goto done; 427 } 428 429 if (st & LPCIB_SMB_HS_INTR) { 430 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 431 goto done; 432 433 /* Read data */ 434 b = sc->sc_i2c_xfer.buf; 435 len = sc->sc_i2c_xfer.len; 436 if (len > 0) 437 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 438 LPCIB_SMB_HD0); 439 if (len > 1) 440 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 441 LPCIB_SMB_HD1); 442 } 443 444 done: 445 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 446 wakeup(sc); 447 return (1); 448 } 449
Indexes created Thu Oct 02 14:10:14 GMT 2025