ichsmb.c revision 1.46.2.3
1 /* $NetBSD: ichsmb.c,v 1.46.2.3 2017/04/26 02:53:12 pgoyette Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.18 2007/05/03 09:36:26 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.46.2.3 2017/04/26 02:53:12 pgoyette Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/ic/i82801lpcreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #ifdef ICHIIC_DEBUG 45 #define DPRINTF(x) printf x 46 #else 47 #define DPRINTF(x) 48 #endif 49 50 #define ICHIIC_DELAY 100 51 #define ICHIIC_TIMEOUT 1 52 53 struct ichsmb_softc { 54 device_t sc_dev; 55 56 bus_space_tag_t sc_iot; 57 bus_space_handle_t sc_ioh; 58 void * sc_ih; 59 int sc_poll; 60 61 struct i2c_controller sc_i2c_tag; 62 kmutex_t sc_i2c_mutex; 63 struct { 64 i2c_op_t op; 65 void * buf; 66 size_t len; 67 int flags; 68 volatile int error; 69 } sc_i2c_xfer; 70 device_t sc_i2c_device; 71 }; 72 73 static int ichsmb_match(device_t, cfdata_t, void *); 74 static void ichsmb_attach(device_t, device_t, void *); 75 static int ichsmb_rescan(device_t, const char *, const int *); 76 static void ichsmb_chdet(device_t, device_t); 77 78 static int ichsmb_i2c_acquire_bus(void *, int); 79 static void ichsmb_i2c_release_bus(void *, int); 80 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 81 size_t, void *, size_t, int); 82 83 static int ichsmb_intr(void *); 84 85 86 CFATTACH_DECL3_NEW(ichsmb, sizeof(struct ichsmb_softc), 87 ichsmb_match, ichsmb_attach, NULL, NULL, ichsmb_rescan, ichsmb_chdet, 0); 88 89 90 static int 91 ichsmb_match(device_t parent, cfdata_t match, void *aux) 92 { 93 struct pci_attach_args *pa = aux; 94 95 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 96 switch (PCI_PRODUCT(pa->pa_id)) { 97 case PCI_PRODUCT_INTEL_6300ESB_SMB: 98 case PCI_PRODUCT_INTEL_63XXESB_SMB: 99 case PCI_PRODUCT_INTEL_82801AA_SMB: 100 case PCI_PRODUCT_INTEL_82801AB_SMB: 101 case PCI_PRODUCT_INTEL_82801BA_SMB: 102 case PCI_PRODUCT_INTEL_82801CA_SMB: 103 case PCI_PRODUCT_INTEL_82801DB_SMB: 104 case PCI_PRODUCT_INTEL_82801E_SMB: 105 case PCI_PRODUCT_INTEL_82801EB_SMB: 106 case PCI_PRODUCT_INTEL_82801FB_SMB: 107 case PCI_PRODUCT_INTEL_82801G_SMB: 108 case PCI_PRODUCT_INTEL_82801H_SMB: 109 case PCI_PRODUCT_INTEL_82801I_SMB: 110 case PCI_PRODUCT_INTEL_82801JD_SMB: 111 case PCI_PRODUCT_INTEL_82801JI_SMB: 112 case PCI_PRODUCT_INTEL_3400_SMB: 113 case PCI_PRODUCT_INTEL_6SERIES_SMB: 114 case PCI_PRODUCT_INTEL_7SERIES_SMB: 115 case PCI_PRODUCT_INTEL_8SERIES_SMB: 116 case PCI_PRODUCT_INTEL_9SERIES_SMB: 117 case PCI_PRODUCT_INTEL_100SERIES_SMB: 118 case PCI_PRODUCT_INTEL_100SERIES_LP_SMB: 119 case PCI_PRODUCT_INTEL_2HS_SMB: 120 case PCI_PRODUCT_INTEL_CORE4G_M_SMB: 121 case PCI_PRODUCT_INTEL_CORE5G_M_SMB: 122 case PCI_PRODUCT_INTEL_BAYTRAIL_PCU_SMB: 123 case PCI_PRODUCT_INTEL_BSW_PCU_SMB: 124 case PCI_PRODUCT_INTEL_C600_SMBUS: 125 case PCI_PRODUCT_INTEL_C600_SMB_0: 126 case PCI_PRODUCT_INTEL_C600_SMB_1: 127 case PCI_PRODUCT_INTEL_C600_SMB_2: 128 case PCI_PRODUCT_INTEL_C610_SMB: 129 case PCI_PRODUCT_INTEL_EP80579_SMB: 130 case PCI_PRODUCT_INTEL_DH89XXCC_SMB: 131 case PCI_PRODUCT_INTEL_DH89XXCL_SMB: 132 case PCI_PRODUCT_INTEL_C2000_PCU_SMBUS: 133 return 1; 134 } 135 } 136 return 0; 137 } 138 139 static void 140 ichsmb_attach(device_t parent, device_t self, void *aux) 141 { 142 struct ichsmb_softc *sc = device_private(self); 143 struct pci_attach_args *pa = aux; 144 pcireg_t conf; 145 bus_size_t iosize; 146 pci_intr_handle_t ih; 147 const char *intrstr = NULL; 148 char intrbuf[PCI_INTRSTR_LEN]; 149 int flags; 150 151 sc->sc_dev = self; 152 153 pci_aprint_devinfo(pa, NULL); 154 155 /* Read configuration */ 156 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 157 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 158 159 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 160 aprint_error_dev(self, "SMBus disabled\n"); 161 goto out; 162 } 163 164 /* Map I/O space */ 165 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 166 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize)) { 167 aprint_error_dev(self, "can't map I/O space\n"); 168 goto out; 169 } 170 171 sc->sc_poll = 1; 172 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 173 /* No PCI IRQ */ 174 aprint_normal_dev(self, "interrupting at SMI\n"); 175 } else { 176 /* Install interrupt handler */ 177 if (pci_intr_map(pa, &ih) == 0) { 178 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, 179 sizeof(intrbuf)); 180 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, ih, 181 IPL_BIO, ichsmb_intr, sc, device_xname(sc->sc_dev)); 182 if (sc->sc_ih != NULL) { 183 aprint_normal_dev(self, "interrupting at %s\n", 184 intrstr); 185 sc->sc_poll = 0; 186 } 187 } 188 if (sc->sc_poll) 189 aprint_normal_dev(self, "polling\n"); 190 } 191 192 sc->sc_i2c_device = NULL; 193 flags = 0; 194 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 195 ichsmb_rescan(self, "i2cbus", &flags); 196 197 out: if (!pmf_device_register(self, NULL, NULL)) 198 aprint_error_dev(self, "couldn't establish power handler\n"); 199 } 200 201 static int 202 ichsmb_rescan(device_t self, const char *ifattr, const int *flags) 203 { 204 struct ichsmb_softc *sc = device_private(self); 205 struct i2cbus_attach_args iba; 206 207 if (!ifattr_match(ifattr, "i2cbus")) 208 return 0; 209 210 if (sc->sc_i2c_device) 211 return 0; 212 213 /* Attach I2C bus */ 214 sc->sc_i2c_tag.ic_cookie = sc; 215 sc->sc_i2c_tag.ic_acquire_bus = ichsmb_i2c_acquire_bus; 216 sc->sc_i2c_tag.ic_release_bus = ichsmb_i2c_release_bus; 217 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 218 219 memset(&iba, 0, sizeof(iba)); 220 iba.iba_type = I2C_TYPE_SMBUS; 221 iba.iba_tag = &sc->sc_i2c_tag; 222 sc->sc_i2c_device = config_found_ia(self, ifattr, &iba, iicbus_print); 223 224 return 0; 225 } 226 227 static void 228 ichsmb_chdet(device_t self, device_t child) 229 { 230 struct ichsmb_softc *sc = device_private(self); 231 232 if (sc->sc_i2c_device == child) 233 sc->sc_i2c_device = NULL; 234 235 } 236 237 static int 238 ichsmb_i2c_acquire_bus(void *cookie, int flags) 239 { 240 struct ichsmb_softc *sc = cookie; 241 242 if (cold) 243 return 0; 244 245 mutex_enter(&sc->sc_i2c_mutex); 246 return 0; 247 } 248 249 static void 250 ichsmb_i2c_release_bus(void *cookie, int flags) 251 { 252 struct ichsmb_softc *sc = cookie; 253 254 if (cold) 255 return; 256 257 mutex_exit(&sc->sc_i2c_mutex); 258 } 259 260 static int 261 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 262 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 263 { 264 struct ichsmb_softc *sc = cookie; 265 const uint8_t *b; 266 uint8_t ctl = 0, st; 267 int retries; 268 char fbuf[64]; 269 270 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 271 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 272 len, flags)); 273 274 /* Clear status bits */ 275 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 276 LPCIB_SMB_HS_INTR | LPCIB_SMB_HS_DEVERR | 277 LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED); 278 bus_space_barrier(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 1, 279 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 280 281 /* Wait for bus to be idle */ 282 for (retries = 100; retries > 0; retries--) { 283 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 284 if (!(st & LPCIB_SMB_HS_BUSY)) 285 break; 286 DELAY(ICHIIC_DELAY); 287 } 288 #ifdef ICHIIC_DEBUG 289 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 290 printf("%s: exec: st %s\n", device_xname(sc->sc_dev), fbuf); 291 #endif 292 if (st & LPCIB_SMB_HS_BUSY) 293 return (1); 294 295 if (cold || sc->sc_poll) 296 flags |= I2C_F_POLL; 297 298 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 299 (cmdlen == 0 && len > 1)) 300 return (1); 301 302 /* Setup transfer */ 303 sc->sc_i2c_xfer.op = op; 304 sc->sc_i2c_xfer.buf = buf; 305 sc->sc_i2c_xfer.len = len; 306 sc->sc_i2c_xfer.flags = flags; 307 sc->sc_i2c_xfer.error = 0; 308 309 /* Set slave address and transfer direction */ 310 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 311 LPCIB_SMB_TXSLVA_ADDR(addr) | 312 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 313 314 b = (const uint8_t *)cmdbuf; 315 if (cmdlen > 0) 316 /* Set command byte */ 317 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 318 319 if (I2C_OP_WRITE_P(op)) { 320 /* Write data */ 321 b = buf; 322 if (cmdlen == 0 && len == 1) 323 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 324 LPCIB_SMB_HCMD, b[0]); 325 else if (len > 0) 326 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 327 LPCIB_SMB_HD0, b[0]); 328 if (len > 1) 329 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 330 LPCIB_SMB_HD1, b[1]); 331 } 332 333 /* Set SMBus command */ 334 if (cmdlen == 0) { 335 if (len == 0) 336 ctl = LPCIB_SMB_HC_CMD_QUICK; 337 else 338 ctl = LPCIB_SMB_HC_CMD_BYTE; 339 } else if (len == 1) 340 ctl = LPCIB_SMB_HC_CMD_BDATA; 341 else if (len == 2) 342 ctl = LPCIB_SMB_HC_CMD_WDATA; 343 344 if ((flags & I2C_F_POLL) == 0) 345 ctl |= LPCIB_SMB_HC_INTREN; 346 347 /* Start transaction */ 348 ctl |= LPCIB_SMB_HC_START; 349 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 350 351 if (flags & I2C_F_POLL) { 352 /* Poll for completion */ 353 DELAY(ICHIIC_DELAY); 354 for (retries = 1000; retries > 0; retries--) { 355 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 356 LPCIB_SMB_HS); 357 if ((st & LPCIB_SMB_HS_BUSY) == 0) 358 break; 359 DELAY(ICHIIC_DELAY); 360 } 361 if (st & LPCIB_SMB_HS_BUSY) 362 goto timeout; 363 ichsmb_intr(sc); 364 } else { 365 /* Wait for interrupt */ 366 if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz)) 367 goto timeout; 368 } 369 370 if (sc->sc_i2c_xfer.error) 371 return (1); 372 373 return (0); 374 375 timeout: 376 /* 377 * Transfer timeout. Kill the transaction and clear status bits. 378 */ 379 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 380 aprint_error_dev(sc->sc_dev, 381 "exec: op %d, addr 0x%02x, cmdlen %zd, len %zd, " 382 "flags 0x%02x: timeout, status %s\n", 383 op, addr, cmdlen, len, flags, fbuf); 384 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 385 LPCIB_SMB_HC_KILL); 386 DELAY(ICHIIC_DELAY); 387 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 388 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 389 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 390 aprint_error_dev(sc->sc_dev, "abort failed, status %s\n", 391 fbuf); 392 } 393 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 394 return (1); 395 } 396 397 static int 398 ichsmb_intr(void *arg) 399 { 400 struct ichsmb_softc *sc = arg; 401 uint8_t st; 402 uint8_t *b; 403 size_t len; 404 #ifdef ICHIIC_DEBUG 405 char fbuf[64]; 406 #endif 407 408 /* Read status */ 409 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 410 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 411 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 412 LPCIB_SMB_HS_SMBAL | LPCIB_SMB_HS_BDONE)) == 0) 413 /* Interrupt was not for us */ 414 return (0); 415 416 #ifdef ICHIIC_DEBUG 417 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 418 printf("%s: intr st %s\n", device_xname(sc->sc_dev), fbuf); 419 #endif 420 421 /* Clear status bits */ 422 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 423 424 /* Check for errors */ 425 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 426 sc->sc_i2c_xfer.error = 1; 427 goto done; 428 } 429 430 if (st & LPCIB_SMB_HS_INTR) { 431 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 432 goto done; 433 434 /* Read data */ 435 b = sc->sc_i2c_xfer.buf; 436 len = sc->sc_i2c_xfer.len; 437 if (len > 0) 438 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 439 LPCIB_SMB_HD0); 440 if (len > 1) 441 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 442 LPCIB_SMB_HD1); 443 } 444 445 done: 446 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 447 wakeup(sc); 448 return (1); 449 } 450
Indexes created Thu Oct 02 14:10:14 GMT 2025