ichsmb.c revision 1.50.6.1
1 /* $NetBSD: ichsmb.c,v 1.50.6.1 2018/02/26 00:05:04 snj Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.18 2007/05/03 09:36:26 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.50.6.1 2018/02/26 00:05:04 snj Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/ic/i82801lpcreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #ifdef ICHIIC_DEBUG 45 #define DPRINTF(x) printf x 46 #else 47 #define DPRINTF(x) 48 #endif 49 50 #define ICHIIC_DELAY 100 51 #define ICHIIC_TIMEOUT 1 52 53 struct ichsmb_softc { 54 device_t sc_dev; 55 56 bus_space_tag_t sc_iot; 57 bus_space_handle_t sc_ioh; 58 void * sc_ih; 59 int sc_poll; 60 61 struct i2c_controller sc_i2c_tag; 62 kmutex_t sc_i2c_mutex; 63 struct { 64 i2c_op_t op; 65 void * buf; 66 size_t len; 67 int flags; 68 volatile int error; 69 } sc_i2c_xfer; 70 device_t sc_i2c_device; 71 }; 72 73 static int ichsmb_match(device_t, cfdata_t, void *); 74 static void ichsmb_attach(device_t, device_t, void *); 75 static int ichsmb_rescan(device_t, const char *, const int *); 76 static void ichsmb_chdet(device_t, device_t); 77 78 static int ichsmb_i2c_acquire_bus(void *, int); 79 static void ichsmb_i2c_release_bus(void *, int); 80 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 81 size_t, void *, size_t, int); 82 83 static int ichsmb_intr(void *); 84 85 86 CFATTACH_DECL3_NEW(ichsmb, sizeof(struct ichsmb_softc), 87 ichsmb_match, ichsmb_attach, NULL, NULL, ichsmb_rescan, ichsmb_chdet, 0); 88 89 90 static int 91 ichsmb_match(device_t parent, cfdata_t match, void *aux) 92 { 93 struct pci_attach_args *pa = aux; 94 95 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 96 switch (PCI_PRODUCT(pa->pa_id)) { 97 case PCI_PRODUCT_INTEL_6300ESB_SMB: 98 case PCI_PRODUCT_INTEL_63XXESB_SMB: 99 case PCI_PRODUCT_INTEL_82801AA_SMB: 100 case PCI_PRODUCT_INTEL_82801AB_SMB: 101 case PCI_PRODUCT_INTEL_82801BA_SMB: 102 case PCI_PRODUCT_INTEL_82801CA_SMB: 103 case PCI_PRODUCT_INTEL_82801DB_SMB: 104 case PCI_PRODUCT_INTEL_82801E_SMB: 105 case PCI_PRODUCT_INTEL_82801EB_SMB: 106 case PCI_PRODUCT_INTEL_82801FB_SMB: 107 case PCI_PRODUCT_INTEL_82801G_SMB: 108 case PCI_PRODUCT_INTEL_82801H_SMB: 109 case PCI_PRODUCT_INTEL_82801I_SMB: 110 case PCI_PRODUCT_INTEL_82801JD_SMB: 111 case PCI_PRODUCT_INTEL_82801JI_SMB: 112 case PCI_PRODUCT_INTEL_3400_SMB: 113 case PCI_PRODUCT_INTEL_6SERIES_SMB: 114 case PCI_PRODUCT_INTEL_7SERIES_SMB: 115 case PCI_PRODUCT_INTEL_8SERIES_SMB: 116 case PCI_PRODUCT_INTEL_9SERIES_SMB: 117 case PCI_PRODUCT_INTEL_100SERIES_SMB: 118 case PCI_PRODUCT_INTEL_100SERIES_LP_SMB: 119 case PCI_PRODUCT_INTEL_2HS_SMB: 120 case PCI_PRODUCT_INTEL_CORE4G_M_SMB: 121 case PCI_PRODUCT_INTEL_CORE5G_M_SMB: 122 case PCI_PRODUCT_INTEL_BAYTRAIL_PCU_SMB: 123 case PCI_PRODUCT_INTEL_BSW_PCU_SMB: 124 case PCI_PRODUCT_INTEL_C600_SMBUS: 125 case PCI_PRODUCT_INTEL_C600_SMB_0: 126 case PCI_PRODUCT_INTEL_C600_SMB_1: 127 case PCI_PRODUCT_INTEL_C600_SMB_2: 128 case PCI_PRODUCT_INTEL_C610_SMB: 129 case PCI_PRODUCT_INTEL_EP80579_SMB: 130 case PCI_PRODUCT_INTEL_DH89XXCC_SMB: 131 case PCI_PRODUCT_INTEL_DH89XXCL_SMB: 132 case PCI_PRODUCT_INTEL_C2000_PCU_SMBUS: 133 case PCI_PRODUCT_INTEL_C3K_SMBUS_LEGACY: 134 return 1; 135 } 136 } 137 return 0; 138 } 139 140 static void 141 ichsmb_attach(device_t parent, device_t self, void *aux) 142 { 143 struct ichsmb_softc *sc = device_private(self); 144 struct pci_attach_args *pa = aux; 145 pcireg_t conf; 146 bus_size_t iosize; 147 pci_intr_handle_t ih; 148 const char *intrstr = NULL; 149 char intrbuf[PCI_INTRSTR_LEN]; 150 int flags; 151 152 sc->sc_dev = self; 153 154 pci_aprint_devinfo(pa, NULL); 155 156 /* Read configuration */ 157 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 158 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 159 160 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 161 aprint_error_dev(self, "SMBus disabled\n"); 162 goto out; 163 } 164 165 /* Map I/O space */ 166 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 167 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize)) { 168 aprint_error_dev(self, "can't map I/O space\n"); 169 goto out; 170 } 171 172 sc->sc_poll = 1; 173 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 174 /* No PCI IRQ */ 175 aprint_normal_dev(self, "interrupting at SMI\n"); 176 } else { 177 /* Install interrupt handler */ 178 if (pci_intr_map(pa, &ih) == 0) { 179 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, 180 sizeof(intrbuf)); 181 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, ih, 182 IPL_BIO, ichsmb_intr, sc, device_xname(sc->sc_dev)); 183 if (sc->sc_ih != NULL) { 184 aprint_normal_dev(self, "interrupting at %s\n", 185 intrstr); 186 sc->sc_poll = 0; 187 } 188 } 189 if (sc->sc_poll) 190 aprint_normal_dev(self, "polling\n"); 191 } 192 193 sc->sc_i2c_device = NULL; 194 flags = 0; 195 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 196 ichsmb_rescan(self, "i2cbus", &flags); 197 198 out: if (!pmf_device_register(self, NULL, NULL)) 199 aprint_error_dev(self, "couldn't establish power handler\n"); 200 } 201 202 static int 203 ichsmb_rescan(device_t self, const char *ifattr, const int *flags) 204 { 205 struct ichsmb_softc *sc = device_private(self); 206 struct i2cbus_attach_args iba; 207 208 if (!ifattr_match(ifattr, "i2cbus")) 209 return 0; 210 211 if (sc->sc_i2c_device) 212 return 0; 213 214 /* Attach I2C bus */ 215 sc->sc_i2c_tag.ic_cookie = sc; 216 sc->sc_i2c_tag.ic_acquire_bus = ichsmb_i2c_acquire_bus; 217 sc->sc_i2c_tag.ic_release_bus = ichsmb_i2c_release_bus; 218 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 219 220 memset(&iba, 0, sizeof(iba)); 221 iba.iba_type = I2C_TYPE_SMBUS; 222 iba.iba_tag = &sc->sc_i2c_tag; 223 sc->sc_i2c_device = config_found_ia(self, ifattr, &iba, iicbus_print); 224 225 return 0; 226 } 227 228 static void 229 ichsmb_chdet(device_t self, device_t child) 230 { 231 struct ichsmb_softc *sc = device_private(self); 232 233 if (sc->sc_i2c_device == child) 234 sc->sc_i2c_device = NULL; 235 236 } 237 238 static int 239 ichsmb_i2c_acquire_bus(void *cookie, int flags) 240 { 241 struct ichsmb_softc *sc = cookie; 242 243 if (cold) 244 return 0; 245 246 mutex_enter(&sc->sc_i2c_mutex); 247 return 0; 248 } 249 250 static void 251 ichsmb_i2c_release_bus(void *cookie, int flags) 252 { 253 struct ichsmb_softc *sc = cookie; 254 255 if (cold) 256 return; 257 258 mutex_exit(&sc->sc_i2c_mutex); 259 } 260 261 static int 262 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 263 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 264 { 265 struct ichsmb_softc *sc = cookie; 266 const uint8_t *b; 267 uint8_t ctl = 0, st; 268 int retries; 269 char fbuf[64]; 270 271 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 272 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 273 len, flags)); 274 275 /* Clear status bits */ 276 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 277 LPCIB_SMB_HS_INTR | LPCIB_SMB_HS_DEVERR | 278 LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED); 279 bus_space_barrier(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 1, 280 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 281 282 /* Wait for bus to be idle */ 283 for (retries = 100; retries > 0; retries--) { 284 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 285 if (!(st & LPCIB_SMB_HS_BUSY)) 286 break; 287 DELAY(ICHIIC_DELAY); 288 } 289 #ifdef ICHIIC_DEBUG 290 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 291 printf("%s: exec: st %s\n", device_xname(sc->sc_dev), fbuf); 292 #endif 293 if (st & LPCIB_SMB_HS_BUSY) 294 return (1); 295 296 if (cold || sc->sc_poll) 297 flags |= I2C_F_POLL; 298 299 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 300 (cmdlen == 0 && len > 1)) 301 return (1); 302 303 /* Setup transfer */ 304 sc->sc_i2c_xfer.op = op; 305 sc->sc_i2c_xfer.buf = buf; 306 sc->sc_i2c_xfer.len = len; 307 sc->sc_i2c_xfer.flags = flags; 308 sc->sc_i2c_xfer.error = 0; 309 310 /* Set slave address and transfer direction */ 311 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 312 LPCIB_SMB_TXSLVA_ADDR(addr) | 313 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 314 315 b = (const uint8_t *)cmdbuf; 316 if (cmdlen > 0) 317 /* Set command byte */ 318 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 319 320 if (I2C_OP_WRITE_P(op)) { 321 /* Write data */ 322 b = buf; 323 if (cmdlen == 0 && len == 1) 324 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 325 LPCIB_SMB_HCMD, b[0]); 326 else if (len > 0) 327 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 328 LPCIB_SMB_HD0, b[0]); 329 if (len > 1) 330 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 331 LPCIB_SMB_HD1, b[1]); 332 } 333 334 /* Set SMBus command */ 335 if (cmdlen == 0) { 336 if (len == 0) 337 ctl = LPCIB_SMB_HC_CMD_QUICK; 338 else 339 ctl = LPCIB_SMB_HC_CMD_BYTE; 340 } else if (len == 1) 341 ctl = LPCIB_SMB_HC_CMD_BDATA; 342 else if (len == 2) 343 ctl = LPCIB_SMB_HC_CMD_WDATA; 344 345 if ((flags & I2C_F_POLL) == 0) 346 ctl |= LPCIB_SMB_HC_INTREN; 347 348 /* Start transaction */ 349 ctl |= LPCIB_SMB_HC_START; 350 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 351 352 if (flags & I2C_F_POLL) { 353 /* Poll for completion */ 354 DELAY(ICHIIC_DELAY); 355 for (retries = 1000; retries > 0; retries--) { 356 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 357 LPCIB_SMB_HS); 358 if ((st & LPCIB_SMB_HS_BUSY) == 0) 359 break; 360 DELAY(ICHIIC_DELAY); 361 } 362 if (st & LPCIB_SMB_HS_BUSY) 363 goto timeout; 364 ichsmb_intr(sc); 365 } else { 366 /* Wait for interrupt */ 367 if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz)) 368 goto timeout; 369 } 370 371 if (sc->sc_i2c_xfer.error) 372 return (1); 373 374 return (0); 375 376 timeout: 377 /* 378 * Transfer timeout. Kill the transaction and clear status bits. 379 */ 380 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 381 aprint_error_dev(sc->sc_dev, 382 "exec: op %d, addr 0x%02x, cmdlen %zd, len %zd, " 383 "flags 0x%02x: timeout, status %s\n", 384 op, addr, cmdlen, len, flags, fbuf); 385 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 386 LPCIB_SMB_HC_KILL); 387 DELAY(ICHIIC_DELAY); 388 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 389 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 390 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 391 aprint_error_dev(sc->sc_dev, "abort failed, status %s\n", 392 fbuf); 393 } 394 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 395 return (1); 396 } 397 398 static int 399 ichsmb_intr(void *arg) 400 { 401 struct ichsmb_softc *sc = arg; 402 uint8_t st; 403 uint8_t *b; 404 size_t len; 405 #ifdef ICHIIC_DEBUG 406 char fbuf[64]; 407 #endif 408 409 /* Read status */ 410 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 411 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 412 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 413 LPCIB_SMB_HS_SMBAL | LPCIB_SMB_HS_BDONE)) == 0) 414 /* Interrupt was not for us */ 415 return (0); 416 417 #ifdef ICHIIC_DEBUG 418 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 419 printf("%s: intr st %s\n", device_xname(sc->sc_dev), fbuf); 420 #endif 421 422 /* Clear status bits */ 423 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 424 425 /* Check for errors */ 426 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 427 sc->sc_i2c_xfer.error = 1; 428 goto done; 429 } 430 431 if (st & LPCIB_SMB_HS_INTR) { 432 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 433 goto done; 434 435 /* Read data */ 436 b = sc->sc_i2c_xfer.buf; 437 len = sc->sc_i2c_xfer.len; 438 if (len > 0) 439 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 440 LPCIB_SMB_HD0); 441 if (len > 1) 442 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 443 LPCIB_SMB_HD1); 444 } 445 446 done: 447 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 448 wakeup(sc); 449 return (1); 450 } 451
Indexes created Thu Oct 02 14:10:14 GMT 2025