ichsmb.c revision 1.50.6.4
1 /* $NetBSD: ichsmb.c,v 1.50.6.4 2020/08/05 15:54:30 martin Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.18 2007/05/03 09:36:26 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.50.6.4 2020/08/05 15:54:30 martin Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/ic/i82801lpcreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #ifdef ICHIIC_DEBUG 45 #define DPRINTF(x) printf x 46 #else 47 #define DPRINTF(x) 48 #endif 49 50 #define ICHIIC_DELAY 100 51 #define ICHIIC_TIMEOUT 1 52 53 struct ichsmb_softc { 54 device_t sc_dev; 55 56 bus_space_tag_t sc_iot; 57 bus_space_handle_t sc_ioh; 58 void * sc_ih; 59 int sc_poll; 60 61 struct i2c_controller sc_i2c_tag; 62 kmutex_t sc_i2c_mutex; 63 struct { 64 i2c_op_t op; 65 void * buf; 66 size_t len; 67 int flags; 68 volatile int error; 69 } sc_i2c_xfer; 70 device_t sc_i2c_device; 71 }; 72 73 static int ichsmb_match(device_t, cfdata_t, void *); 74 static void ichsmb_attach(device_t, device_t, void *); 75 static int ichsmb_rescan(device_t, const char *, const int *); 76 static void ichsmb_chdet(device_t, device_t); 77 78 static int ichsmb_i2c_acquire_bus(void *, int); 79 static void ichsmb_i2c_release_bus(void *, int); 80 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 81 size_t, void *, size_t, int); 82 83 static int ichsmb_intr(void *); 84 85 86 CFATTACH_DECL3_NEW(ichsmb, sizeof(struct ichsmb_softc), 87 ichsmb_match, ichsmb_attach, NULL, NULL, ichsmb_rescan, ichsmb_chdet, 0); 88 89 90 static int 91 ichsmb_match(device_t parent, cfdata_t match, void *aux) 92 { 93 struct pci_attach_args *pa = aux; 94 95 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 96 switch (PCI_PRODUCT(pa->pa_id)) { 97 case PCI_PRODUCT_INTEL_6300ESB_SMB: 98 case PCI_PRODUCT_INTEL_63XXESB_SMB: 99 case PCI_PRODUCT_INTEL_82801AA_SMB: 100 case PCI_PRODUCT_INTEL_82801AB_SMB: 101 case PCI_PRODUCT_INTEL_82801BA_SMB: 102 case PCI_PRODUCT_INTEL_82801CA_SMB: 103 case PCI_PRODUCT_INTEL_82801DB_SMB: 104 case PCI_PRODUCT_INTEL_82801E_SMB: 105 case PCI_PRODUCT_INTEL_82801EB_SMB: 106 case PCI_PRODUCT_INTEL_82801FB_SMB: 107 case PCI_PRODUCT_INTEL_82801G_SMB: 108 case PCI_PRODUCT_INTEL_82801H_SMB: 109 case PCI_PRODUCT_INTEL_82801I_SMB: 110 case PCI_PRODUCT_INTEL_82801JD_SMB: 111 case PCI_PRODUCT_INTEL_82801JI_SMB: 112 case PCI_PRODUCT_INTEL_3400_SMB: 113 case PCI_PRODUCT_INTEL_6SERIES_SMB: 114 case PCI_PRODUCT_INTEL_7SERIES_SMB: 115 case PCI_PRODUCT_INTEL_8SERIES_SMB: 116 case PCI_PRODUCT_INTEL_9SERIES_SMB: 117 case PCI_PRODUCT_INTEL_100SERIES_SMB: 118 case PCI_PRODUCT_INTEL_100SERIES_LP_SMB: 119 case PCI_PRODUCT_INTEL_2HS_SMB: 120 case PCI_PRODUCT_INTEL_3HS_SMB: 121 case PCI_PRODUCT_INTEL_3HS_U_SMB: 122 case PCI_PRODUCT_INTEL_CORE4G_M_SMB: 123 case PCI_PRODUCT_INTEL_CORE5G_M_SMB: 124 case PCI_PRODUCT_INTEL_CMTLK_SMB: 125 case PCI_PRODUCT_INTEL_BAYTRAIL_PCU_SMB: 126 case PCI_PRODUCT_INTEL_BSW_PCU_SMB: 127 case PCI_PRODUCT_INTEL_APL_SMB: 128 case PCI_PRODUCT_INTEL_GLK_SMB: 129 case PCI_PRODUCT_INTEL_C600_SMBUS: 130 case PCI_PRODUCT_INTEL_C600_SMB_0: 131 case PCI_PRODUCT_INTEL_C600_SMB_1: 132 case PCI_PRODUCT_INTEL_C600_SMB_2: 133 case PCI_PRODUCT_INTEL_C610_SMB: 134 case PCI_PRODUCT_INTEL_C620_SMB: 135 case PCI_PRODUCT_INTEL_C620_SMB_S: 136 case PCI_PRODUCT_INTEL_EP80579_SMB: 137 case PCI_PRODUCT_INTEL_DH89XXCC_SMB: 138 case PCI_PRODUCT_INTEL_DH89XXCL_SMB: 139 case PCI_PRODUCT_INTEL_C2000_PCU_SMBUS: 140 case PCI_PRODUCT_INTEL_C3K_SMBUS_LEGACY: 141 return 1; 142 } 143 } 144 return 0; 145 } 146 147 static void 148 ichsmb_attach(device_t parent, device_t self, void *aux) 149 { 150 struct ichsmb_softc *sc = device_private(self); 151 struct pci_attach_args *pa = aux; 152 pcireg_t conf; 153 bus_size_t iosize; 154 pci_intr_handle_t ih; 155 const char *intrstr = NULL; 156 char intrbuf[PCI_INTRSTR_LEN]; 157 int flags; 158 159 sc->sc_dev = self; 160 161 pci_aprint_devinfo(pa, NULL); 162 163 /* Read configuration */ 164 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 165 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 166 167 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 168 aprint_error_dev(self, "SMBus disabled\n"); 169 goto out; 170 } 171 172 /* Map I/O space */ 173 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 174 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize)) { 175 aprint_error_dev(self, "can't map I/O space\n"); 176 goto out; 177 } 178 179 sc->sc_poll = 1; 180 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 181 /* No PCI IRQ */ 182 aprint_normal_dev(self, "interrupting at SMI\n"); 183 } else { 184 /* Install interrupt handler */ 185 if (pci_intr_map(pa, &ih) == 0) { 186 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, 187 sizeof(intrbuf)); 188 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, ih, 189 IPL_BIO, ichsmb_intr, sc, device_xname(sc->sc_dev)); 190 if (sc->sc_ih != NULL) { 191 aprint_normal_dev(self, "interrupting at %s\n", 192 intrstr); 193 sc->sc_poll = 0; 194 } 195 } 196 if (sc->sc_poll) 197 aprint_normal_dev(self, "polling\n"); 198 } 199 200 sc->sc_i2c_device = NULL; 201 flags = 0; 202 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 203 ichsmb_rescan(self, "i2cbus", &flags); 204 205 out: if (!pmf_device_register(self, NULL, NULL)) 206 aprint_error_dev(self, "couldn't establish power handler\n"); 207 } 208 209 static int 210 ichsmb_rescan(device_t self, const char *ifattr, const int *flags) 211 { 212 struct ichsmb_softc *sc = device_private(self); 213 struct i2cbus_attach_args iba; 214 215 if (!ifattr_match(ifattr, "i2cbus")) 216 return 0; 217 218 if (sc->sc_i2c_device) 219 return 0; 220 221 /* Attach I2C bus */ 222 sc->sc_i2c_tag.ic_cookie = sc; 223 sc->sc_i2c_tag.ic_acquire_bus = ichsmb_i2c_acquire_bus; 224 sc->sc_i2c_tag.ic_release_bus = ichsmb_i2c_release_bus; 225 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 226 227 memset(&iba, 0, sizeof(iba)); 228 iba.iba_type = I2C_TYPE_SMBUS; 229 iba.iba_tag = &sc->sc_i2c_tag; 230 sc->sc_i2c_device = config_found_ia(self, ifattr, &iba, iicbus_print); 231 232 return 0; 233 } 234 235 static void 236 ichsmb_chdet(device_t self, device_t child) 237 { 238 struct ichsmb_softc *sc = device_private(self); 239 240 if (sc->sc_i2c_device == child) 241 sc->sc_i2c_device = NULL; 242 } 243 244 static int 245 ichsmb_i2c_acquire_bus(void *cookie, int flags) 246 { 247 struct ichsmb_softc *sc = cookie; 248 249 if (cold) 250 return 0; 251 252 mutex_enter(&sc->sc_i2c_mutex); 253 return 0; 254 } 255 256 static void 257 ichsmb_i2c_release_bus(void *cookie, int flags) 258 { 259 struct ichsmb_softc *sc = cookie; 260 261 if (cold) 262 return; 263 264 mutex_exit(&sc->sc_i2c_mutex); 265 } 266 267 static int 268 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 269 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 270 { 271 struct ichsmb_softc *sc = cookie; 272 const uint8_t *b; 273 uint8_t ctl = 0, st; 274 int retries; 275 char fbuf[64]; 276 277 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 278 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 279 len, flags)); 280 281 /* Clear status bits */ 282 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 283 LPCIB_SMB_HS_INTR | LPCIB_SMB_HS_DEVERR | 284 LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED); 285 bus_space_barrier(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 1, 286 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 287 288 /* Wait for bus to be idle */ 289 for (retries = 100; retries > 0; retries--) { 290 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 291 if (!(st & LPCIB_SMB_HS_BUSY)) 292 break; 293 DELAY(ICHIIC_DELAY); 294 } 295 #ifdef ICHIIC_DEBUG 296 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 297 printf("%s: exec: st %s\n", device_xname(sc->sc_dev), fbuf); 298 #endif 299 if (st & LPCIB_SMB_HS_BUSY) 300 return (1); 301 302 if (cold || sc->sc_poll) 303 flags |= I2C_F_POLL; 304 305 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 306 (cmdlen == 0 && len > 1)) 307 return (1); 308 309 /* Setup transfer */ 310 sc->sc_i2c_xfer.op = op; 311 sc->sc_i2c_xfer.buf = buf; 312 sc->sc_i2c_xfer.len = len; 313 sc->sc_i2c_xfer.flags = flags; 314 sc->sc_i2c_xfer.error = 0; 315 316 /* Set slave address and transfer direction */ 317 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 318 LPCIB_SMB_TXSLVA_ADDR(addr) | 319 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 320 321 b = (const uint8_t *)cmdbuf; 322 if (cmdlen > 0) 323 /* Set command byte */ 324 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 325 326 if (I2C_OP_WRITE_P(op)) { 327 /* Write data */ 328 b = buf; 329 if (cmdlen == 0 && len == 1) 330 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 331 LPCIB_SMB_HCMD, b[0]); 332 else if (len > 0) 333 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 334 LPCIB_SMB_HD0, b[0]); 335 if (len > 1) 336 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 337 LPCIB_SMB_HD1, b[1]); 338 } 339 340 /* Set SMBus command */ 341 if (cmdlen == 0) { 342 if (len == 0) 343 ctl = LPCIB_SMB_HC_CMD_QUICK; 344 else 345 ctl = LPCIB_SMB_HC_CMD_BYTE; 346 } else if (len == 1) 347 ctl = LPCIB_SMB_HC_CMD_BDATA; 348 else if (len == 2) 349 ctl = LPCIB_SMB_HC_CMD_WDATA; 350 351 if ((flags & I2C_F_POLL) == 0) 352 ctl |= LPCIB_SMB_HC_INTREN; 353 354 /* Start transaction */ 355 ctl |= LPCIB_SMB_HC_START; 356 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 357 358 if (flags & I2C_F_POLL) { 359 /* Poll for completion */ 360 DELAY(ICHIIC_DELAY); 361 for (retries = 1000; retries > 0; retries--) { 362 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 363 LPCIB_SMB_HS); 364 if ((st & LPCIB_SMB_HS_BUSY) == 0) 365 break; 366 DELAY(ICHIIC_DELAY); 367 } 368 if (st & LPCIB_SMB_HS_BUSY) 369 goto timeout; 370 ichsmb_intr(sc); 371 } else { 372 /* Wait for interrupt */ 373 if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz)) 374 goto timeout; 375 } 376 377 if (sc->sc_i2c_xfer.error) 378 return (1); 379 380 return (0); 381 382 timeout: 383 /* 384 * Transfer timeout. Kill the transaction and clear status bits. 385 */ 386 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 387 aprint_error_dev(sc->sc_dev, 388 "exec: op %d, addr 0x%02x, cmdlen %zd, len %zd, " 389 "flags 0x%02x: timeout, status %s\n", 390 op, addr, cmdlen, len, flags, fbuf); 391 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 392 LPCIB_SMB_HC_KILL); 393 DELAY(ICHIIC_DELAY); 394 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 395 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 396 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 397 aprint_error_dev(sc->sc_dev, "abort failed, status %s\n", 398 fbuf); 399 } 400 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 401 return (1); 402 } 403 404 static int 405 ichsmb_intr(void *arg) 406 { 407 struct ichsmb_softc *sc = arg; 408 uint8_t st; 409 uint8_t *b; 410 size_t len; 411 #ifdef ICHIIC_DEBUG 412 char fbuf[64]; 413 #endif 414 415 /* Read status */ 416 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 417 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 418 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 419 LPCIB_SMB_HS_SMBAL | LPCIB_SMB_HS_BDONE)) == 0) 420 /* Interrupt was not for us */ 421 return (0); 422 423 #ifdef ICHIIC_DEBUG 424 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 425 printf("%s: intr st %s\n", device_xname(sc->sc_dev), fbuf); 426 #endif 427 428 /* Clear status bits */ 429 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 430 431 /* Check for errors */ 432 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 433 sc->sc_i2c_xfer.error = 1; 434 goto done; 435 } 436 437 if (st & LPCIB_SMB_HS_INTR) { 438 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 439 goto done; 440 441 /* Read data */ 442 b = sc->sc_i2c_xfer.buf; 443 len = sc->sc_i2c_xfer.len; 444 if (len > 0) 445 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 446 LPCIB_SMB_HD0); 447 if (len > 1) 448 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 449 LPCIB_SMB_HD1); 450 } 451 452 done: 453 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 454 wakeup(sc); 455 return (1); 456 } 457
Indexes created Thu Oct 02 14:10:14 GMT 2025