ichsmb.c revision 1.50.6.6
1 /* $NetBSD: ichsmb.c,v 1.50.6.6 2022/10/15 10:33:42 martin Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.44 2020/10/07 11:23:05 jsg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.50.6.6 2022/10/15 10:33:42 martin Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/ic/i82801lpcreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #ifdef ICHIIC_DEBUG 45 #define DPRINTF(x) printf x 46 #else 47 #define DPRINTF(x) 48 #endif 49 50 #define ICHIIC_DELAY 100 51 #define ICHIIC_TIMEOUT 1 52 53 struct ichsmb_softc { 54 device_t sc_dev; 55 56 bus_space_tag_t sc_iot; 57 bus_space_handle_t sc_ioh; 58 void * sc_ih; 59 int sc_poll; 60 61 struct i2c_controller sc_i2c_tag; 62 kmutex_t sc_i2c_mutex; 63 struct { 64 i2c_op_t op; 65 void * buf; 66 size_t len; 67 int flags; 68 volatile int error; 69 } sc_i2c_xfer; 70 device_t sc_i2c_device; 71 }; 72 73 static int ichsmb_match(device_t, cfdata_t, void *); 74 static void ichsmb_attach(device_t, device_t, void *); 75 static int ichsmb_rescan(device_t, const char *, const int *); 76 static void ichsmb_chdet(device_t, device_t); 77 78 static int ichsmb_i2c_acquire_bus(void *, int); 79 static void ichsmb_i2c_release_bus(void *, int); 80 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 81 size_t, void *, size_t, int); 82 83 static int ichsmb_intr(void *); 84 85 86 CFATTACH_DECL3_NEW(ichsmb, sizeof(struct ichsmb_softc), 87 ichsmb_match, ichsmb_attach, NULL, NULL, ichsmb_rescan, ichsmb_chdet, 0); 88 89 90 static int 91 ichsmb_match(device_t parent, cfdata_t match, void *aux) 92 { 93 struct pci_attach_args *pa = aux; 94 95 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 96 switch (PCI_PRODUCT(pa->pa_id)) { 97 case PCI_PRODUCT_INTEL_6300ESB_SMB: 98 case PCI_PRODUCT_INTEL_63XXESB_SMB: 99 case PCI_PRODUCT_INTEL_82801AA_SMB: 100 case PCI_PRODUCT_INTEL_82801AB_SMB: 101 case PCI_PRODUCT_INTEL_82801BA_SMB: 102 case PCI_PRODUCT_INTEL_82801CA_SMB: 103 case PCI_PRODUCT_INTEL_82801DB_SMB: 104 case PCI_PRODUCT_INTEL_82801E_SMB: 105 case PCI_PRODUCT_INTEL_82801EB_SMB: 106 case PCI_PRODUCT_INTEL_82801FB_SMB: 107 case PCI_PRODUCT_INTEL_82801G_SMB: 108 case PCI_PRODUCT_INTEL_82801H_SMB: 109 case PCI_PRODUCT_INTEL_82801I_SMB: 110 case PCI_PRODUCT_INTEL_82801JD_SMB: 111 case PCI_PRODUCT_INTEL_82801JI_SMB: 112 case PCI_PRODUCT_INTEL_3400_SMB: 113 case PCI_PRODUCT_INTEL_6SERIES_SMB: 114 case PCI_PRODUCT_INTEL_7SERIES_SMB: 115 case PCI_PRODUCT_INTEL_8SERIES_SMB: 116 case PCI_PRODUCT_INTEL_9SERIES_SMB: 117 case PCI_PRODUCT_INTEL_100SERIES_SMB: 118 case PCI_PRODUCT_INTEL_100SERIES_LP_SMB: 119 case PCI_PRODUCT_INTEL_2HS_SMB: 120 case PCI_PRODUCT_INTEL_3HS_SMB: 121 case PCI_PRODUCT_INTEL_3HS_U_SMB: 122 case PCI_PRODUCT_INTEL_4HS_H_SMB: 123 case PCI_PRODUCT_INTEL_4HS_V_SMB: 124 case PCI_PRODUCT_INTEL_CORE4G_M_SMB: 125 case PCI_PRODUCT_INTEL_CORE5G_M_SMB: 126 case PCI_PRODUCT_INTEL_CMTLK_SMB: 127 case PCI_PRODUCT_INTEL_BAYTRAIL_PCU_SMB: 128 case PCI_PRODUCT_INTEL_BSW_PCU_SMB: 129 case PCI_PRODUCT_INTEL_APL_SMB: 130 case PCI_PRODUCT_INTEL_GLK_SMB: 131 case PCI_PRODUCT_INTEL_EHL_SMB: 132 case PCI_PRODUCT_INTEL_JSL_SMB: 133 case PCI_PRODUCT_INTEL_C600_SMBUS: 134 case PCI_PRODUCT_INTEL_C600_SMB_0: 135 case PCI_PRODUCT_INTEL_C600_SMB_1: 136 case PCI_PRODUCT_INTEL_C600_SMB_2: 137 case PCI_PRODUCT_INTEL_C610_SMB: 138 case PCI_PRODUCT_INTEL_C620_SMB: 139 case PCI_PRODUCT_INTEL_C620_SMB_S: 140 case PCI_PRODUCT_INTEL_EP80579_SMB: 141 case PCI_PRODUCT_INTEL_DH89XXCC_SMB: 142 case PCI_PRODUCT_INTEL_DH89XXCL_SMB: 143 case PCI_PRODUCT_INTEL_C2000_PCU_SMBUS: 144 case PCI_PRODUCT_INTEL_C3K_SMBUS_LEGACY: 145 case PCI_PRODUCT_INTEL_495_YU_SMB: 146 case PCI_PRODUCT_INTEL_5HS_H_SMB: 147 case PCI_PRODUCT_INTEL_5HS_LP_SMB: 148 case PCI_PRODUCT_INTEL_6HS_H_SMB: 149 case PCI_PRODUCT_INTEL_6HS_LP_SMB: 150 return 1; 151 } 152 } 153 return 0; 154 } 155 156 static void 157 ichsmb_attach(device_t parent, device_t self, void *aux) 158 { 159 struct ichsmb_softc *sc = device_private(self); 160 struct pci_attach_args *pa = aux; 161 pcireg_t conf; 162 bus_size_t iosize; 163 pci_intr_handle_t ih; 164 const char *intrstr = NULL; 165 char intrbuf[PCI_INTRSTR_LEN]; 166 int flags; 167 168 sc->sc_dev = self; 169 170 pci_aprint_devinfo(pa, NULL); 171 172 /* Read configuration */ 173 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 174 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 175 176 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 177 aprint_error_dev(self, "SMBus disabled\n"); 178 goto out; 179 } 180 181 /* Map I/O space */ 182 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 183 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize)) { 184 aprint_error_dev(self, "can't map I/O space\n"); 185 goto out; 186 } 187 188 sc->sc_poll = 1; 189 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 190 /* No PCI IRQ */ 191 aprint_normal_dev(self, "interrupting at SMI\n"); 192 } else { 193 /* Install interrupt handler */ 194 if (pci_intr_map(pa, &ih) == 0) { 195 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, 196 sizeof(intrbuf)); 197 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, ih, 198 IPL_BIO, ichsmb_intr, sc, device_xname(sc->sc_dev)); 199 if (sc->sc_ih != NULL) { 200 aprint_normal_dev(self, "interrupting at %s\n", 201 intrstr); 202 sc->sc_poll = 0; 203 } 204 } 205 if (sc->sc_poll) 206 aprint_normal_dev(self, "polling\n"); 207 } 208 209 sc->sc_i2c_device = NULL; 210 flags = 0; 211 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 212 ichsmb_rescan(self, "i2cbus", &flags); 213 214 out: if (!pmf_device_register(self, NULL, NULL)) 215 aprint_error_dev(self, "couldn't establish power handler\n"); 216 } 217 218 static int 219 ichsmb_rescan(device_t self, const char *ifattr, const int *flags) 220 { 221 struct ichsmb_softc *sc = device_private(self); 222 struct i2cbus_attach_args iba; 223 224 if (!ifattr_match(ifattr, "i2cbus")) 225 return 0; 226 227 if (sc->sc_i2c_device) 228 return 0; 229 230 /* Attach I2C bus */ 231 sc->sc_i2c_tag.ic_cookie = sc; 232 sc->sc_i2c_tag.ic_acquire_bus = ichsmb_i2c_acquire_bus; 233 sc->sc_i2c_tag.ic_release_bus = ichsmb_i2c_release_bus; 234 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 235 236 memset(&iba, 0, sizeof(iba)); 237 iba.iba_type = I2C_TYPE_SMBUS; 238 iba.iba_tag = &sc->sc_i2c_tag; 239 sc->sc_i2c_device = config_found_ia(self, ifattr, &iba, iicbus_print); 240 241 return 0; 242 } 243 244 static void 245 ichsmb_chdet(device_t self, device_t child) 246 { 247 struct ichsmb_softc *sc = device_private(self); 248 249 if (sc->sc_i2c_device == child) 250 sc->sc_i2c_device = NULL; 251 } 252 253 static int 254 ichsmb_i2c_acquire_bus(void *cookie, int flags) 255 { 256 struct ichsmb_softc *sc = cookie; 257 258 if (cold) 259 return 0; 260 261 mutex_enter(&sc->sc_i2c_mutex); 262 return 0; 263 } 264 265 static void 266 ichsmb_i2c_release_bus(void *cookie, int flags) 267 { 268 struct ichsmb_softc *sc = cookie; 269 270 if (cold) 271 return; 272 273 mutex_exit(&sc->sc_i2c_mutex); 274 } 275 276 static int 277 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 278 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 279 { 280 struct ichsmb_softc *sc = cookie; 281 const uint8_t *b; 282 uint8_t ctl = 0, st; 283 int retries; 284 char fbuf[64]; 285 286 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 287 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 288 len, flags)); 289 290 /* Clear status bits */ 291 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 292 LPCIB_SMB_HS_INTR | LPCIB_SMB_HS_DEVERR | 293 LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED); 294 bus_space_barrier(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 1, 295 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 296 297 /* Wait for bus to be idle */ 298 for (retries = 100; retries > 0; retries--) { 299 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 300 if (!(st & LPCIB_SMB_HS_BUSY)) 301 break; 302 DELAY(ICHIIC_DELAY); 303 } 304 #ifdef ICHIIC_DEBUG 305 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 306 printf("%s: exec: st %s\n", device_xname(sc->sc_dev), fbuf); 307 #endif 308 if (st & LPCIB_SMB_HS_BUSY) 309 return (1); 310 311 if (cold || sc->sc_poll) 312 flags |= I2C_F_POLL; 313 314 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 315 (cmdlen == 0 && len > 1)) 316 return (1); 317 318 /* Setup transfer */ 319 sc->sc_i2c_xfer.op = op; 320 sc->sc_i2c_xfer.buf = buf; 321 sc->sc_i2c_xfer.len = len; 322 sc->sc_i2c_xfer.flags = flags; 323 sc->sc_i2c_xfer.error = 0; 324 325 /* Set slave address and transfer direction */ 326 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 327 LPCIB_SMB_TXSLVA_ADDR(addr) | 328 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 329 330 b = (const uint8_t *)cmdbuf; 331 if (cmdlen > 0) 332 /* Set command byte */ 333 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 334 335 if (I2C_OP_WRITE_P(op)) { 336 /* Write data */ 337 b = buf; 338 if (cmdlen == 0 && len == 1) 339 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 340 LPCIB_SMB_HCMD, b[0]); 341 else if (len > 0) 342 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 343 LPCIB_SMB_HD0, b[0]); 344 if (len > 1) 345 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 346 LPCIB_SMB_HD1, b[1]); 347 } 348 349 /* Set SMBus command */ 350 if (cmdlen == 0) { 351 if (len == 0) 352 ctl = LPCIB_SMB_HC_CMD_QUICK; 353 else 354 ctl = LPCIB_SMB_HC_CMD_BYTE; 355 } else if (len == 1) 356 ctl = LPCIB_SMB_HC_CMD_BDATA; 357 else if (len == 2) 358 ctl = LPCIB_SMB_HC_CMD_WDATA; 359 360 if ((flags & I2C_F_POLL) == 0) 361 ctl |= LPCIB_SMB_HC_INTREN; 362 363 /* Start transaction */ 364 ctl |= LPCIB_SMB_HC_START; 365 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 366 367 if (flags & I2C_F_POLL) { 368 /* Poll for completion */ 369 DELAY(ICHIIC_DELAY); 370 for (retries = 1000; retries > 0; retries--) { 371 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 372 LPCIB_SMB_HS); 373 if ((st & LPCIB_SMB_HS_BUSY) == 0) 374 break; 375 DELAY(ICHIIC_DELAY); 376 } 377 if (st & LPCIB_SMB_HS_BUSY) 378 goto timeout; 379 ichsmb_intr(sc); 380 } else { 381 /* Wait for interrupt */ 382 if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz)) 383 goto timeout; 384 } 385 386 if (sc->sc_i2c_xfer.error) 387 return (1); 388 389 return (0); 390 391 timeout: 392 /* 393 * Transfer timeout. Kill the transaction and clear status bits. 394 */ 395 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 396 LPCIB_SMB_HC_KILL); 397 DELAY(ICHIIC_DELAY); 398 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 399 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 400 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 401 aprint_error_dev(sc->sc_dev, "abort failed, status %s\n", 402 fbuf); 403 } 404 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 405 return (1); 406 } 407 408 static int 409 ichsmb_intr(void *arg) 410 { 411 struct ichsmb_softc *sc = arg; 412 uint8_t st; 413 uint8_t *b; 414 size_t len; 415 #ifdef ICHIIC_DEBUG 416 char fbuf[64]; 417 #endif 418 419 /* Read status */ 420 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 421 422 /* Clear status bits */ 423 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 424 425 /* XXX Ignore SMBALERT# for now */ 426 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 427 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 428 LPCIB_SMB_HS_BDONE)) == 0) 429 /* Interrupt was not for us */ 430 return (0); 431 432 #ifdef ICHIIC_DEBUG 433 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 434 printf("%s: intr st %s\n", device_xname(sc->sc_dev), fbuf); 435 #endif 436 437 /* Check for errors */ 438 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 439 sc->sc_i2c_xfer.error = 1; 440 goto done; 441 } 442 443 if (st & LPCIB_SMB_HS_INTR) { 444 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 445 goto done; 446 447 /* Read data */ 448 b = sc->sc_i2c_xfer.buf; 449 len = sc->sc_i2c_xfer.len; 450 if (len > 0) 451 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 452 LPCIB_SMB_HD0); 453 if (len > 1) 454 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 455 LPCIB_SMB_HD1); 456 } 457 458 done: 459 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 460 wakeup(sc); 461 return (1); 462 } 463
Indexes created Thu Oct 02 14:10:14 GMT 2025