ichsmb.c revision 1.52
1 /* $NetBSD: ichsmb.c,v 1.52 2018/02/22 05:09:56 msaitoh Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.18 2007/05/03 09:36:26 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.52 2018/02/22 05:09:56 msaitoh Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/ic/i82801lpcreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #ifdef ICHIIC_DEBUG 45 #define DPRINTF(x) printf x 46 #else 47 #define DPRINTF(x) 48 #endif 49 50 #define ICHIIC_DELAY 100 51 #define ICHIIC_TIMEOUT 1 52 53 struct ichsmb_softc { 54 device_t sc_dev; 55 56 bus_space_tag_t sc_iot; 57 bus_space_handle_t sc_ioh; 58 void * sc_ih; 59 int sc_poll; 60 61 struct i2c_controller sc_i2c_tag; 62 kmutex_t sc_i2c_mutex; 63 struct { 64 i2c_op_t op; 65 void * buf; 66 size_t len; 67 int flags; 68 volatile int error; 69 } sc_i2c_xfer; 70 device_t sc_i2c_device; 71 }; 72 73 static int ichsmb_match(device_t, cfdata_t, void *); 74 static void ichsmb_attach(device_t, device_t, void *); 75 static int ichsmb_rescan(device_t, const char *, const int *); 76 static void ichsmb_chdet(device_t, device_t); 77 78 static int ichsmb_i2c_acquire_bus(void *, int); 79 static void ichsmb_i2c_release_bus(void *, int); 80 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 81 size_t, void *, size_t, int); 82 83 static int ichsmb_intr(void *); 84 85 86 CFATTACH_DECL3_NEW(ichsmb, sizeof(struct ichsmb_softc), 87 ichsmb_match, ichsmb_attach, NULL, NULL, ichsmb_rescan, ichsmb_chdet, 0); 88 89 90 static int 91 ichsmb_match(device_t parent, cfdata_t match, void *aux) 92 { 93 struct pci_attach_args *pa = aux; 94 95 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 96 switch (PCI_PRODUCT(pa->pa_id)) { 97 case PCI_PRODUCT_INTEL_6300ESB_SMB: 98 case PCI_PRODUCT_INTEL_63XXESB_SMB: 99 case PCI_PRODUCT_INTEL_82801AA_SMB: 100 case PCI_PRODUCT_INTEL_82801AB_SMB: 101 case PCI_PRODUCT_INTEL_82801BA_SMB: 102 case PCI_PRODUCT_INTEL_82801CA_SMB: 103 case PCI_PRODUCT_INTEL_82801DB_SMB: 104 case PCI_PRODUCT_INTEL_82801E_SMB: 105 case PCI_PRODUCT_INTEL_82801EB_SMB: 106 case PCI_PRODUCT_INTEL_82801FB_SMB: 107 case PCI_PRODUCT_INTEL_82801G_SMB: 108 case PCI_PRODUCT_INTEL_82801H_SMB: 109 case PCI_PRODUCT_INTEL_82801I_SMB: 110 case PCI_PRODUCT_INTEL_82801JD_SMB: 111 case PCI_PRODUCT_INTEL_82801JI_SMB: 112 case PCI_PRODUCT_INTEL_3400_SMB: 113 case PCI_PRODUCT_INTEL_6SERIES_SMB: 114 case PCI_PRODUCT_INTEL_7SERIES_SMB: 115 case PCI_PRODUCT_INTEL_8SERIES_SMB: 116 case PCI_PRODUCT_INTEL_9SERIES_SMB: 117 case PCI_PRODUCT_INTEL_100SERIES_SMB: 118 case PCI_PRODUCT_INTEL_100SERIES_LP_SMB: 119 case PCI_PRODUCT_INTEL_2HS_SMB: 120 case PCI_PRODUCT_INTEL_CORE4G_M_SMB: 121 case PCI_PRODUCT_INTEL_CORE5G_M_SMB: 122 case PCI_PRODUCT_INTEL_BAYTRAIL_PCU_SMB: 123 case PCI_PRODUCT_INTEL_BSW_PCU_SMB: 124 case PCI_PRODUCT_INTEL_C600_SMBUS: 125 case PCI_PRODUCT_INTEL_C600_SMB_0: 126 case PCI_PRODUCT_INTEL_C600_SMB_1: 127 case PCI_PRODUCT_INTEL_C600_SMB_2: 128 case PCI_PRODUCT_INTEL_C610_SMB: 129 case PCI_PRODUCT_INTEL_C620_SMB: 130 case PCI_PRODUCT_INTEL_C620_SMB_S: 131 case PCI_PRODUCT_INTEL_EP80579_SMB: 132 case PCI_PRODUCT_INTEL_DH89XXCC_SMB: 133 case PCI_PRODUCT_INTEL_DH89XXCL_SMB: 134 case PCI_PRODUCT_INTEL_C2000_PCU_SMBUS: 135 case PCI_PRODUCT_INTEL_C3K_SMBUS_LEGACY: 136 return 1; 137 } 138 } 139 return 0; 140 } 141 142 static void 143 ichsmb_attach(device_t parent, device_t self, void *aux) 144 { 145 struct ichsmb_softc *sc = device_private(self); 146 struct pci_attach_args *pa = aux; 147 pcireg_t conf; 148 bus_size_t iosize; 149 pci_intr_handle_t ih; 150 const char *intrstr = NULL; 151 char intrbuf[PCI_INTRSTR_LEN]; 152 int flags; 153 154 sc->sc_dev = self; 155 156 pci_aprint_devinfo(pa, NULL); 157 158 /* Read configuration */ 159 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 160 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 161 162 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 163 aprint_error_dev(self, "SMBus disabled\n"); 164 goto out; 165 } 166 167 /* Map I/O space */ 168 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 169 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize)) { 170 aprint_error_dev(self, "can't map I/O space\n"); 171 goto out; 172 } 173 174 sc->sc_poll = 1; 175 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 176 /* No PCI IRQ */ 177 aprint_normal_dev(self, "interrupting at SMI\n"); 178 } else { 179 /* Install interrupt handler */ 180 if (pci_intr_map(pa, &ih) == 0) { 181 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, 182 sizeof(intrbuf)); 183 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, ih, 184 IPL_BIO, ichsmb_intr, sc, device_xname(sc->sc_dev)); 185 if (sc->sc_ih != NULL) { 186 aprint_normal_dev(self, "interrupting at %s\n", 187 intrstr); 188 sc->sc_poll = 0; 189 } 190 } 191 if (sc->sc_poll) 192 aprint_normal_dev(self, "polling\n"); 193 } 194 195 sc->sc_i2c_device = NULL; 196 flags = 0; 197 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 198 ichsmb_rescan(self, "i2cbus", &flags); 199 200 out: if (!pmf_device_register(self, NULL, NULL)) 201 aprint_error_dev(self, "couldn't establish power handler\n"); 202 } 203 204 static int 205 ichsmb_rescan(device_t self, const char *ifattr, const int *flags) 206 { 207 struct ichsmb_softc *sc = device_private(self); 208 struct i2cbus_attach_args iba; 209 210 if (!ifattr_match(ifattr, "i2cbus")) 211 return 0; 212 213 if (sc->sc_i2c_device) 214 return 0; 215 216 /* Attach I2C bus */ 217 sc->sc_i2c_tag.ic_cookie = sc; 218 sc->sc_i2c_tag.ic_acquire_bus = ichsmb_i2c_acquire_bus; 219 sc->sc_i2c_tag.ic_release_bus = ichsmb_i2c_release_bus; 220 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 221 222 memset(&iba, 0, sizeof(iba)); 223 iba.iba_type = I2C_TYPE_SMBUS; 224 iba.iba_tag = &sc->sc_i2c_tag; 225 sc->sc_i2c_device = config_found_ia(self, ifattr, &iba, iicbus_print); 226 227 return 0; 228 } 229 230 static void 231 ichsmb_chdet(device_t self, device_t child) 232 { 233 struct ichsmb_softc *sc = device_private(self); 234 235 if (sc->sc_i2c_device == child) 236 sc->sc_i2c_device = NULL; 237 238 } 239 240 static int 241 ichsmb_i2c_acquire_bus(void *cookie, int flags) 242 { 243 struct ichsmb_softc *sc = cookie; 244 245 if (cold) 246 return 0; 247 248 mutex_enter(&sc->sc_i2c_mutex); 249 return 0; 250 } 251 252 static void 253 ichsmb_i2c_release_bus(void *cookie, int flags) 254 { 255 struct ichsmb_softc *sc = cookie; 256 257 if (cold) 258 return; 259 260 mutex_exit(&sc->sc_i2c_mutex); 261 } 262 263 static int 264 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 265 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 266 { 267 struct ichsmb_softc *sc = cookie; 268 const uint8_t *b; 269 uint8_t ctl = 0, st; 270 int retries; 271 char fbuf[64]; 272 273 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 274 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 275 len, flags)); 276 277 /* Clear status bits */ 278 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 279 LPCIB_SMB_HS_INTR | LPCIB_SMB_HS_DEVERR | 280 LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED); 281 bus_space_barrier(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 1, 282 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 283 284 /* Wait for bus to be idle */ 285 for (retries = 100; retries > 0; retries--) { 286 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 287 if (!(st & LPCIB_SMB_HS_BUSY)) 288 break; 289 DELAY(ICHIIC_DELAY); 290 } 291 #ifdef ICHIIC_DEBUG 292 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 293 printf("%s: exec: st %s\n", device_xname(sc->sc_dev), fbuf); 294 #endif 295 if (st & LPCIB_SMB_HS_BUSY) 296 return (1); 297 298 if (cold || sc->sc_poll) 299 flags |= I2C_F_POLL; 300 301 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 302 (cmdlen == 0 && len > 1)) 303 return (1); 304 305 /* Setup transfer */ 306 sc->sc_i2c_xfer.op = op; 307 sc->sc_i2c_xfer.buf = buf; 308 sc->sc_i2c_xfer.len = len; 309 sc->sc_i2c_xfer.flags = flags; 310 sc->sc_i2c_xfer.error = 0; 311 312 /* Set slave address and transfer direction */ 313 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 314 LPCIB_SMB_TXSLVA_ADDR(addr) | 315 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 316 317 b = (const uint8_t *)cmdbuf; 318 if (cmdlen > 0) 319 /* Set command byte */ 320 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 321 322 if (I2C_OP_WRITE_P(op)) { 323 /* Write data */ 324 b = buf; 325 if (cmdlen == 0 && len == 1) 326 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 327 LPCIB_SMB_HCMD, b[0]); 328 else if (len > 0) 329 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 330 LPCIB_SMB_HD0, b[0]); 331 if (len > 1) 332 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 333 LPCIB_SMB_HD1, b[1]); 334 } 335 336 /* Set SMBus command */ 337 if (cmdlen == 0) { 338 if (len == 0) 339 ctl = LPCIB_SMB_HC_CMD_QUICK; 340 else 341 ctl = LPCIB_SMB_HC_CMD_BYTE; 342 } else if (len == 1) 343 ctl = LPCIB_SMB_HC_CMD_BDATA; 344 else if (len == 2) 345 ctl = LPCIB_SMB_HC_CMD_WDATA; 346 347 if ((flags & I2C_F_POLL) == 0) 348 ctl |= LPCIB_SMB_HC_INTREN; 349 350 /* Start transaction */ 351 ctl |= LPCIB_SMB_HC_START; 352 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 353 354 if (flags & I2C_F_POLL) { 355 /* Poll for completion */ 356 DELAY(ICHIIC_DELAY); 357 for (retries = 1000; retries > 0; retries--) { 358 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 359 LPCIB_SMB_HS); 360 if ((st & LPCIB_SMB_HS_BUSY) == 0) 361 break; 362 DELAY(ICHIIC_DELAY); 363 } 364 if (st & LPCIB_SMB_HS_BUSY) 365 goto timeout; 366 ichsmb_intr(sc); 367 } else { 368 /* Wait for interrupt */ 369 if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz)) 370 goto timeout; 371 } 372 373 if (sc->sc_i2c_xfer.error) 374 return (1); 375 376 return (0); 377 378 timeout: 379 /* 380 * Transfer timeout. Kill the transaction and clear status bits. 381 */ 382 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 383 aprint_error_dev(sc->sc_dev, 384 "exec: op %d, addr 0x%02x, cmdlen %zd, len %zd, " 385 "flags 0x%02x: timeout, status %s\n", 386 op, addr, cmdlen, len, flags, fbuf); 387 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 388 LPCIB_SMB_HC_KILL); 389 DELAY(ICHIIC_DELAY); 390 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 391 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 392 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 393 aprint_error_dev(sc->sc_dev, "abort failed, status %s\n", 394 fbuf); 395 } 396 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 397 return (1); 398 } 399 400 static int 401 ichsmb_intr(void *arg) 402 { 403 struct ichsmb_softc *sc = arg; 404 uint8_t st; 405 uint8_t *b; 406 size_t len; 407 #ifdef ICHIIC_DEBUG 408 char fbuf[64]; 409 #endif 410 411 /* Read status */ 412 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 413 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 414 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 415 LPCIB_SMB_HS_SMBAL | LPCIB_SMB_HS_BDONE)) == 0) 416 /* Interrupt was not for us */ 417 return (0); 418 419 #ifdef ICHIIC_DEBUG 420 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 421 printf("%s: intr st %s\n", device_xname(sc->sc_dev), fbuf); 422 #endif 423 424 /* Clear status bits */ 425 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 426 427 /* Check for errors */ 428 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 429 sc->sc_i2c_xfer.error = 1; 430 goto done; 431 } 432 433 if (st & LPCIB_SMB_HS_INTR) { 434 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 435 goto done; 436 437 /* Read data */ 438 b = sc->sc_i2c_xfer.buf; 439 len = sc->sc_i2c_xfer.len; 440 if (len > 0) 441 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 442 LPCIB_SMB_HD0); 443 if (len > 1) 444 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 445 LPCIB_SMB_HD1); 446 } 447 448 done: 449 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 450 wakeup(sc); 451 return (1); 452 } 453
Indexes created Thu Oct 02 14:10:14 GMT 2025