ichsmb.c revision 1.54
1 /* $NetBSD: ichsmb.c,v 1.54 2018/02/27 00:18:02 pgoyette Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.18 2007/05/03 09:36:26 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.54 2018/02/27 00:18:02 pgoyette Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 #include <sys/module.h> 34 35 #include <sys/bus.h> 36 37 #include <dev/pci/pcidevs.h> 38 #include <dev/pci/pcireg.h> 39 #include <dev/pci/pcivar.h> 40 41 #include <dev/ic/i82801lpcreg.h> 42 43 #include <dev/i2c/i2cvar.h> 44 45 #ifdef ICHIIC_DEBUG 46 #define DPRINTF(x) printf x 47 #else 48 #define DPRINTF(x) 49 #endif 50 51 #define ICHIIC_DELAY 100 52 #define ICHIIC_TIMEOUT 1 53 54 struct ichsmb_softc { 55 device_t sc_dev; 56 57 bus_space_tag_t sc_iot; 58 bus_space_handle_t sc_ioh; 59 void * sc_ih; 60 int sc_poll; 61 62 struct i2c_controller sc_i2c_tag; 63 kmutex_t sc_i2c_mutex; 64 struct { 65 i2c_op_t op; 66 void * buf; 67 size_t len; 68 int flags; 69 volatile int error; 70 } sc_i2c_xfer; 71 device_t sc_i2c_device; 72 }; 73 74 static int ichsmb_match(device_t, cfdata_t, void *); 75 static void ichsmb_attach(device_t, device_t, void *); 76 static int ichsmb_rescan(device_t, const char *, const int *); 77 static void ichsmb_chdet(device_t, device_t); 78 79 static int ichsmb_i2c_acquire_bus(void *, int); 80 static void ichsmb_i2c_release_bus(void *, int); 81 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 82 size_t, void *, size_t, int); 83 84 static int ichsmb_intr(void *); 85 86 #include "ioconf.h" 87 88 CFATTACH_DECL3_NEW(ichsmb, sizeof(struct ichsmb_softc), 89 ichsmb_match, ichsmb_attach, NULL, NULL, ichsmb_rescan, ichsmb_chdet, 0); 90 91 92 static int 93 ichsmb_match(device_t parent, cfdata_t match, void *aux) 94 { 95 struct pci_attach_args *pa = aux; 96 97 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 98 switch (PCI_PRODUCT(pa->pa_id)) { 99 case PCI_PRODUCT_INTEL_6300ESB_SMB: 100 case PCI_PRODUCT_INTEL_63XXESB_SMB: 101 case PCI_PRODUCT_INTEL_82801AA_SMB: 102 case PCI_PRODUCT_INTEL_82801AB_SMB: 103 case PCI_PRODUCT_INTEL_82801BA_SMB: 104 case PCI_PRODUCT_INTEL_82801CA_SMB: 105 case PCI_PRODUCT_INTEL_82801DB_SMB: 106 case PCI_PRODUCT_INTEL_82801E_SMB: 107 case PCI_PRODUCT_INTEL_82801EB_SMB: 108 case PCI_PRODUCT_INTEL_82801FB_SMB: 109 case PCI_PRODUCT_INTEL_82801G_SMB: 110 case PCI_PRODUCT_INTEL_82801H_SMB: 111 case PCI_PRODUCT_INTEL_82801I_SMB: 112 case PCI_PRODUCT_INTEL_82801JD_SMB: 113 case PCI_PRODUCT_INTEL_82801JI_SMB: 114 case PCI_PRODUCT_INTEL_3400_SMB: 115 case PCI_PRODUCT_INTEL_6SERIES_SMB: 116 case PCI_PRODUCT_INTEL_7SERIES_SMB: 117 case PCI_PRODUCT_INTEL_8SERIES_SMB: 118 case PCI_PRODUCT_INTEL_9SERIES_SMB: 119 case PCI_PRODUCT_INTEL_100SERIES_SMB: 120 case PCI_PRODUCT_INTEL_100SERIES_LP_SMB: 121 case PCI_PRODUCT_INTEL_2HS_SMB: 122 case PCI_PRODUCT_INTEL_CORE4G_M_SMB: 123 case PCI_PRODUCT_INTEL_CORE5G_M_SMB: 124 case PCI_PRODUCT_INTEL_BAYTRAIL_PCU_SMB: 125 case PCI_PRODUCT_INTEL_BSW_PCU_SMB: 126 case PCI_PRODUCT_INTEL_C600_SMBUS: 127 case PCI_PRODUCT_INTEL_C600_SMB_0: 128 case PCI_PRODUCT_INTEL_C600_SMB_1: 129 case PCI_PRODUCT_INTEL_C600_SMB_2: 130 case PCI_PRODUCT_INTEL_C610_SMB: 131 case PCI_PRODUCT_INTEL_C620_SMB: 132 case PCI_PRODUCT_INTEL_C620_SMB_S: 133 case PCI_PRODUCT_INTEL_EP80579_SMB: 134 case PCI_PRODUCT_INTEL_DH89XXCC_SMB: 135 case PCI_PRODUCT_INTEL_DH89XXCL_SMB: 136 case PCI_PRODUCT_INTEL_C2000_PCU_SMBUS: 137 case PCI_PRODUCT_INTEL_C3K_SMBUS_LEGACY: 138 return 1; 139 } 140 } 141 return 0; 142 } 143 144 static void 145 ichsmb_attach(device_t parent, device_t self, void *aux) 146 { 147 struct ichsmb_softc *sc = device_private(self); 148 struct pci_attach_args *pa = aux; 149 pcireg_t conf; 150 bus_size_t iosize; 151 pci_intr_handle_t ih; 152 const char *intrstr = NULL; 153 char intrbuf[PCI_INTRSTR_LEN]; 154 int flags; 155 156 sc->sc_dev = self; 157 158 pci_aprint_devinfo(pa, NULL); 159 160 /* Read configuration */ 161 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 162 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 163 164 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 165 aprint_error_dev(self, "SMBus disabled\n"); 166 goto out; 167 } 168 169 /* Map I/O space */ 170 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 171 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize)) { 172 aprint_error_dev(self, "can't map I/O space\n"); 173 goto out; 174 } 175 176 sc->sc_poll = 1; 177 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 178 /* No PCI IRQ */ 179 aprint_normal_dev(self, "interrupting at SMI\n"); 180 } else { 181 /* Install interrupt handler */ 182 if (pci_intr_map(pa, &ih) == 0) { 183 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, 184 sizeof(intrbuf)); 185 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, ih, 186 IPL_BIO, ichsmb_intr, sc, device_xname(sc->sc_dev)); 187 if (sc->sc_ih != NULL) { 188 aprint_normal_dev(self, "interrupting at %s\n", 189 intrstr); 190 sc->sc_poll = 0; 191 } 192 } 193 if (sc->sc_poll) 194 aprint_normal_dev(self, "polling\n"); 195 } 196 197 sc->sc_i2c_device = NULL; 198 flags = 0; 199 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 200 ichsmb_rescan(self, "i2cbus", &flags); 201 202 out: if (!pmf_device_register(self, NULL, NULL)) 203 aprint_error_dev(self, "couldn't establish power handler\n"); 204 } 205 206 static int 207 ichsmb_rescan(device_t self, const char *ifattr, const int *flags) 208 { 209 struct ichsmb_softc *sc = device_private(self); 210 struct i2cbus_attach_args iba; 211 212 if (!ifattr_match(ifattr, "i2cbus")) 213 return 0; 214 215 if (sc->sc_i2c_device) 216 return 0; 217 218 /* Attach I2C bus */ 219 sc->sc_i2c_tag.ic_cookie = sc; 220 sc->sc_i2c_tag.ic_acquire_bus = ichsmb_i2c_acquire_bus; 221 sc->sc_i2c_tag.ic_release_bus = ichsmb_i2c_release_bus; 222 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 223 224 memset(&iba, 0, sizeof(iba)); 225 iba.iba_type = I2C_TYPE_SMBUS; 226 iba.iba_tag = &sc->sc_i2c_tag; 227 sc->sc_i2c_device = config_found_ia(self, ifattr, &iba, iicbus_print); 228 229 return 0; 230 } 231 232 static void 233 ichsmb_chdet(device_t self, device_t child) 234 { 235 struct ichsmb_softc *sc = device_private(self); 236 237 if (sc->sc_i2c_device == child) 238 sc->sc_i2c_device = NULL; 239 240 } 241 242 static int 243 ichsmb_i2c_acquire_bus(void *cookie, int flags) 244 { 245 struct ichsmb_softc *sc = cookie; 246 247 if (cold) 248 return 0; 249 250 mutex_enter(&sc->sc_i2c_mutex); 251 return 0; 252 } 253 254 static void 255 ichsmb_i2c_release_bus(void *cookie, int flags) 256 { 257 struct ichsmb_softc *sc = cookie; 258 259 if (cold) 260 return; 261 262 mutex_exit(&sc->sc_i2c_mutex); 263 } 264 265 static int 266 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 267 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 268 { 269 struct ichsmb_softc *sc = cookie; 270 const uint8_t *b; 271 uint8_t ctl = 0, st; 272 int retries; 273 char fbuf[64]; 274 275 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 276 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 277 len, flags)); 278 279 /* Clear status bits */ 280 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 281 LPCIB_SMB_HS_INTR | LPCIB_SMB_HS_DEVERR | 282 LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED); 283 bus_space_barrier(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 1, 284 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 285 286 /* Wait for bus to be idle */ 287 for (retries = 100; retries > 0; retries--) { 288 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 289 if (!(st & LPCIB_SMB_HS_BUSY)) 290 break; 291 DELAY(ICHIIC_DELAY); 292 } 293 #ifdef ICHIIC_DEBUG 294 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 295 printf("%s: exec: st %s\n", device_xname(sc->sc_dev), fbuf); 296 #endif 297 if (st & LPCIB_SMB_HS_BUSY) 298 return (1); 299 300 if (cold || sc->sc_poll) 301 flags |= I2C_F_POLL; 302 303 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 304 (cmdlen == 0 && len > 1)) 305 return (1); 306 307 /* Setup transfer */ 308 sc->sc_i2c_xfer.op = op; 309 sc->sc_i2c_xfer.buf = buf; 310 sc->sc_i2c_xfer.len = len; 311 sc->sc_i2c_xfer.flags = flags; 312 sc->sc_i2c_xfer.error = 0; 313 314 /* Set slave address and transfer direction */ 315 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 316 LPCIB_SMB_TXSLVA_ADDR(addr) | 317 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 318 319 b = (const uint8_t *)cmdbuf; 320 if (cmdlen > 0) 321 /* Set command byte */ 322 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 323 324 if (I2C_OP_WRITE_P(op)) { 325 /* Write data */ 326 b = buf; 327 if (cmdlen == 0 && len == 1) 328 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 329 LPCIB_SMB_HCMD, b[0]); 330 else if (len > 0) 331 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 332 LPCIB_SMB_HD0, b[0]); 333 if (len > 1) 334 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 335 LPCIB_SMB_HD1, b[1]); 336 } 337 338 /* Set SMBus command */ 339 if (cmdlen == 0) { 340 if (len == 0) 341 ctl = LPCIB_SMB_HC_CMD_QUICK; 342 else 343 ctl = LPCIB_SMB_HC_CMD_BYTE; 344 } else if (len == 1) 345 ctl = LPCIB_SMB_HC_CMD_BDATA; 346 else if (len == 2) 347 ctl = LPCIB_SMB_HC_CMD_WDATA; 348 349 if ((flags & I2C_F_POLL) == 0) 350 ctl |= LPCIB_SMB_HC_INTREN; 351 352 /* Start transaction */ 353 ctl |= LPCIB_SMB_HC_START; 354 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 355 356 if (flags & I2C_F_POLL) { 357 /* Poll for completion */ 358 DELAY(ICHIIC_DELAY); 359 for (retries = 1000; retries > 0; retries--) { 360 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 361 LPCIB_SMB_HS); 362 if ((st & LPCIB_SMB_HS_BUSY) == 0) 363 break; 364 DELAY(ICHIIC_DELAY); 365 } 366 if (st & LPCIB_SMB_HS_BUSY) 367 goto timeout; 368 ichsmb_intr(sc); 369 } else { 370 /* Wait for interrupt */ 371 if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz)) 372 goto timeout; 373 } 374 375 if (sc->sc_i2c_xfer.error) 376 return (1); 377 378 return (0); 379 380 timeout: 381 /* 382 * Transfer timeout. Kill the transaction and clear status bits. 383 */ 384 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 385 aprint_error_dev(sc->sc_dev, 386 "exec: op %d, addr 0x%02x, cmdlen %zd, len %zd, " 387 "flags 0x%02x: timeout, status %s\n", 388 op, addr, cmdlen, len, flags, fbuf); 389 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 390 LPCIB_SMB_HC_KILL); 391 DELAY(ICHIIC_DELAY); 392 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 393 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 394 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 395 aprint_error_dev(sc->sc_dev, "abort failed, status %s\n", 396 fbuf); 397 } 398 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 399 return (1); 400 } 401 402 static int 403 ichsmb_intr(void *arg) 404 { 405 struct ichsmb_softc *sc = arg; 406 uint8_t st; 407 uint8_t *b; 408 size_t len; 409 #ifdef ICHIIC_DEBUG 410 char fbuf[64]; 411 #endif 412 413 /* Read status */ 414 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 415 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 416 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 417 LPCIB_SMB_HS_SMBAL | LPCIB_SMB_HS_BDONE)) == 0) 418 /* Interrupt was not for us */ 419 return (0); 420 421 #ifdef ICHIIC_DEBUG 422 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 423 printf("%s: intr st %s\n", device_xname(sc->sc_dev), fbuf); 424 #endif 425 426 /* Clear status bits */ 427 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 428 429 /* Check for errors */ 430 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 431 sc->sc_i2c_xfer.error = 1; 432 goto done; 433 } 434 435 if (st & LPCIB_SMB_HS_INTR) { 436 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 437 goto done; 438 439 /* Read data */ 440 b = sc->sc_i2c_xfer.buf; 441 len = sc->sc_i2c_xfer.len; 442 if (len > 0) 443 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 444 LPCIB_SMB_HD0); 445 if (len > 1) 446 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 447 LPCIB_SMB_HD1); 448 } 449 450 done: 451 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 452 wakeup(sc); 453 return (1); 454 } 455 456 MODULE(MODULE_CLASS_DRIVER, ichsmb, "pci,iic"); 457 458 #ifdef _MODULE 459 #include "ioconf.c" 460 #endif 461 462 static int 463 ichsmb_modcmd(modcmd_t cmd, void *opaque) 464 { 465 int error = 0; 466 467 switch (cmd) { 468 case MODULE_CMD_INIT: 469 #ifdef _MODULE 470 error = config_init_component(cfdriver_ioconf_ichsmb, 471 cfattach_ioconf_ichsmb, cfdata_ioconf_ichsmb); 472 #endif 473 break; 474 case MODULE_CMD_FINI: 475 #ifdef _MODULE 476 error = config_fini_component(cfdriver_ioconf_ichsmb, 477 cfattach_ioconf_ichsmb, cfdata_ioconf_ichsmb); 478 #endif 479 break; 480 default: 481 #ifdef _MODULE 482 error = ENOTTY; 483 #endif 484 break; 485 } 486 487 return error; 488 } 489
Indexes created Thu Oct 02 14:10:14 GMT 2025