ichsmb.c revision 1.55
1 /* $NetBSD: ichsmb.c,v 1.55 2018/02/28 22:36:02 pgoyette Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.18 2007/05/03 09:36:26 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.55 2018/02/28 22:36:02 pgoyette Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 #include <sys/module.h> 34 35 #include <sys/bus.h> 36 37 #include <dev/pci/pcidevs.h> 38 #include <dev/pci/pcireg.h> 39 #include <dev/pci/pcivar.h> 40 41 #include <dev/ic/i82801lpcreg.h> 42 43 #include <dev/i2c/i2cvar.h> 44 45 #ifdef ICHIIC_DEBUG 46 #define DPRINTF(x) printf x 47 #else 48 #define DPRINTF(x) 49 #endif 50 51 #define ICHIIC_DELAY 100 52 #define ICHIIC_TIMEOUT 1 53 54 struct ichsmb_softc { 55 device_t sc_dev; 56 57 bus_space_tag_t sc_iot; 58 bus_space_handle_t sc_ioh; 59 bus_size_t sc_size; 60 pci_chipset_tag_t sc_pc; 61 void * sc_ih; 62 int sc_poll; 63 64 struct i2c_controller sc_i2c_tag; 65 kmutex_t sc_i2c_mutex; 66 struct { 67 i2c_op_t op; 68 void * buf; 69 size_t len; 70 int flags; 71 volatile int error; 72 } sc_i2c_xfer; 73 device_t sc_i2c_device; 74 }; 75 76 static int ichsmb_match(device_t, cfdata_t, void *); 77 static void ichsmb_attach(device_t, device_t, void *); 78 static int ichsmb_detach(device_t, int); 79 static int ichsmb_rescan(device_t, const char *, const int *); 80 static void ichsmb_chdet(device_t, device_t); 81 82 static int ichsmb_i2c_acquire_bus(void *, int); 83 static void ichsmb_i2c_release_bus(void *, int); 84 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 85 size_t, void *, size_t, int); 86 87 static int ichsmb_intr(void *); 88 89 #include "ioconf.h" 90 91 CFATTACH_DECL3_NEW(ichsmb, sizeof(struct ichsmb_softc), 92 ichsmb_match, ichsmb_attach, ichsmb_detach, NULL, ichsmb_rescan, 93 ichsmb_chdet, 0); 94 95 96 static int 97 ichsmb_match(device_t parent, cfdata_t match, void *aux) 98 { 99 struct pci_attach_args *pa = aux; 100 101 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 102 switch (PCI_PRODUCT(pa->pa_id)) { 103 case PCI_PRODUCT_INTEL_6300ESB_SMB: 104 case PCI_PRODUCT_INTEL_63XXESB_SMB: 105 case PCI_PRODUCT_INTEL_82801AA_SMB: 106 case PCI_PRODUCT_INTEL_82801AB_SMB: 107 case PCI_PRODUCT_INTEL_82801BA_SMB: 108 case PCI_PRODUCT_INTEL_82801CA_SMB: 109 case PCI_PRODUCT_INTEL_82801DB_SMB: 110 case PCI_PRODUCT_INTEL_82801E_SMB: 111 case PCI_PRODUCT_INTEL_82801EB_SMB: 112 case PCI_PRODUCT_INTEL_82801FB_SMB: 113 case PCI_PRODUCT_INTEL_82801G_SMB: 114 case PCI_PRODUCT_INTEL_82801H_SMB: 115 case PCI_PRODUCT_INTEL_82801I_SMB: 116 case PCI_PRODUCT_INTEL_82801JD_SMB: 117 case PCI_PRODUCT_INTEL_82801JI_SMB: 118 case PCI_PRODUCT_INTEL_3400_SMB: 119 case PCI_PRODUCT_INTEL_6SERIES_SMB: 120 case PCI_PRODUCT_INTEL_7SERIES_SMB: 121 case PCI_PRODUCT_INTEL_8SERIES_SMB: 122 case PCI_PRODUCT_INTEL_9SERIES_SMB: 123 case PCI_PRODUCT_INTEL_100SERIES_SMB: 124 case PCI_PRODUCT_INTEL_100SERIES_LP_SMB: 125 case PCI_PRODUCT_INTEL_2HS_SMB: 126 case PCI_PRODUCT_INTEL_CORE4G_M_SMB: 127 case PCI_PRODUCT_INTEL_CORE5G_M_SMB: 128 case PCI_PRODUCT_INTEL_BAYTRAIL_PCU_SMB: 129 case PCI_PRODUCT_INTEL_BSW_PCU_SMB: 130 case PCI_PRODUCT_INTEL_C600_SMBUS: 131 case PCI_PRODUCT_INTEL_C600_SMB_0: 132 case PCI_PRODUCT_INTEL_C600_SMB_1: 133 case PCI_PRODUCT_INTEL_C600_SMB_2: 134 case PCI_PRODUCT_INTEL_C610_SMB: 135 case PCI_PRODUCT_INTEL_C620_SMB: 136 case PCI_PRODUCT_INTEL_C620_SMB_S: 137 case PCI_PRODUCT_INTEL_EP80579_SMB: 138 case PCI_PRODUCT_INTEL_DH89XXCC_SMB: 139 case PCI_PRODUCT_INTEL_DH89XXCL_SMB: 140 case PCI_PRODUCT_INTEL_C2000_PCU_SMBUS: 141 case PCI_PRODUCT_INTEL_C3K_SMBUS_LEGACY: 142 return 1; 143 } 144 } 145 return 0; 146 } 147 148 static void 149 ichsmb_attach(device_t parent, device_t self, void *aux) 150 { 151 struct ichsmb_softc *sc = device_private(self); 152 struct pci_attach_args *pa = aux; 153 pcireg_t conf; 154 pci_intr_handle_t ih; 155 const char *intrstr = NULL; 156 char intrbuf[PCI_INTRSTR_LEN]; 157 int flags; 158 159 sc->sc_dev = self; 160 sc->sc_pc = pa->pa_pc; 161 162 pci_aprint_devinfo(pa, NULL); 163 164 /* Read configuration */ 165 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 166 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 167 168 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 169 aprint_error_dev(self, "SMBus disabled\n"); 170 goto out; 171 } 172 173 /* Map I/O space */ 174 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 175 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_size)) { 176 aprint_error_dev(self, "can't map I/O space\n"); 177 goto out; 178 } 179 180 sc->sc_poll = 1; 181 sc->sc_ih = NULL; 182 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 183 /* No PCI IRQ */ 184 aprint_normal_dev(self, "interrupting at SMI\n"); 185 } else { 186 /* Install interrupt handler */ 187 if (pci_intr_map(pa, &ih) == 0) { 188 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, 189 sizeof(intrbuf)); 190 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, ih, 191 IPL_BIO, ichsmb_intr, sc, device_xname(sc->sc_dev)); 192 if (sc->sc_ih != NULL) { 193 aprint_normal_dev(self, "interrupting at %s\n", 194 intrstr); 195 sc->sc_poll = 0; 196 } 197 } 198 if (sc->sc_poll) 199 aprint_normal_dev(self, "polling\n"); 200 } 201 202 sc->sc_i2c_device = NULL; 203 flags = 0; 204 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 205 ichsmb_rescan(self, "i2cbus", &flags); 206 207 out: if (!pmf_device_register(self, NULL, NULL)) 208 aprint_error_dev(self, "couldn't establish power handler\n"); 209 } 210 211 static int 212 ichsmb_rescan(device_t self, const char *ifattr, const int *flags) 213 { 214 struct ichsmb_softc *sc = device_private(self); 215 struct i2cbus_attach_args iba; 216 217 if (!ifattr_match(ifattr, "i2cbus")) 218 return 0; 219 220 if (sc->sc_i2c_device) 221 return 0; 222 223 /* Attach I2C bus */ 224 sc->sc_i2c_tag.ic_cookie = sc; 225 sc->sc_i2c_tag.ic_acquire_bus = ichsmb_i2c_acquire_bus; 226 sc->sc_i2c_tag.ic_release_bus = ichsmb_i2c_release_bus; 227 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 228 229 memset(&iba, 0, sizeof(iba)); 230 iba.iba_type = I2C_TYPE_SMBUS; 231 iba.iba_tag = &sc->sc_i2c_tag; 232 sc->sc_i2c_device = config_found_ia(self, ifattr, &iba, iicbus_print); 233 234 return 0; 235 } 236 237 static int 238 ichsmb_detach(device_t self, int flags) 239 { 240 struct ichsmb_softc *sc = device_private(self); 241 int error; 242 243 if (sc->sc_i2c_device) { 244 error = config_detach(sc->sc_i2c_device, flags); 245 if (error) 246 return error; 247 } 248 249 mutex_destroy(&sc->sc_i2c_mutex); 250 251 if (sc->sc_ih) 252 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 253 254 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_size); 255 256 return 0; 257 } 258 259 static void 260 ichsmb_chdet(device_t self, device_t child) 261 { 262 struct ichsmb_softc *sc = device_private(self); 263 264 if (sc->sc_i2c_device == child) 265 sc->sc_i2c_device = NULL; 266 } 267 268 static int 269 ichsmb_i2c_acquire_bus(void *cookie, int flags) 270 { 271 struct ichsmb_softc *sc = cookie; 272 273 if (cold) 274 return 0; 275 276 mutex_enter(&sc->sc_i2c_mutex); 277 return 0; 278 } 279 280 static void 281 ichsmb_i2c_release_bus(void *cookie, int flags) 282 { 283 struct ichsmb_softc *sc = cookie; 284 285 if (cold) 286 return; 287 288 mutex_exit(&sc->sc_i2c_mutex); 289 } 290 291 static int 292 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 293 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 294 { 295 struct ichsmb_softc *sc = cookie; 296 const uint8_t *b; 297 uint8_t ctl = 0, st; 298 int retries; 299 char fbuf[64]; 300 301 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 302 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 303 len, flags)); 304 305 /* Clear status bits */ 306 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 307 LPCIB_SMB_HS_INTR | LPCIB_SMB_HS_DEVERR | 308 LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED); 309 bus_space_barrier(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 1, 310 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 311 312 /* Wait for bus to be idle */ 313 for (retries = 100; retries > 0; retries--) { 314 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 315 if (!(st & LPCIB_SMB_HS_BUSY)) 316 break; 317 DELAY(ICHIIC_DELAY); 318 } 319 #ifdef ICHIIC_DEBUG 320 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 321 printf("%s: exec: st %s\n", device_xname(sc->sc_dev), fbuf); 322 #endif 323 if (st & LPCIB_SMB_HS_BUSY) 324 return (1); 325 326 if (cold || sc->sc_poll) 327 flags |= I2C_F_POLL; 328 329 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 330 (cmdlen == 0 && len > 1)) 331 return (1); 332 333 /* Setup transfer */ 334 sc->sc_i2c_xfer.op = op; 335 sc->sc_i2c_xfer.buf = buf; 336 sc->sc_i2c_xfer.len = len; 337 sc->sc_i2c_xfer.flags = flags; 338 sc->sc_i2c_xfer.error = 0; 339 340 /* Set slave address and transfer direction */ 341 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 342 LPCIB_SMB_TXSLVA_ADDR(addr) | 343 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 344 345 b = (const uint8_t *)cmdbuf; 346 if (cmdlen > 0) 347 /* Set command byte */ 348 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 349 350 if (I2C_OP_WRITE_P(op)) { 351 /* Write data */ 352 b = buf; 353 if (cmdlen == 0 && len == 1) 354 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 355 LPCIB_SMB_HCMD, b[0]); 356 else if (len > 0) 357 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 358 LPCIB_SMB_HD0, b[0]); 359 if (len > 1) 360 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 361 LPCIB_SMB_HD1, b[1]); 362 } 363 364 /* Set SMBus command */ 365 if (cmdlen == 0) { 366 if (len == 0) 367 ctl = LPCIB_SMB_HC_CMD_QUICK; 368 else 369 ctl = LPCIB_SMB_HC_CMD_BYTE; 370 } else if (len == 1) 371 ctl = LPCIB_SMB_HC_CMD_BDATA; 372 else if (len == 2) 373 ctl = LPCIB_SMB_HC_CMD_WDATA; 374 375 if ((flags & I2C_F_POLL) == 0) 376 ctl |= LPCIB_SMB_HC_INTREN; 377 378 /* Start transaction */ 379 ctl |= LPCIB_SMB_HC_START; 380 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 381 382 if (flags & I2C_F_POLL) { 383 /* Poll for completion */ 384 DELAY(ICHIIC_DELAY); 385 for (retries = 1000; retries > 0; retries--) { 386 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 387 LPCIB_SMB_HS); 388 if ((st & LPCIB_SMB_HS_BUSY) == 0) 389 break; 390 DELAY(ICHIIC_DELAY); 391 } 392 if (st & LPCIB_SMB_HS_BUSY) 393 goto timeout; 394 ichsmb_intr(sc); 395 } else { 396 /* Wait for interrupt */ 397 if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz)) 398 goto timeout; 399 } 400 401 if (sc->sc_i2c_xfer.error) 402 return (1); 403 404 return (0); 405 406 timeout: 407 /* 408 * Transfer timeout. Kill the transaction and clear status bits. 409 */ 410 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 411 aprint_error_dev(sc->sc_dev, 412 "exec: op %d, addr 0x%02x, cmdlen %zd, len %zd, " 413 "flags 0x%02x: timeout, status %s\n", 414 op, addr, cmdlen, len, flags, fbuf); 415 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 416 LPCIB_SMB_HC_KILL); 417 DELAY(ICHIIC_DELAY); 418 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 419 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 420 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 421 aprint_error_dev(sc->sc_dev, "abort failed, status %s\n", 422 fbuf); 423 } 424 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 425 return (1); 426 } 427 428 static int 429 ichsmb_intr(void *arg) 430 { 431 struct ichsmb_softc *sc = arg; 432 uint8_t st; 433 uint8_t *b; 434 size_t len; 435 #ifdef ICHIIC_DEBUG 436 char fbuf[64]; 437 #endif 438 439 /* Read status */ 440 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 441 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 442 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 443 LPCIB_SMB_HS_SMBAL | LPCIB_SMB_HS_BDONE)) == 0) 444 /* Interrupt was not for us */ 445 return (0); 446 447 #ifdef ICHIIC_DEBUG 448 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 449 printf("%s: intr st %s\n", device_xname(sc->sc_dev), fbuf); 450 #endif 451 452 /* Clear status bits */ 453 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 454 455 /* Check for errors */ 456 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 457 sc->sc_i2c_xfer.error = 1; 458 goto done; 459 } 460 461 if (st & LPCIB_SMB_HS_INTR) { 462 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 463 goto done; 464 465 /* Read data */ 466 b = sc->sc_i2c_xfer.buf; 467 len = sc->sc_i2c_xfer.len; 468 if (len > 0) 469 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 470 LPCIB_SMB_HD0); 471 if (len > 1) 472 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 473 LPCIB_SMB_HD1); 474 } 475 476 done: 477 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 478 wakeup(sc); 479 return (1); 480 } 481 482 MODULE(MODULE_CLASS_DRIVER, ichsmb, "pci,iic"); 483 484 #ifdef _MODULE 485 #include "ioconf.c" 486 #endif 487 488 static int 489 ichsmb_modcmd(modcmd_t cmd, void *opaque) 490 { 491 int error = 0; 492 493 switch (cmd) { 494 case MODULE_CMD_INIT: 495 #ifdef _MODULE 496 error = config_init_component(cfdriver_ioconf_ichsmb, 497 cfattach_ioconf_ichsmb, cfdata_ioconf_ichsmb); 498 #endif 499 break; 500 case MODULE_CMD_FINI: 501 #ifdef _MODULE 502 error = config_fini_component(cfdriver_ioconf_ichsmb, 503 cfattach_ioconf_ichsmb, cfdata_ioconf_ichsmb); 504 #endif 505 break; 506 default: 507 #ifdef _MODULE 508 error = ENOTTY; 509 #endif 510 break; 511 } 512 513 return error; 514 } 515
Indexes created Thu Oct 02 14:10:14 GMT 2025