ichsmb.c revision 1.56.2.1
1 /* $NetBSD: ichsmb.c,v 1.56.2.1 2018/04/16 01:59:58 pgoyette Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.18 2007/05/03 09:36:26 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.56.2.1 2018/04/16 01:59:58 pgoyette Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 #include <sys/module.h> 34 35 #include <sys/bus.h> 36 37 #include <dev/pci/pcidevs.h> 38 #include <dev/pci/pcireg.h> 39 #include <dev/pci/pcivar.h> 40 41 #include <dev/ic/i82801lpcreg.h> 42 43 #include <dev/i2c/i2cvar.h> 44 45 #ifdef ICHIIC_DEBUG 46 #define DPRINTF(x) printf x 47 #else 48 #define DPRINTF(x) 49 #endif 50 51 #define ICHIIC_DELAY 100 52 #define ICHIIC_TIMEOUT 1 53 54 struct ichsmb_softc { 55 device_t sc_dev; 56 57 bus_space_tag_t sc_iot; 58 bus_space_handle_t sc_ioh; 59 bus_size_t sc_size; 60 pci_chipset_tag_t sc_pc; 61 void * sc_ih; 62 int sc_poll; 63 64 struct i2c_controller sc_i2c_tag; 65 kmutex_t sc_i2c_mutex; 66 struct { 67 i2c_op_t op; 68 void * buf; 69 size_t len; 70 int flags; 71 volatile int error; 72 } sc_i2c_xfer; 73 device_t sc_i2c_device; 74 }; 75 76 static int ichsmb_match(device_t, cfdata_t, void *); 77 static void ichsmb_attach(device_t, device_t, void *); 78 static int ichsmb_detach(device_t, int); 79 static int ichsmb_rescan(device_t, const char *, const int *); 80 static void ichsmb_chdet(device_t, device_t); 81 82 static int ichsmb_i2c_acquire_bus(void *, int); 83 static void ichsmb_i2c_release_bus(void *, int); 84 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 85 size_t, void *, size_t, int); 86 87 static int ichsmb_intr(void *); 88 89 #include "ioconf.h" 90 91 CFATTACH_DECL3_NEW(ichsmb, sizeof(struct ichsmb_softc), 92 ichsmb_match, ichsmb_attach, ichsmb_detach, NULL, ichsmb_rescan, 93 ichsmb_chdet, 0); 94 95 96 static int 97 ichsmb_match(device_t parent, cfdata_t match, void *aux) 98 { 99 struct pci_attach_args *pa = aux; 100 101 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 102 switch (PCI_PRODUCT(pa->pa_id)) { 103 case PCI_PRODUCT_INTEL_6300ESB_SMB: 104 case PCI_PRODUCT_INTEL_63XXESB_SMB: 105 case PCI_PRODUCT_INTEL_82801AA_SMB: 106 case PCI_PRODUCT_INTEL_82801AB_SMB: 107 case PCI_PRODUCT_INTEL_82801BA_SMB: 108 case PCI_PRODUCT_INTEL_82801CA_SMB: 109 case PCI_PRODUCT_INTEL_82801DB_SMB: 110 case PCI_PRODUCT_INTEL_82801E_SMB: 111 case PCI_PRODUCT_INTEL_82801EB_SMB: 112 case PCI_PRODUCT_INTEL_82801FB_SMB: 113 case PCI_PRODUCT_INTEL_82801G_SMB: 114 case PCI_PRODUCT_INTEL_82801H_SMB: 115 case PCI_PRODUCT_INTEL_82801I_SMB: 116 case PCI_PRODUCT_INTEL_82801JD_SMB: 117 case PCI_PRODUCT_INTEL_82801JI_SMB: 118 case PCI_PRODUCT_INTEL_3400_SMB: 119 case PCI_PRODUCT_INTEL_6SERIES_SMB: 120 case PCI_PRODUCT_INTEL_7SERIES_SMB: 121 case PCI_PRODUCT_INTEL_8SERIES_SMB: 122 case PCI_PRODUCT_INTEL_9SERIES_SMB: 123 case PCI_PRODUCT_INTEL_100SERIES_SMB: 124 case PCI_PRODUCT_INTEL_100SERIES_LP_SMB: 125 case PCI_PRODUCT_INTEL_2HS_SMB: 126 case PCI_PRODUCT_INTEL_3HS_SMB: 127 case PCI_PRODUCT_INTEL_CORE4G_M_SMB: 128 case PCI_PRODUCT_INTEL_CORE5G_M_SMB: 129 case PCI_PRODUCT_INTEL_BAYTRAIL_PCU_SMB: 130 case PCI_PRODUCT_INTEL_BSW_PCU_SMB: 131 case PCI_PRODUCT_INTEL_APL_SMB: 132 case PCI_PRODUCT_INTEL_GLK_SMB: 133 case PCI_PRODUCT_INTEL_C600_SMBUS: 134 case PCI_PRODUCT_INTEL_C600_SMB_0: 135 case PCI_PRODUCT_INTEL_C600_SMB_1: 136 case PCI_PRODUCT_INTEL_C600_SMB_2: 137 case PCI_PRODUCT_INTEL_C610_SMB: 138 case PCI_PRODUCT_INTEL_C620_SMB: 139 case PCI_PRODUCT_INTEL_C620_SMB_S: 140 case PCI_PRODUCT_INTEL_EP80579_SMB: 141 case PCI_PRODUCT_INTEL_DH89XXCC_SMB: 142 case PCI_PRODUCT_INTEL_DH89XXCL_SMB: 143 case PCI_PRODUCT_INTEL_C2000_PCU_SMBUS: 144 case PCI_PRODUCT_INTEL_C3K_SMBUS_LEGACY: 145 return 1; 146 } 147 } 148 return 0; 149 } 150 151 static void 152 ichsmb_attach(device_t parent, device_t self, void *aux) 153 { 154 struct ichsmb_softc *sc = device_private(self); 155 struct pci_attach_args *pa = aux; 156 pcireg_t conf; 157 pci_intr_handle_t ih; 158 const char *intrstr = NULL; 159 char intrbuf[PCI_INTRSTR_LEN]; 160 int flags; 161 162 sc->sc_dev = self; 163 sc->sc_pc = pa->pa_pc; 164 165 pci_aprint_devinfo(pa, NULL); 166 167 /* Read configuration */ 168 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 169 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 170 171 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 172 aprint_error_dev(self, "SMBus disabled\n"); 173 goto out; 174 } 175 176 /* Map I/O space */ 177 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 178 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_size)) { 179 aprint_error_dev(self, "can't map I/O space\n"); 180 goto out; 181 } 182 183 sc->sc_poll = 1; 184 sc->sc_ih = NULL; 185 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 186 /* No PCI IRQ */ 187 aprint_normal_dev(self, "interrupting at SMI\n"); 188 } else { 189 /* Install interrupt handler */ 190 if (pci_intr_map(pa, &ih) == 0) { 191 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, 192 sizeof(intrbuf)); 193 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, ih, 194 IPL_BIO, ichsmb_intr, sc, device_xname(sc->sc_dev)); 195 if (sc->sc_ih != NULL) { 196 aprint_normal_dev(self, "interrupting at %s\n", 197 intrstr); 198 sc->sc_poll = 0; 199 } 200 } 201 if (sc->sc_poll) 202 aprint_normal_dev(self, "polling\n"); 203 } 204 205 sc->sc_i2c_device = NULL; 206 flags = 0; 207 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 208 ichsmb_rescan(self, "i2cbus", &flags); 209 210 out: if (!pmf_device_register(self, NULL, NULL)) 211 aprint_error_dev(self, "couldn't establish power handler\n"); 212 } 213 214 static int 215 ichsmb_rescan(device_t self, const char *ifattr, const int *flags) 216 { 217 struct ichsmb_softc *sc = device_private(self); 218 struct i2cbus_attach_args iba; 219 220 if (!ifattr_match(ifattr, "i2cbus")) 221 return 0; 222 223 if (sc->sc_i2c_device) 224 return 0; 225 226 /* Attach I2C bus */ 227 sc->sc_i2c_tag.ic_cookie = sc; 228 sc->sc_i2c_tag.ic_acquire_bus = ichsmb_i2c_acquire_bus; 229 sc->sc_i2c_tag.ic_release_bus = ichsmb_i2c_release_bus; 230 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 231 232 memset(&iba, 0, sizeof(iba)); 233 iba.iba_type = I2C_TYPE_SMBUS; 234 iba.iba_tag = &sc->sc_i2c_tag; 235 sc->sc_i2c_device = config_found_ia(self, ifattr, &iba, iicbus_print); 236 237 return 0; 238 } 239 240 static int 241 ichsmb_detach(device_t self, int flags) 242 { 243 struct ichsmb_softc *sc = device_private(self); 244 int error; 245 246 if (sc->sc_i2c_device) { 247 error = config_detach(sc->sc_i2c_device, flags); 248 if (error) 249 return error; 250 } 251 252 mutex_destroy(&sc->sc_i2c_mutex); 253 254 if (sc->sc_ih) 255 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 256 257 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_size); 258 259 return 0; 260 } 261 262 static void 263 ichsmb_chdet(device_t self, device_t child) 264 { 265 struct ichsmb_softc *sc = device_private(self); 266 267 if (sc->sc_i2c_device == child) 268 sc->sc_i2c_device = NULL; 269 } 270 271 static int 272 ichsmb_i2c_acquire_bus(void *cookie, int flags) 273 { 274 struct ichsmb_softc *sc = cookie; 275 276 if (cold) 277 return 0; 278 279 mutex_enter(&sc->sc_i2c_mutex); 280 return 0; 281 } 282 283 static void 284 ichsmb_i2c_release_bus(void *cookie, int flags) 285 { 286 struct ichsmb_softc *sc = cookie; 287 288 if (cold) 289 return; 290 291 mutex_exit(&sc->sc_i2c_mutex); 292 } 293 294 static int 295 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 296 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 297 { 298 struct ichsmb_softc *sc = cookie; 299 const uint8_t *b; 300 uint8_t ctl = 0, st; 301 int retries; 302 char fbuf[64]; 303 304 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 305 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 306 len, flags)); 307 308 /* Clear status bits */ 309 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 310 LPCIB_SMB_HS_INTR | LPCIB_SMB_HS_DEVERR | 311 LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED); 312 bus_space_barrier(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 1, 313 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 314 315 /* Wait for bus to be idle */ 316 for (retries = 100; retries > 0; retries--) { 317 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 318 if (!(st & LPCIB_SMB_HS_BUSY)) 319 break; 320 DELAY(ICHIIC_DELAY); 321 } 322 #ifdef ICHIIC_DEBUG 323 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 324 printf("%s: exec: st %s\n", device_xname(sc->sc_dev), fbuf); 325 #endif 326 if (st & LPCIB_SMB_HS_BUSY) 327 return (1); 328 329 if (cold || sc->sc_poll) 330 flags |= I2C_F_POLL; 331 332 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 333 (cmdlen == 0 && len > 1)) 334 return (1); 335 336 /* Setup transfer */ 337 sc->sc_i2c_xfer.op = op; 338 sc->sc_i2c_xfer.buf = buf; 339 sc->sc_i2c_xfer.len = len; 340 sc->sc_i2c_xfer.flags = flags; 341 sc->sc_i2c_xfer.error = 0; 342 343 /* Set slave address and transfer direction */ 344 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 345 LPCIB_SMB_TXSLVA_ADDR(addr) | 346 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 347 348 b = (const uint8_t *)cmdbuf; 349 if (cmdlen > 0) 350 /* Set command byte */ 351 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 352 353 if (I2C_OP_WRITE_P(op)) { 354 /* Write data */ 355 b = buf; 356 if (cmdlen == 0 && len == 1) 357 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 358 LPCIB_SMB_HCMD, b[0]); 359 else if (len > 0) 360 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 361 LPCIB_SMB_HD0, b[0]); 362 if (len > 1) 363 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 364 LPCIB_SMB_HD1, b[1]); 365 } 366 367 /* Set SMBus command */ 368 if (cmdlen == 0) { 369 if (len == 0) 370 ctl = LPCIB_SMB_HC_CMD_QUICK; 371 else 372 ctl = LPCIB_SMB_HC_CMD_BYTE; 373 } else if (len == 1) 374 ctl = LPCIB_SMB_HC_CMD_BDATA; 375 else if (len == 2) 376 ctl = LPCIB_SMB_HC_CMD_WDATA; 377 378 if ((flags & I2C_F_POLL) == 0) 379 ctl |= LPCIB_SMB_HC_INTREN; 380 381 /* Start transaction */ 382 ctl |= LPCIB_SMB_HC_START; 383 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 384 385 if (flags & I2C_F_POLL) { 386 /* Poll for completion */ 387 DELAY(ICHIIC_DELAY); 388 for (retries = 1000; retries > 0; retries--) { 389 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 390 LPCIB_SMB_HS); 391 if ((st & LPCIB_SMB_HS_BUSY) == 0) 392 break; 393 DELAY(ICHIIC_DELAY); 394 } 395 if (st & LPCIB_SMB_HS_BUSY) 396 goto timeout; 397 ichsmb_intr(sc); 398 } else { 399 /* Wait for interrupt */ 400 if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz)) 401 goto timeout; 402 } 403 404 if (sc->sc_i2c_xfer.error) 405 return (1); 406 407 return (0); 408 409 timeout: 410 /* 411 * Transfer timeout. Kill the transaction and clear status bits. 412 */ 413 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 414 aprint_error_dev(sc->sc_dev, 415 "exec: op %d, addr 0x%02x, cmdlen %zd, len %zd, " 416 "flags 0x%02x: timeout, status %s\n", 417 op, addr, cmdlen, len, flags, fbuf); 418 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 419 LPCIB_SMB_HC_KILL); 420 DELAY(ICHIIC_DELAY); 421 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 422 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 423 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 424 aprint_error_dev(sc->sc_dev, "abort failed, status %s\n", 425 fbuf); 426 } 427 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 428 return (1); 429 } 430 431 static int 432 ichsmb_intr(void *arg) 433 { 434 struct ichsmb_softc *sc = arg; 435 uint8_t st; 436 uint8_t *b; 437 size_t len; 438 #ifdef ICHIIC_DEBUG 439 char fbuf[64]; 440 #endif 441 442 /* Read status */ 443 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 444 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 445 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 446 LPCIB_SMB_HS_SMBAL | LPCIB_SMB_HS_BDONE)) == 0) 447 /* Interrupt was not for us */ 448 return (0); 449 450 #ifdef ICHIIC_DEBUG 451 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 452 printf("%s: intr st %s\n", device_xname(sc->sc_dev), fbuf); 453 #endif 454 455 /* Clear status bits */ 456 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 457 458 /* Check for errors */ 459 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 460 sc->sc_i2c_xfer.error = 1; 461 goto done; 462 } 463 464 if (st & LPCIB_SMB_HS_INTR) { 465 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 466 goto done; 467 468 /* Read data */ 469 b = sc->sc_i2c_xfer.buf; 470 len = sc->sc_i2c_xfer.len; 471 if (len > 0) 472 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 473 LPCIB_SMB_HD0); 474 if (len > 1) 475 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 476 LPCIB_SMB_HD1); 477 } 478 479 done: 480 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 481 wakeup(sc); 482 return (1); 483 } 484 485 MODULE(MODULE_CLASS_DRIVER, ichsmb, "pci,iic"); 486 487 #ifdef _MODULE 488 #include "ioconf.c" 489 #endif 490 491 static int 492 ichsmb_modcmd(modcmd_t cmd, void *opaque) 493 { 494 int error = 0; 495 496 switch (cmd) { 497 case MODULE_CMD_INIT: 498 #ifdef _MODULE 499 error = config_init_component(cfdriver_ioconf_ichsmb, 500 cfattach_ioconf_ichsmb, cfdata_ioconf_ichsmb); 501 #endif 502 break; 503 case MODULE_CMD_FINI: 504 #ifdef _MODULE 505 error = config_fini_component(cfdriver_ioconf_ichsmb, 506 cfattach_ioconf_ichsmb, cfdata_ioconf_ichsmb); 507 #endif 508 break; 509 default: 510 #ifdef _MODULE 511 error = ENOTTY; 512 #endif 513 break; 514 } 515 516 return error; 517 } 518
Indexes created Thu Oct 02 14:10:14 GMT 2025