ichsmb.c revision 1.57.2.3
1 /* $NetBSD: ichsmb.c,v 1.57.2.3 2020/04/21 18:42:16 martin Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.18 2007/05/03 09:36:26 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.57.2.3 2020/04/21 18:42:16 martin Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/condvar.h> 33 #include <sys/proc.h> 34 #include <sys/module.h> 35 36 #include <sys/bus.h> 37 38 #include <dev/pci/pcidevs.h> 39 #include <dev/pci/pcireg.h> 40 #include <dev/pci/pcivar.h> 41 42 #include <dev/ic/i82801lpcreg.h> 43 44 #include <dev/i2c/i2cvar.h> 45 46 #ifdef ICHIIC_DEBUG 47 #define DPRINTF(x) printf x 48 #else 49 #define DPRINTF(x) 50 #endif 51 52 #define ICHIIC_DELAY 100 53 #define ICHIIC_TIMEOUT 1 54 55 struct ichsmb_softc { 56 device_t sc_dev; 57 58 bus_space_tag_t sc_iot; 59 bus_space_handle_t sc_ioh; 60 bus_size_t sc_size; 61 pci_chipset_tag_t sc_pc; 62 void * sc_ih; 63 int sc_poll; 64 pci_intr_handle_t *sc_pihp; 65 66 kmutex_t sc_exec_lock; 67 kcondvar_t sc_exec_wait; 68 69 struct i2c_controller sc_i2c_tag; 70 struct { 71 i2c_op_t op; 72 void * buf; 73 size_t len; 74 int flags; 75 int error; 76 bool done; 77 } sc_i2c_xfer; 78 device_t sc_i2c_device; 79 }; 80 81 static int ichsmb_match(device_t, cfdata_t, void *); 82 static void ichsmb_attach(device_t, device_t, void *); 83 static int ichsmb_detach(device_t, int); 84 static int ichsmb_rescan(device_t, const char *, const int *); 85 static void ichsmb_chdet(device_t, device_t); 86 87 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 88 size_t, void *, size_t, int); 89 90 static int ichsmb_intr(void *); 91 92 #include "ioconf.h" 93 94 CFATTACH_DECL3_NEW(ichsmb, sizeof(struct ichsmb_softc), 95 ichsmb_match, ichsmb_attach, ichsmb_detach, NULL, ichsmb_rescan, 96 ichsmb_chdet, DVF_DETACH_SHUTDOWN); 97 98 99 static int 100 ichsmb_match(device_t parent, cfdata_t match, void *aux) 101 { 102 struct pci_attach_args *pa = aux; 103 104 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 105 switch (PCI_PRODUCT(pa->pa_id)) { 106 case PCI_PRODUCT_INTEL_6300ESB_SMB: 107 case PCI_PRODUCT_INTEL_63XXESB_SMB: 108 case PCI_PRODUCT_INTEL_82801AA_SMB: 109 case PCI_PRODUCT_INTEL_82801AB_SMB: 110 case PCI_PRODUCT_INTEL_82801BA_SMB: 111 case PCI_PRODUCT_INTEL_82801CA_SMB: 112 case PCI_PRODUCT_INTEL_82801DB_SMB: 113 case PCI_PRODUCT_INTEL_82801E_SMB: 114 case PCI_PRODUCT_INTEL_82801EB_SMB: 115 case PCI_PRODUCT_INTEL_82801FB_SMB: 116 case PCI_PRODUCT_INTEL_82801G_SMB: 117 case PCI_PRODUCT_INTEL_82801H_SMB: 118 case PCI_PRODUCT_INTEL_82801I_SMB: 119 case PCI_PRODUCT_INTEL_82801JD_SMB: 120 case PCI_PRODUCT_INTEL_82801JI_SMB: 121 case PCI_PRODUCT_INTEL_3400_SMB: 122 case PCI_PRODUCT_INTEL_6SERIES_SMB: 123 case PCI_PRODUCT_INTEL_7SERIES_SMB: 124 case PCI_PRODUCT_INTEL_8SERIES_SMB: 125 case PCI_PRODUCT_INTEL_9SERIES_SMB: 126 case PCI_PRODUCT_INTEL_100SERIES_SMB: 127 case PCI_PRODUCT_INTEL_100SERIES_LP_SMB: 128 case PCI_PRODUCT_INTEL_2HS_SMB: 129 case PCI_PRODUCT_INTEL_3HS_SMB: 130 case PCI_PRODUCT_INTEL_CORE4G_M_SMB: 131 case PCI_PRODUCT_INTEL_CORE5G_M_SMB: 132 case PCI_PRODUCT_INTEL_CMTLK_SMB: 133 case PCI_PRODUCT_INTEL_BAYTRAIL_PCU_SMB: 134 case PCI_PRODUCT_INTEL_BSW_PCU_SMB: 135 case PCI_PRODUCT_INTEL_APL_SMB: 136 case PCI_PRODUCT_INTEL_GLK_SMB: 137 case PCI_PRODUCT_INTEL_C600_SMBUS: 138 case PCI_PRODUCT_INTEL_C600_SMB_0: 139 case PCI_PRODUCT_INTEL_C600_SMB_1: 140 case PCI_PRODUCT_INTEL_C600_SMB_2: 141 case PCI_PRODUCT_INTEL_C610_SMB: 142 case PCI_PRODUCT_INTEL_C620_SMB: 143 case PCI_PRODUCT_INTEL_C620_SMB_S: 144 case PCI_PRODUCT_INTEL_EP80579_SMB: 145 case PCI_PRODUCT_INTEL_DH89XXCC_SMB: 146 case PCI_PRODUCT_INTEL_DH89XXCL_SMB: 147 case PCI_PRODUCT_INTEL_C2000_PCU_SMBUS: 148 case PCI_PRODUCT_INTEL_C3K_SMBUS_LEGACY: 149 return 1; 150 } 151 } 152 return 0; 153 } 154 155 static void 156 ichsmb_attach(device_t parent, device_t self, void *aux) 157 { 158 struct ichsmb_softc *sc = device_private(self); 159 struct pci_attach_args *pa = aux; 160 pcireg_t conf; 161 const char *intrstr = NULL; 162 char intrbuf[PCI_INTRSTR_LEN]; 163 int flags; 164 165 sc->sc_dev = self; 166 sc->sc_pc = pa->pa_pc; 167 168 pci_aprint_devinfo(pa, NULL); 169 170 mutex_init(&sc->sc_exec_lock, MUTEX_DEFAULT, IPL_BIO); 171 cv_init(&sc->sc_exec_wait, device_xname(self)); 172 173 /* Read configuration */ 174 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 175 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 176 177 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 178 aprint_error_dev(self, "SMBus disabled\n"); 179 goto out; 180 } 181 182 /* Map I/O space */ 183 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 184 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_size)) { 185 aprint_error_dev(self, "can't map I/O space\n"); 186 goto out; 187 } 188 189 sc->sc_poll = 1; 190 sc->sc_ih = NULL; 191 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 192 /* No PCI IRQ */ 193 aprint_normal_dev(self, "interrupting at SMI\n"); 194 } else { 195 /* Install interrupt handler */ 196 if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0) == 0) { 197 intrstr = pci_intr_string(pa->pa_pc, sc->sc_pihp[0], 198 intrbuf, sizeof(intrbuf)); 199 pci_intr_setattr(pa->pa_pc, &sc->sc_pihp[0], 200 PCI_INTR_MPSAFE, true); 201 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, 202 sc->sc_pihp[0], IPL_BIO, ichsmb_intr, sc, 203 device_xname(sc->sc_dev)); 204 if (sc->sc_ih != NULL) { 205 aprint_normal_dev(self, "interrupting at %s\n", 206 intrstr); 207 sc->sc_poll = 0; 208 } else { 209 pci_intr_release(pa->pa_pc, sc->sc_pihp, 1); 210 sc->sc_pihp = NULL; 211 } 212 } 213 if (sc->sc_poll) 214 aprint_normal_dev(self, "polling\n"); 215 } 216 217 sc->sc_i2c_device = NULL; 218 flags = 0; 219 ichsmb_rescan(self, "i2cbus", &flags); 220 221 out: if (!pmf_device_register(self, NULL, NULL)) 222 aprint_error_dev(self, "couldn't establish power handler\n"); 223 } 224 225 static int 226 ichsmb_rescan(device_t self, const char *ifattr, const int *flags) 227 { 228 struct ichsmb_softc *sc = device_private(self); 229 struct i2cbus_attach_args iba; 230 231 if (!ifattr_match(ifattr, "i2cbus")) 232 return 0; 233 234 if (sc->sc_i2c_device) 235 return 0; 236 237 /* Attach I2C bus */ 238 iic_tag_init(&sc->sc_i2c_tag); 239 sc->sc_i2c_tag.ic_cookie = sc; 240 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 241 242 memset(&iba, 0, sizeof(iba)); 243 iba.iba_tag = &sc->sc_i2c_tag; 244 sc->sc_i2c_device = config_found_ia(self, ifattr, &iba, iicbus_print); 245 246 return 0; 247 } 248 249 static int 250 ichsmb_detach(device_t self, int flags) 251 { 252 struct ichsmb_softc *sc = device_private(self); 253 int error; 254 255 if (sc->sc_i2c_device) { 256 error = config_detach(sc->sc_i2c_device, flags); 257 if (error) 258 return error; 259 } 260 261 iic_tag_fini(&sc->sc_i2c_tag); 262 263 if (sc->sc_ih) { 264 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 265 sc->sc_ih = NULL; 266 } 267 268 if (sc->sc_pihp) { 269 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 270 sc->sc_pihp = NULL; 271 } 272 273 if (sc->sc_size != 0) 274 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_size); 275 276 mutex_destroy(&sc->sc_exec_lock); 277 cv_destroy(&sc->sc_exec_wait); 278 279 return 0; 280 } 281 282 static void 283 ichsmb_chdet(device_t self, device_t child) 284 { 285 struct ichsmb_softc *sc = device_private(self); 286 287 if (sc->sc_i2c_device == child) 288 sc->sc_i2c_device = NULL; 289 } 290 291 static int 292 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 293 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 294 { 295 struct ichsmb_softc *sc = cookie; 296 const uint8_t *b; 297 uint8_t ctl = 0, st; 298 int retries; 299 char fbuf[64]; 300 301 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 302 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 303 len, flags)); 304 305 mutex_enter(&sc->sc_exec_lock); 306 307 /* Clear status bits */ 308 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 309 LPCIB_SMB_HS_INTR | LPCIB_SMB_HS_DEVERR | 310 LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED); 311 bus_space_barrier(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 1, 312 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 313 314 /* Wait for bus to be idle */ 315 for (retries = 100; retries > 0; retries--) { 316 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 317 if (!(st & LPCIB_SMB_HS_BUSY)) 318 break; 319 DELAY(ICHIIC_DELAY); 320 } 321 #ifdef ICHIIC_DEBUG 322 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 323 printf("%s: exec: st %s\n", device_xname(sc->sc_dev), fbuf); 324 #endif 325 if (st & LPCIB_SMB_HS_BUSY) { 326 mutex_exit(&sc->sc_exec_lock); 327 return (EBUSY); 328 } 329 330 if (sc->sc_poll) 331 flags |= I2C_F_POLL; 332 333 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 334 (cmdlen == 0 && len > 1)) { 335 mutex_exit(&sc->sc_exec_lock); 336 return (EINVAL); 337 } 338 339 /* Setup transfer */ 340 sc->sc_i2c_xfer.op = op; 341 sc->sc_i2c_xfer.buf = buf; 342 sc->sc_i2c_xfer.len = len; 343 sc->sc_i2c_xfer.flags = flags; 344 sc->sc_i2c_xfer.error = 0; 345 sc->sc_i2c_xfer.done = false; 346 347 /* Set slave address and transfer direction */ 348 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 349 LPCIB_SMB_TXSLVA_ADDR(addr) | 350 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 351 352 b = (const uint8_t *)cmdbuf; 353 if (cmdlen > 0) 354 /* Set command byte */ 355 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 356 357 if (I2C_OP_WRITE_P(op)) { 358 /* Write data */ 359 b = buf; 360 if (cmdlen == 0 && len == 1) 361 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 362 LPCIB_SMB_HCMD, b[0]); 363 else if (len > 0) 364 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 365 LPCIB_SMB_HD0, b[0]); 366 if (len > 1) 367 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 368 LPCIB_SMB_HD1, b[1]); 369 } 370 371 /* Set SMBus command */ 372 if (cmdlen == 0) { 373 if (len == 0) 374 ctl = LPCIB_SMB_HC_CMD_QUICK; 375 else 376 ctl = LPCIB_SMB_HC_CMD_BYTE; 377 } else if (len == 1) 378 ctl = LPCIB_SMB_HC_CMD_BDATA; 379 else if (len == 2) 380 ctl = LPCIB_SMB_HC_CMD_WDATA; 381 382 if ((flags & I2C_F_POLL) == 0) 383 ctl |= LPCIB_SMB_HC_INTREN; 384 385 /* Start transaction */ 386 ctl |= LPCIB_SMB_HC_START; 387 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 388 389 if (flags & I2C_F_POLL) { 390 /* Poll for completion */ 391 DELAY(ICHIIC_DELAY); 392 for (retries = 1000; retries > 0; retries--) { 393 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 394 LPCIB_SMB_HS); 395 if ((st & LPCIB_SMB_HS_BUSY) == 0) 396 break; 397 DELAY(ICHIIC_DELAY); 398 } 399 if (st & LPCIB_SMB_HS_BUSY) 400 goto timeout; 401 ichsmb_intr(sc); 402 } else { 403 /* Wait for interrupt */ 404 while (! sc->sc_i2c_xfer.done) { 405 if (cv_timedwait(&sc->sc_exec_wait, &sc->sc_exec_lock, 406 ICHIIC_TIMEOUT * hz)) 407 goto timeout; 408 } 409 } 410 411 int error = sc->sc_i2c_xfer.error; 412 mutex_exit(&sc->sc_exec_lock); 413 414 return (error); 415 416 timeout: 417 /* 418 * Transfer timeout. Kill the transaction and clear status bits. 419 */ 420 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 421 aprint_error_dev(sc->sc_dev, 422 "exec: op %d, addr 0x%02x, cmdlen %zd, len %zd, " 423 "flags 0x%02x: timeout, status %s\n", 424 op, addr, cmdlen, len, flags, fbuf); 425 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 426 LPCIB_SMB_HC_KILL); 427 DELAY(ICHIIC_DELAY); 428 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 429 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 430 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 431 aprint_error_dev(sc->sc_dev, "abort failed, status %s\n", 432 fbuf); 433 } 434 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 435 mutex_exit(&sc->sc_exec_lock); 436 return (ETIMEDOUT); 437 } 438 439 static int 440 ichsmb_intr(void *arg) 441 { 442 struct ichsmb_softc *sc = arg; 443 uint8_t st; 444 uint8_t *b; 445 size_t len; 446 #ifdef ICHIIC_DEBUG 447 char fbuf[64]; 448 #endif 449 450 /* Read status */ 451 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 452 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 453 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 454 LPCIB_SMB_HS_SMBAL | LPCIB_SMB_HS_BDONE)) == 0) 455 /* Interrupt was not for us */ 456 return (0); 457 458 #ifdef ICHIIC_DEBUG 459 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 460 printf("%s: intr st %s\n", device_xname(sc->sc_dev), fbuf); 461 #endif 462 463 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 464 mutex_enter(&sc->sc_exec_lock); 465 466 /* Clear status bits */ 467 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 468 469 /* Check for errors */ 470 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 471 sc->sc_i2c_xfer.error = EIO; 472 goto done; 473 } 474 475 if (st & LPCIB_SMB_HS_INTR) { 476 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 477 goto done; 478 479 /* Read data */ 480 b = sc->sc_i2c_xfer.buf; 481 len = sc->sc_i2c_xfer.len; 482 if (len > 0) 483 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 484 LPCIB_SMB_HD0); 485 if (len > 1) 486 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 487 LPCIB_SMB_HD1); 488 } 489 490 done: 491 sc->sc_i2c_xfer.done = true; 492 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) { 493 cv_signal(&sc->sc_exec_wait); 494 mutex_exit(&sc->sc_exec_lock); 495 } 496 return (1); 497 } 498 499 MODULE(MODULE_CLASS_DRIVER, ichsmb, "pci,iic"); 500 501 #ifdef _MODULE 502 #include "ioconf.c" 503 #endif 504 505 static int 506 ichsmb_modcmd(modcmd_t cmd, void *opaque) 507 { 508 int error = 0; 509 510 switch (cmd) { 511 case MODULE_CMD_INIT: 512 #ifdef _MODULE 513 error = config_init_component(cfdriver_ioconf_ichsmb, 514 cfattach_ioconf_ichsmb, cfdata_ioconf_ichsmb); 515 #endif 516 break; 517 case MODULE_CMD_FINI: 518 #ifdef _MODULE 519 error = config_fini_component(cfdriver_ioconf_ichsmb, 520 cfattach_ioconf_ichsmb, cfdata_ioconf_ichsmb); 521 #endif 522 break; 523 default: 524 #ifdef _MODULE 525 error = ENOTTY; 526 #endif 527 break; 528 } 529 530 return error; 531 } 532
Indexes created Thu Oct 02 14:10:14 GMT 2025