ichsmb.c revision 1.60.4.4
1 /* $NetBSD: ichsmb.c,v 1.60.4.4 2022/10/15 10:29:40 martin Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.44 2020/10/07 11:23:05 jsg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.60.4.4 2022/10/15 10:29:40 martin Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 #include <sys/module.h> 34 35 #include <sys/bus.h> 36 37 #include <dev/pci/pcidevs.h> 38 #include <dev/pci/pcireg.h> 39 #include <dev/pci/pcivar.h> 40 41 #include <dev/ic/i82801lpcreg.h> 42 43 #include <dev/i2c/i2cvar.h> 44 45 #ifdef ICHIIC_DEBUG 46 #define DPRINTF(x) printf x 47 #else 48 #define DPRINTF(x) 49 #endif 50 51 #define ICHIIC_DELAY 100 52 #define ICHIIC_TIMEOUT 1 53 54 struct ichsmb_softc { 55 device_t sc_dev; 56 57 bus_space_tag_t sc_iot; 58 bus_space_handle_t sc_ioh; 59 bus_size_t sc_size; 60 pci_chipset_tag_t sc_pc; 61 void * sc_ih; 62 int sc_poll; 63 pci_intr_handle_t *sc_pihp; 64 65 struct i2c_controller sc_i2c_tag; 66 kmutex_t sc_i2c_mutex; 67 struct { 68 i2c_op_t op; 69 void * buf; 70 size_t len; 71 int flags; 72 volatile int error; 73 } sc_i2c_xfer; 74 device_t sc_i2c_device; 75 }; 76 77 static int ichsmb_match(device_t, cfdata_t, void *); 78 static void ichsmb_attach(device_t, device_t, void *); 79 static int ichsmb_detach(device_t, int); 80 static int ichsmb_rescan(device_t, const char *, const int *); 81 static void ichsmb_chdet(device_t, device_t); 82 83 static int ichsmb_i2c_acquire_bus(void *, int); 84 static void ichsmb_i2c_release_bus(void *, int); 85 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 86 size_t, void *, size_t, int); 87 88 static int ichsmb_intr(void *); 89 90 #include "ioconf.h" 91 92 CFATTACH_DECL3_NEW(ichsmb, sizeof(struct ichsmb_softc), 93 ichsmb_match, ichsmb_attach, ichsmb_detach, NULL, ichsmb_rescan, 94 ichsmb_chdet, DVF_DETACH_SHUTDOWN); 95 96 97 static int 98 ichsmb_match(device_t parent, cfdata_t match, void *aux) 99 { 100 struct pci_attach_args *pa = aux; 101 102 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 103 switch (PCI_PRODUCT(pa->pa_id)) { 104 case PCI_PRODUCT_INTEL_6300ESB_SMB: 105 case PCI_PRODUCT_INTEL_63XXESB_SMB: 106 case PCI_PRODUCT_INTEL_82801AA_SMB: 107 case PCI_PRODUCT_INTEL_82801AB_SMB: 108 case PCI_PRODUCT_INTEL_82801BA_SMB: 109 case PCI_PRODUCT_INTEL_82801CA_SMB: 110 case PCI_PRODUCT_INTEL_82801DB_SMB: 111 case PCI_PRODUCT_INTEL_82801E_SMB: 112 case PCI_PRODUCT_INTEL_82801EB_SMB: 113 case PCI_PRODUCT_INTEL_82801FB_SMB: 114 case PCI_PRODUCT_INTEL_82801G_SMB: 115 case PCI_PRODUCT_INTEL_82801H_SMB: 116 case PCI_PRODUCT_INTEL_82801I_SMB: 117 case PCI_PRODUCT_INTEL_82801JD_SMB: 118 case PCI_PRODUCT_INTEL_82801JI_SMB: 119 case PCI_PRODUCT_INTEL_3400_SMB: 120 case PCI_PRODUCT_INTEL_6SERIES_SMB: 121 case PCI_PRODUCT_INTEL_7SERIES_SMB: 122 case PCI_PRODUCT_INTEL_8SERIES_SMB: 123 case PCI_PRODUCT_INTEL_9SERIES_SMB: 124 case PCI_PRODUCT_INTEL_100SERIES_SMB: 125 case PCI_PRODUCT_INTEL_100SERIES_LP_SMB: 126 case PCI_PRODUCT_INTEL_2HS_SMB: 127 case PCI_PRODUCT_INTEL_3HS_SMB: 128 case PCI_PRODUCT_INTEL_3HS_U_SMB: 129 case PCI_PRODUCT_INTEL_4HS_H_SMB: 130 case PCI_PRODUCT_INTEL_4HS_V_SMB: 131 case PCI_PRODUCT_INTEL_CORE4G_M_SMB: 132 case PCI_PRODUCT_INTEL_CORE5G_M_SMB: 133 case PCI_PRODUCT_INTEL_CMTLK_SMB: 134 case PCI_PRODUCT_INTEL_BAYTRAIL_PCU_SMB: 135 case PCI_PRODUCT_INTEL_BSW_PCU_SMB: 136 case PCI_PRODUCT_INTEL_APL_SMB: 137 case PCI_PRODUCT_INTEL_GLK_SMB: 138 case PCI_PRODUCT_INTEL_EHL_SMB: 139 case PCI_PRODUCT_INTEL_JSL_SMB: 140 case PCI_PRODUCT_INTEL_C600_SMBUS: 141 case PCI_PRODUCT_INTEL_C600_SMB_0: 142 case PCI_PRODUCT_INTEL_C600_SMB_1: 143 case PCI_PRODUCT_INTEL_C600_SMB_2: 144 case PCI_PRODUCT_INTEL_C610_SMB: 145 case PCI_PRODUCT_INTEL_C620_SMB: 146 case PCI_PRODUCT_INTEL_C620_SMB_S: 147 case PCI_PRODUCT_INTEL_EP80579_SMB: 148 case PCI_PRODUCT_INTEL_DH89XXCC_SMB: 149 case PCI_PRODUCT_INTEL_DH89XXCL_SMB: 150 case PCI_PRODUCT_INTEL_C2000_PCU_SMBUS: 151 case PCI_PRODUCT_INTEL_C3K_SMBUS_LEGACY: 152 case PCI_PRODUCT_INTEL_495_YU_SMB: 153 case PCI_PRODUCT_INTEL_5HS_H_SMB: 154 case PCI_PRODUCT_INTEL_5HS_LP_SMB: 155 case PCI_PRODUCT_INTEL_6HS_H_SMB: 156 case PCI_PRODUCT_INTEL_6HS_LP_SMB: 157 return 1; 158 } 159 } 160 return 0; 161 } 162 163 static void 164 ichsmb_attach(device_t parent, device_t self, void *aux) 165 { 166 struct ichsmb_softc *sc = device_private(self); 167 struct pci_attach_args *pa = aux; 168 pcireg_t conf; 169 const char *intrstr = NULL; 170 char intrbuf[PCI_INTRSTR_LEN]; 171 int flags; 172 173 sc->sc_dev = self; 174 sc->sc_pc = pa->pa_pc; 175 176 pci_aprint_devinfo(pa, NULL); 177 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 178 179 /* Read configuration */ 180 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 181 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 182 183 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 184 aprint_error_dev(self, "SMBus disabled\n"); 185 goto out; 186 } 187 188 /* Map I/O space */ 189 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 190 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_size)) { 191 aprint_error_dev(self, "can't map I/O space\n"); 192 goto out; 193 } 194 195 sc->sc_poll = 1; 196 sc->sc_ih = NULL; 197 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 198 /* No PCI IRQ */ 199 aprint_normal_dev(self, "interrupting at SMI\n"); 200 } else { 201 /* Install interrupt handler */ 202 if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0) == 0) { 203 intrstr = pci_intr_string(pa->pa_pc, sc->sc_pihp[0], 204 intrbuf, sizeof(intrbuf)); 205 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, 206 sc->sc_pihp[0], IPL_BIO, ichsmb_intr, sc, 207 device_xname(sc->sc_dev)); 208 if (sc->sc_ih != NULL) { 209 aprint_normal_dev(self, "interrupting at %s\n", 210 intrstr); 211 sc->sc_poll = 0; 212 } else { 213 pci_intr_release(pa->pa_pc, sc->sc_pihp, 1); 214 sc->sc_pihp = NULL; 215 } 216 } 217 if (sc->sc_poll) 218 aprint_normal_dev(self, "polling\n"); 219 } 220 221 sc->sc_i2c_device = NULL; 222 flags = 0; 223 ichsmb_rescan(self, "i2cbus", &flags); 224 225 out: if (!pmf_device_register(self, NULL, NULL)) 226 aprint_error_dev(self, "couldn't establish power handler\n"); 227 } 228 229 static int 230 ichsmb_rescan(device_t self, const char *ifattr, const int *flags) 231 { 232 struct ichsmb_softc *sc = device_private(self); 233 struct i2cbus_attach_args iba; 234 235 if (!ifattr_match(ifattr, "i2cbus")) 236 return 0; 237 238 if (sc->sc_i2c_device) 239 return 0; 240 241 /* Attach I2C bus */ 242 sc->sc_i2c_tag.ic_cookie = sc; 243 sc->sc_i2c_tag.ic_acquire_bus = ichsmb_i2c_acquire_bus; 244 sc->sc_i2c_tag.ic_release_bus = ichsmb_i2c_release_bus; 245 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 246 247 memset(&iba, 0, sizeof(iba)); 248 iba.iba_type = I2C_TYPE_SMBUS; 249 iba.iba_tag = &sc->sc_i2c_tag; 250 sc->sc_i2c_device = config_found_ia(self, ifattr, &iba, iicbus_print); 251 252 return 0; 253 } 254 255 static int 256 ichsmb_detach(device_t self, int flags) 257 { 258 struct ichsmb_softc *sc = device_private(self); 259 int error; 260 261 if (sc->sc_i2c_device) { 262 error = config_detach(sc->sc_i2c_device, flags); 263 if (error) 264 return error; 265 } 266 267 mutex_destroy(&sc->sc_i2c_mutex); 268 269 if (sc->sc_ih) { 270 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 271 sc->sc_ih = NULL; 272 } 273 274 if (sc->sc_pihp) { 275 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 276 sc->sc_pihp = NULL; 277 } 278 279 if (sc->sc_size != 0) 280 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_size); 281 282 return 0; 283 } 284 285 static void 286 ichsmb_chdet(device_t self, device_t child) 287 { 288 struct ichsmb_softc *sc = device_private(self); 289 290 if (sc->sc_i2c_device == child) 291 sc->sc_i2c_device = NULL; 292 } 293 294 static int 295 ichsmb_i2c_acquire_bus(void *cookie, int flags) 296 { 297 struct ichsmb_softc *sc = cookie; 298 299 if (cold) 300 return 0; 301 302 mutex_enter(&sc->sc_i2c_mutex); 303 return 0; 304 } 305 306 static void 307 ichsmb_i2c_release_bus(void *cookie, int flags) 308 { 309 struct ichsmb_softc *sc = cookie; 310 311 if (cold) 312 return; 313 314 mutex_exit(&sc->sc_i2c_mutex); 315 } 316 317 static int 318 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 319 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 320 { 321 struct ichsmb_softc *sc = cookie; 322 const uint8_t *b; 323 uint8_t ctl = 0, st; 324 int retries; 325 char fbuf[64]; 326 327 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 328 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 329 len, flags)); 330 331 /* Clear status bits */ 332 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 333 LPCIB_SMB_HS_INTR | LPCIB_SMB_HS_DEVERR | 334 LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED); 335 bus_space_barrier(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 1, 336 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 337 338 /* Wait for bus to be idle */ 339 for (retries = 100; retries > 0; retries--) { 340 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 341 if (!(st & LPCIB_SMB_HS_BUSY)) 342 break; 343 DELAY(ICHIIC_DELAY); 344 } 345 #ifdef ICHIIC_DEBUG 346 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 347 printf("%s: exec: st %s\n", device_xname(sc->sc_dev), fbuf); 348 #endif 349 if (st & LPCIB_SMB_HS_BUSY) 350 return (1); 351 352 if (cold || sc->sc_poll) 353 flags |= I2C_F_POLL; 354 355 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 356 (cmdlen == 0 && len > 1)) 357 return (1); 358 359 /* Setup transfer */ 360 sc->sc_i2c_xfer.op = op; 361 sc->sc_i2c_xfer.buf = buf; 362 sc->sc_i2c_xfer.len = len; 363 sc->sc_i2c_xfer.flags = flags; 364 sc->sc_i2c_xfer.error = 0; 365 366 /* Set slave address and transfer direction */ 367 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 368 LPCIB_SMB_TXSLVA_ADDR(addr) | 369 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 370 371 b = (const uint8_t *)cmdbuf; 372 if (cmdlen > 0) 373 /* Set command byte */ 374 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 375 376 if (I2C_OP_WRITE_P(op)) { 377 /* Write data */ 378 b = buf; 379 if (cmdlen == 0 && len == 1) 380 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 381 LPCIB_SMB_HCMD, b[0]); 382 else if (len > 0) 383 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 384 LPCIB_SMB_HD0, b[0]); 385 if (len > 1) 386 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 387 LPCIB_SMB_HD1, b[1]); 388 } 389 390 /* Set SMBus command */ 391 if (cmdlen == 0) { 392 if (len == 0) 393 ctl = LPCIB_SMB_HC_CMD_QUICK; 394 else 395 ctl = LPCIB_SMB_HC_CMD_BYTE; 396 } else if (len == 1) 397 ctl = LPCIB_SMB_HC_CMD_BDATA; 398 else if (len == 2) 399 ctl = LPCIB_SMB_HC_CMD_WDATA; 400 401 if ((flags & I2C_F_POLL) == 0) 402 ctl |= LPCIB_SMB_HC_INTREN; 403 404 /* Start transaction */ 405 ctl |= LPCIB_SMB_HC_START; 406 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 407 408 if (flags & I2C_F_POLL) { 409 /* Poll for completion */ 410 DELAY(ICHIIC_DELAY); 411 for (retries = 1000; retries > 0; retries--) { 412 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 413 LPCIB_SMB_HS); 414 if ((st & LPCIB_SMB_HS_BUSY) == 0) 415 break; 416 DELAY(ICHIIC_DELAY); 417 } 418 if (st & LPCIB_SMB_HS_BUSY) 419 goto timeout; 420 ichsmb_intr(sc); 421 } else { 422 /* Wait for interrupt */ 423 if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz)) 424 goto timeout; 425 } 426 427 if (sc->sc_i2c_xfer.error) 428 return (1); 429 430 return (0); 431 432 timeout: 433 /* 434 * Transfer timeout. Kill the transaction and clear status bits. 435 */ 436 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 437 LPCIB_SMB_HC_KILL); 438 DELAY(ICHIIC_DELAY); 439 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 440 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 441 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 442 aprint_error_dev(sc->sc_dev, "abort failed, status %s\n", 443 fbuf); 444 } 445 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 446 return (1); 447 } 448 449 static int 450 ichsmb_intr(void *arg) 451 { 452 struct ichsmb_softc *sc = arg; 453 uint8_t st; 454 uint8_t *b; 455 size_t len; 456 #ifdef ICHIIC_DEBUG 457 char fbuf[64]; 458 #endif 459 460 /* Read status */ 461 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 462 463 /* Clear status bits */ 464 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 465 466 /* XXX Ignore SMBALERT# for now */ 467 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 468 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 469 LPCIB_SMB_HS_BDONE)) == 0) 470 /* Interrupt was not for us */ 471 return (0); 472 473 #ifdef ICHIIC_DEBUG 474 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 475 printf("%s: intr st %s\n", device_xname(sc->sc_dev), fbuf); 476 #endif 477 478 /* Check for errors */ 479 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 480 sc->sc_i2c_xfer.error = 1; 481 goto done; 482 } 483 484 if (st & LPCIB_SMB_HS_INTR) { 485 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 486 goto done; 487 488 /* Read data */ 489 b = sc->sc_i2c_xfer.buf; 490 len = sc->sc_i2c_xfer.len; 491 if (len > 0) 492 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 493 LPCIB_SMB_HD0); 494 if (len > 1) 495 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 496 LPCIB_SMB_HD1); 497 } 498 499 done: 500 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 501 wakeup(sc); 502 return (1); 503 } 504 505 MODULE(MODULE_CLASS_DRIVER, ichsmb, "pci,iic"); 506 507 #ifdef _MODULE 508 #include "ioconf.c" 509 #endif 510 511 static int 512 ichsmb_modcmd(modcmd_t cmd, void *opaque) 513 { 514 int error = 0; 515 516 switch (cmd) { 517 case MODULE_CMD_INIT: 518 #ifdef _MODULE 519 error = config_init_component(cfdriver_ioconf_ichsmb, 520 cfattach_ioconf_ichsmb, cfdata_ioconf_ichsmb); 521 #endif 522 break; 523 case MODULE_CMD_FINI: 524 #ifdef _MODULE 525 error = config_fini_component(cfdriver_ioconf_ichsmb, 526 cfattach_ioconf_ichsmb, cfdata_ioconf_ichsmb); 527 #endif 528 break; 529 default: 530 #ifdef _MODULE 531 error = ENOTTY; 532 #endif 533 break; 534 } 535 536 return error; 537 } 538
Indexes created Thu Oct 02 14:10:14 GMT 2025