ichsmb.c revision 1.64
1 /* $NetBSD: ichsmb.c,v 1.64 2019/12/23 15:34:40 thorpej Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.18 2007/05/03 09:36:26 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.64 2019/12/23 15:34:40 thorpej Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 #include <sys/module.h> 34 35 #include <sys/bus.h> 36 37 #include <dev/pci/pcidevs.h> 38 #include <dev/pci/pcireg.h> 39 #include <dev/pci/pcivar.h> 40 41 #include <dev/ic/i82801lpcreg.h> 42 43 #include <dev/i2c/i2cvar.h> 44 45 #ifdef ICHIIC_DEBUG 46 #define DPRINTF(x) printf x 47 #else 48 #define DPRINTF(x) 49 #endif 50 51 #define ICHIIC_DELAY 100 52 #define ICHIIC_TIMEOUT 1 53 54 struct ichsmb_softc { 55 device_t sc_dev; 56 57 bus_space_tag_t sc_iot; 58 bus_space_handle_t sc_ioh; 59 bus_size_t sc_size; 60 pci_chipset_tag_t sc_pc; 61 void * sc_ih; 62 int sc_poll; 63 pci_intr_handle_t *sc_pihp; 64 65 struct i2c_controller sc_i2c_tag; 66 struct { 67 i2c_op_t op; 68 void * buf; 69 size_t len; 70 int flags; 71 volatile int error; 72 } sc_i2c_xfer; 73 device_t sc_i2c_device; 74 }; 75 76 static int ichsmb_match(device_t, cfdata_t, void *); 77 static void ichsmb_attach(device_t, device_t, void *); 78 static int ichsmb_detach(device_t, int); 79 static int ichsmb_rescan(device_t, const char *, const int *); 80 static void ichsmb_chdet(device_t, device_t); 81 82 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 83 size_t, void *, size_t, int); 84 85 static int ichsmb_intr(void *); 86 87 #include "ioconf.h" 88 89 CFATTACH_DECL3_NEW(ichsmb, sizeof(struct ichsmb_softc), 90 ichsmb_match, ichsmb_attach, ichsmb_detach, NULL, ichsmb_rescan, 91 ichsmb_chdet, DVF_DETACH_SHUTDOWN); 92 93 94 static int 95 ichsmb_match(device_t parent, cfdata_t match, void *aux) 96 { 97 struct pci_attach_args *pa = aux; 98 99 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 100 switch (PCI_PRODUCT(pa->pa_id)) { 101 case PCI_PRODUCT_INTEL_6300ESB_SMB: 102 case PCI_PRODUCT_INTEL_63XXESB_SMB: 103 case PCI_PRODUCT_INTEL_82801AA_SMB: 104 case PCI_PRODUCT_INTEL_82801AB_SMB: 105 case PCI_PRODUCT_INTEL_82801BA_SMB: 106 case PCI_PRODUCT_INTEL_82801CA_SMB: 107 case PCI_PRODUCT_INTEL_82801DB_SMB: 108 case PCI_PRODUCT_INTEL_82801E_SMB: 109 case PCI_PRODUCT_INTEL_82801EB_SMB: 110 case PCI_PRODUCT_INTEL_82801FB_SMB: 111 case PCI_PRODUCT_INTEL_82801G_SMB: 112 case PCI_PRODUCT_INTEL_82801H_SMB: 113 case PCI_PRODUCT_INTEL_82801I_SMB: 114 case PCI_PRODUCT_INTEL_82801JD_SMB: 115 case PCI_PRODUCT_INTEL_82801JI_SMB: 116 case PCI_PRODUCT_INTEL_3400_SMB: 117 case PCI_PRODUCT_INTEL_6SERIES_SMB: 118 case PCI_PRODUCT_INTEL_7SERIES_SMB: 119 case PCI_PRODUCT_INTEL_8SERIES_SMB: 120 case PCI_PRODUCT_INTEL_9SERIES_SMB: 121 case PCI_PRODUCT_INTEL_100SERIES_SMB: 122 case PCI_PRODUCT_INTEL_100SERIES_LP_SMB: 123 case PCI_PRODUCT_INTEL_2HS_SMB: 124 case PCI_PRODUCT_INTEL_3HS_SMB: 125 case PCI_PRODUCT_INTEL_CORE4G_M_SMB: 126 case PCI_PRODUCT_INTEL_CORE5G_M_SMB: 127 case PCI_PRODUCT_INTEL_BAYTRAIL_PCU_SMB: 128 case PCI_PRODUCT_INTEL_BSW_PCU_SMB: 129 case PCI_PRODUCT_INTEL_APL_SMB: 130 case PCI_PRODUCT_INTEL_GLK_SMB: 131 case PCI_PRODUCT_INTEL_C600_SMBUS: 132 case PCI_PRODUCT_INTEL_C600_SMB_0: 133 case PCI_PRODUCT_INTEL_C600_SMB_1: 134 case PCI_PRODUCT_INTEL_C600_SMB_2: 135 case PCI_PRODUCT_INTEL_C610_SMB: 136 case PCI_PRODUCT_INTEL_C620_SMB: 137 case PCI_PRODUCT_INTEL_C620_SMB_S: 138 case PCI_PRODUCT_INTEL_EP80579_SMB: 139 case PCI_PRODUCT_INTEL_DH89XXCC_SMB: 140 case PCI_PRODUCT_INTEL_DH89XXCL_SMB: 141 case PCI_PRODUCT_INTEL_C2000_PCU_SMBUS: 142 case PCI_PRODUCT_INTEL_C3K_SMBUS_LEGACY: 143 return 1; 144 } 145 } 146 return 0; 147 } 148 149 static void 150 ichsmb_attach(device_t parent, device_t self, void *aux) 151 { 152 struct ichsmb_softc *sc = device_private(self); 153 struct pci_attach_args *pa = aux; 154 pcireg_t conf; 155 const char *intrstr = NULL; 156 char intrbuf[PCI_INTRSTR_LEN]; 157 int flags; 158 159 sc->sc_dev = self; 160 sc->sc_pc = pa->pa_pc; 161 162 pci_aprint_devinfo(pa, NULL); 163 164 /* Read configuration */ 165 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 166 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 167 168 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 169 aprint_error_dev(self, "SMBus disabled\n"); 170 goto out; 171 } 172 173 /* Map I/O space */ 174 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 175 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_size)) { 176 aprint_error_dev(self, "can't map I/O space\n"); 177 goto out; 178 } 179 180 sc->sc_poll = 1; 181 sc->sc_ih = NULL; 182 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 183 /* No PCI IRQ */ 184 aprint_normal_dev(self, "interrupting at SMI\n"); 185 } else { 186 /* Install interrupt handler */ 187 if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0) == 0) { 188 intrstr = pci_intr_string(pa->pa_pc, sc->sc_pihp[0], 189 intrbuf, sizeof(intrbuf)); 190 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, 191 sc->sc_pihp[0], IPL_BIO, ichsmb_intr, sc, 192 device_xname(sc->sc_dev)); 193 if (sc->sc_ih != NULL) { 194 aprint_normal_dev(self, "interrupting at %s\n", 195 intrstr); 196 sc->sc_poll = 0; 197 } else { 198 pci_intr_release(pa->pa_pc, sc->sc_pihp, 1); 199 sc->sc_pihp = NULL; 200 } 201 } 202 if (sc->sc_poll) 203 aprint_normal_dev(self, "polling\n"); 204 } 205 206 sc->sc_i2c_device = NULL; 207 flags = 0; 208 ichsmb_rescan(self, "i2cbus", &flags); 209 210 out: if (!pmf_device_register(self, NULL, NULL)) 211 aprint_error_dev(self, "couldn't establish power handler\n"); 212 } 213 214 static int 215 ichsmb_rescan(device_t self, const char *ifattr, const int *flags) 216 { 217 struct ichsmb_softc *sc = device_private(self); 218 struct i2cbus_attach_args iba; 219 220 if (!ifattr_match(ifattr, "i2cbus")) 221 return 0; 222 223 if (sc->sc_i2c_device) 224 return 0; 225 226 /* Attach I2C bus */ 227 iic_tag_init(&sc->sc_i2c_tag); 228 sc->sc_i2c_tag.ic_cookie = sc; 229 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 230 231 memset(&iba, 0, sizeof(iba)); 232 iba.iba_tag = &sc->sc_i2c_tag; 233 sc->sc_i2c_device = config_found_ia(self, ifattr, &iba, iicbus_print); 234 235 return 0; 236 } 237 238 static int 239 ichsmb_detach(device_t self, int flags) 240 { 241 struct ichsmb_softc *sc = device_private(self); 242 int error; 243 244 if (sc->sc_i2c_device) { 245 error = config_detach(sc->sc_i2c_device, flags); 246 if (error) 247 return error; 248 } 249 250 iic_tag_fini(&sc->sc_i2c_tag); 251 252 if (sc->sc_ih) { 253 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 254 sc->sc_ih = NULL; 255 } 256 257 if (sc->sc_pihp) { 258 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 259 sc->sc_pihp = NULL; 260 } 261 262 if (sc->sc_size != 0) 263 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_size); 264 265 return 0; 266 } 267 268 static void 269 ichsmb_chdet(device_t self, device_t child) 270 { 271 struct ichsmb_softc *sc = device_private(self); 272 273 if (sc->sc_i2c_device == child) 274 sc->sc_i2c_device = NULL; 275 } 276 277 static int 278 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 279 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 280 { 281 struct ichsmb_softc *sc = cookie; 282 const uint8_t *b; 283 uint8_t ctl = 0, st; 284 int retries; 285 char fbuf[64]; 286 287 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 288 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 289 len, flags)); 290 291 /* Clear status bits */ 292 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 293 LPCIB_SMB_HS_INTR | LPCIB_SMB_HS_DEVERR | 294 LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED); 295 bus_space_barrier(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 1, 296 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 297 298 /* Wait for bus to be idle */ 299 for (retries = 100; retries > 0; retries--) { 300 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 301 if (!(st & LPCIB_SMB_HS_BUSY)) 302 break; 303 DELAY(ICHIIC_DELAY); 304 } 305 #ifdef ICHIIC_DEBUG 306 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 307 printf("%s: exec: st %s\n", device_xname(sc->sc_dev), fbuf); 308 #endif 309 if (st & LPCIB_SMB_HS_BUSY) 310 return (1); 311 312 if (sc->sc_poll) 313 flags |= I2C_F_POLL; 314 315 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 316 (cmdlen == 0 && len > 1)) 317 return (1); 318 319 /* Setup transfer */ 320 sc->sc_i2c_xfer.op = op; 321 sc->sc_i2c_xfer.buf = buf; 322 sc->sc_i2c_xfer.len = len; 323 sc->sc_i2c_xfer.flags = flags; 324 sc->sc_i2c_xfer.error = 0; 325 326 /* Set slave address and transfer direction */ 327 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 328 LPCIB_SMB_TXSLVA_ADDR(addr) | 329 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 330 331 b = (const uint8_t *)cmdbuf; 332 if (cmdlen > 0) 333 /* Set command byte */ 334 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 335 336 if (I2C_OP_WRITE_P(op)) { 337 /* Write data */ 338 b = buf; 339 if (cmdlen == 0 && len == 1) 340 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 341 LPCIB_SMB_HCMD, b[0]); 342 else if (len > 0) 343 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 344 LPCIB_SMB_HD0, b[0]); 345 if (len > 1) 346 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 347 LPCIB_SMB_HD1, b[1]); 348 } 349 350 /* Set SMBus command */ 351 if (cmdlen == 0) { 352 if (len == 0) 353 ctl = LPCIB_SMB_HC_CMD_QUICK; 354 else 355 ctl = LPCIB_SMB_HC_CMD_BYTE; 356 } else if (len == 1) 357 ctl = LPCIB_SMB_HC_CMD_BDATA; 358 else if (len == 2) 359 ctl = LPCIB_SMB_HC_CMD_WDATA; 360 361 if ((flags & I2C_F_POLL) == 0) 362 ctl |= LPCIB_SMB_HC_INTREN; 363 364 /* Start transaction */ 365 ctl |= LPCIB_SMB_HC_START; 366 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 367 368 if (flags & I2C_F_POLL) { 369 /* Poll for completion */ 370 DELAY(ICHIIC_DELAY); 371 for (retries = 1000; retries > 0; retries--) { 372 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 373 LPCIB_SMB_HS); 374 if ((st & LPCIB_SMB_HS_BUSY) == 0) 375 break; 376 DELAY(ICHIIC_DELAY); 377 } 378 if (st & LPCIB_SMB_HS_BUSY) 379 goto timeout; 380 ichsmb_intr(sc); 381 } else { 382 /* Wait for interrupt */ 383 if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz)) 384 goto timeout; 385 } 386 387 if (sc->sc_i2c_xfer.error) 388 return (1); 389 390 return (0); 391 392 timeout: 393 /* 394 * Transfer timeout. Kill the transaction and clear status bits. 395 */ 396 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 397 aprint_error_dev(sc->sc_dev, 398 "exec: op %d, addr 0x%02x, cmdlen %zd, len %zd, " 399 "flags 0x%02x: timeout, status %s\n", 400 op, addr, cmdlen, len, flags, fbuf); 401 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 402 LPCIB_SMB_HC_KILL); 403 DELAY(ICHIIC_DELAY); 404 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 405 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 406 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 407 aprint_error_dev(sc->sc_dev, "abort failed, status %s\n", 408 fbuf); 409 } 410 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 411 return (1); 412 } 413 414 static int 415 ichsmb_intr(void *arg) 416 { 417 struct ichsmb_softc *sc = arg; 418 uint8_t st; 419 uint8_t *b; 420 size_t len; 421 #ifdef ICHIIC_DEBUG 422 char fbuf[64]; 423 #endif 424 425 /* Read status */ 426 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 427 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 428 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 429 LPCIB_SMB_HS_SMBAL | LPCIB_SMB_HS_BDONE)) == 0) 430 /* Interrupt was not for us */ 431 return (0); 432 433 #ifdef ICHIIC_DEBUG 434 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 435 printf("%s: intr st %s\n", device_xname(sc->sc_dev), fbuf); 436 #endif 437 438 /* Clear status bits */ 439 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 440 441 /* Check for errors */ 442 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 443 sc->sc_i2c_xfer.error = 1; 444 goto done; 445 } 446 447 if (st & LPCIB_SMB_HS_INTR) { 448 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 449 goto done; 450 451 /* Read data */ 452 b = sc->sc_i2c_xfer.buf; 453 len = sc->sc_i2c_xfer.len; 454 if (len > 0) 455 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 456 LPCIB_SMB_HD0); 457 if (len > 1) 458 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 459 LPCIB_SMB_HD1); 460 } 461 462 done: 463 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 464 wakeup(sc); 465 return (1); 466 } 467 468 MODULE(MODULE_CLASS_DRIVER, ichsmb, "pci,iic"); 469 470 #ifdef _MODULE 471 #include "ioconf.c" 472 #endif 473 474 static int 475 ichsmb_modcmd(modcmd_t cmd, void *opaque) 476 { 477 int error = 0; 478 479 switch (cmd) { 480 case MODULE_CMD_INIT: 481 #ifdef _MODULE 482 error = config_init_component(cfdriver_ioconf_ichsmb, 483 cfattach_ioconf_ichsmb, cfdata_ioconf_ichsmb); 484 #endif 485 break; 486 case MODULE_CMD_FINI: 487 #ifdef _MODULE 488 error = config_fini_component(cfdriver_ioconf_ichsmb, 489 cfattach_ioconf_ichsmb, cfdata_ioconf_ichsmb); 490 #endif 491 break; 492 default: 493 #ifdef _MODULE 494 error = ENOTTY; 495 #endif 496 break; 497 } 498 499 return error; 500 } 501
Indexes created Thu Oct 02 14:10:14 GMT 2025