ichsmb.c revision 1.65.2.1
1 /* $NetBSD: ichsmb.c,v 1.65.2.1 2020/02/29 20:19:10 ad Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.18 2007/05/03 09:36:26 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.65.2.1 2020/02/29 20:19:10 ad Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/condvar.h> 33 #include <sys/proc.h> 34 #include <sys/module.h> 35 36 #include <sys/bus.h> 37 38 #include <dev/pci/pcidevs.h> 39 #include <dev/pci/pcireg.h> 40 #include <dev/pci/pcivar.h> 41 42 #include <dev/ic/i82801lpcreg.h> 43 44 #include <dev/i2c/i2cvar.h> 45 46 #ifdef ICHIIC_DEBUG 47 #define DPRINTF(x) printf x 48 #else 49 #define DPRINTF(x) 50 #endif 51 52 #define ICHIIC_DELAY 100 53 #define ICHIIC_TIMEOUT 1 54 55 struct ichsmb_softc { 56 device_t sc_dev; 57 58 bus_space_tag_t sc_iot; 59 bus_space_handle_t sc_ioh; 60 bus_size_t sc_size; 61 pci_chipset_tag_t sc_pc; 62 void * sc_ih; 63 int sc_poll; 64 pci_intr_handle_t *sc_pihp; 65 66 kmutex_t sc_exec_lock; 67 kcondvar_t sc_exec_wait; 68 69 struct i2c_controller sc_i2c_tag; 70 struct { 71 i2c_op_t op; 72 void * buf; 73 size_t len; 74 int flags; 75 int error; 76 bool done; 77 } sc_i2c_xfer; 78 device_t sc_i2c_device; 79 }; 80 81 static int ichsmb_match(device_t, cfdata_t, void *); 82 static void ichsmb_attach(device_t, device_t, void *); 83 static int ichsmb_detach(device_t, int); 84 static int ichsmb_rescan(device_t, const char *, const int *); 85 static void ichsmb_chdet(device_t, device_t); 86 87 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 88 size_t, void *, size_t, int); 89 90 static int ichsmb_intr(void *); 91 92 #include "ioconf.h" 93 94 CFATTACH_DECL3_NEW(ichsmb, sizeof(struct ichsmb_softc), 95 ichsmb_match, ichsmb_attach, ichsmb_detach, NULL, ichsmb_rescan, 96 ichsmb_chdet, DVF_DETACH_SHUTDOWN); 97 98 99 static int 100 ichsmb_match(device_t parent, cfdata_t match, void *aux) 101 { 102 struct pci_attach_args *pa = aux; 103 104 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 105 switch (PCI_PRODUCT(pa->pa_id)) { 106 case PCI_PRODUCT_INTEL_6300ESB_SMB: 107 case PCI_PRODUCT_INTEL_63XXESB_SMB: 108 case PCI_PRODUCT_INTEL_82801AA_SMB: 109 case PCI_PRODUCT_INTEL_82801AB_SMB: 110 case PCI_PRODUCT_INTEL_82801BA_SMB: 111 case PCI_PRODUCT_INTEL_82801CA_SMB: 112 case PCI_PRODUCT_INTEL_82801DB_SMB: 113 case PCI_PRODUCT_INTEL_82801E_SMB: 114 case PCI_PRODUCT_INTEL_82801EB_SMB: 115 case PCI_PRODUCT_INTEL_82801FB_SMB: 116 case PCI_PRODUCT_INTEL_82801G_SMB: 117 case PCI_PRODUCT_INTEL_82801H_SMB: 118 case PCI_PRODUCT_INTEL_82801I_SMB: 119 case PCI_PRODUCT_INTEL_82801JD_SMB: 120 case PCI_PRODUCT_INTEL_82801JI_SMB: 121 case PCI_PRODUCT_INTEL_3400_SMB: 122 case PCI_PRODUCT_INTEL_6SERIES_SMB: 123 case PCI_PRODUCT_INTEL_7SERIES_SMB: 124 case PCI_PRODUCT_INTEL_8SERIES_SMB: 125 case PCI_PRODUCT_INTEL_9SERIES_SMB: 126 case PCI_PRODUCT_INTEL_100SERIES_SMB: 127 case PCI_PRODUCT_INTEL_100SERIES_LP_SMB: 128 case PCI_PRODUCT_INTEL_2HS_SMB: 129 case PCI_PRODUCT_INTEL_3HS_SMB: 130 case PCI_PRODUCT_INTEL_CORE4G_M_SMB: 131 case PCI_PRODUCT_INTEL_CORE5G_M_SMB: 132 case PCI_PRODUCT_INTEL_BAYTRAIL_PCU_SMB: 133 case PCI_PRODUCT_INTEL_BSW_PCU_SMB: 134 case PCI_PRODUCT_INTEL_APL_SMB: 135 case PCI_PRODUCT_INTEL_GLK_SMB: 136 case PCI_PRODUCT_INTEL_C600_SMBUS: 137 case PCI_PRODUCT_INTEL_C600_SMB_0: 138 case PCI_PRODUCT_INTEL_C600_SMB_1: 139 case PCI_PRODUCT_INTEL_C600_SMB_2: 140 case PCI_PRODUCT_INTEL_C610_SMB: 141 case PCI_PRODUCT_INTEL_C620_SMB: 142 case PCI_PRODUCT_INTEL_C620_SMB_S: 143 case PCI_PRODUCT_INTEL_EP80579_SMB: 144 case PCI_PRODUCT_INTEL_DH89XXCC_SMB: 145 case PCI_PRODUCT_INTEL_DH89XXCL_SMB: 146 case PCI_PRODUCT_INTEL_C2000_PCU_SMBUS: 147 case PCI_PRODUCT_INTEL_C3K_SMBUS_LEGACY: 148 return 1; 149 } 150 } 151 return 0; 152 } 153 154 static void 155 ichsmb_attach(device_t parent, device_t self, void *aux) 156 { 157 struct ichsmb_softc *sc = device_private(self); 158 struct pci_attach_args *pa = aux; 159 pcireg_t conf; 160 const char *intrstr = NULL; 161 char intrbuf[PCI_INTRSTR_LEN]; 162 int flags; 163 164 sc->sc_dev = self; 165 sc->sc_pc = pa->pa_pc; 166 167 pci_aprint_devinfo(pa, NULL); 168 169 mutex_init(&sc->sc_exec_lock, MUTEX_DEFAULT, IPL_BIO); 170 cv_init(&sc->sc_exec_wait, device_xname(self)); 171 172 /* Read configuration */ 173 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 174 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 175 176 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 177 aprint_error_dev(self, "SMBus disabled\n"); 178 goto out; 179 } 180 181 /* Map I/O space */ 182 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 183 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_size)) { 184 aprint_error_dev(self, "can't map I/O space\n"); 185 goto out; 186 } 187 188 sc->sc_poll = 1; 189 sc->sc_ih = NULL; 190 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 191 /* No PCI IRQ */ 192 aprint_normal_dev(self, "interrupting at SMI\n"); 193 } else { 194 /* Install interrupt handler */ 195 if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0) == 0) { 196 intrstr = pci_intr_string(pa->pa_pc, sc->sc_pihp[0], 197 intrbuf, sizeof(intrbuf)); 198 pci_intr_setattr(pa->pa_pc, &sc->sc_pihp[0], 199 PCI_INTR_MPSAFE, true); 200 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, 201 sc->sc_pihp[0], IPL_BIO, ichsmb_intr, sc, 202 device_xname(sc->sc_dev)); 203 if (sc->sc_ih != NULL) { 204 aprint_normal_dev(self, "interrupting at %s\n", 205 intrstr); 206 sc->sc_poll = 0; 207 } else { 208 pci_intr_release(pa->pa_pc, sc->sc_pihp, 1); 209 sc->sc_pihp = NULL; 210 } 211 } 212 if (sc->sc_poll) 213 aprint_normal_dev(self, "polling\n"); 214 } 215 216 sc->sc_i2c_device = NULL; 217 flags = 0; 218 ichsmb_rescan(self, "i2cbus", &flags); 219 220 out: if (!pmf_device_register(self, NULL, NULL)) 221 aprint_error_dev(self, "couldn't establish power handler\n"); 222 } 223 224 static int 225 ichsmb_rescan(device_t self, const char *ifattr, const int *flags) 226 { 227 struct ichsmb_softc *sc = device_private(self); 228 struct i2cbus_attach_args iba; 229 230 if (!ifattr_match(ifattr, "i2cbus")) 231 return 0; 232 233 if (sc->sc_i2c_device) 234 return 0; 235 236 /* Attach I2C bus */ 237 iic_tag_init(&sc->sc_i2c_tag); 238 sc->sc_i2c_tag.ic_cookie = sc; 239 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 240 241 memset(&iba, 0, sizeof(iba)); 242 iba.iba_tag = &sc->sc_i2c_tag; 243 sc->sc_i2c_device = config_found_ia(self, ifattr, &iba, iicbus_print); 244 245 return 0; 246 } 247 248 static int 249 ichsmb_detach(device_t self, int flags) 250 { 251 struct ichsmb_softc *sc = device_private(self); 252 int error; 253 254 if (sc->sc_i2c_device) { 255 error = config_detach(sc->sc_i2c_device, flags); 256 if (error) 257 return error; 258 } 259 260 iic_tag_fini(&sc->sc_i2c_tag); 261 262 if (sc->sc_ih) { 263 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 264 sc->sc_ih = NULL; 265 } 266 267 if (sc->sc_pihp) { 268 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 269 sc->sc_pihp = NULL; 270 } 271 272 if (sc->sc_size != 0) 273 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_size); 274 275 mutex_destroy(&sc->sc_exec_lock); 276 cv_destroy(&sc->sc_exec_wait); 277 278 return 0; 279 } 280 281 static void 282 ichsmb_chdet(device_t self, device_t child) 283 { 284 struct ichsmb_softc *sc = device_private(self); 285 286 if (sc->sc_i2c_device == child) 287 sc->sc_i2c_device = NULL; 288 } 289 290 static int 291 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 292 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 293 { 294 struct ichsmb_softc *sc = cookie; 295 const uint8_t *b; 296 uint8_t ctl = 0, st; 297 int retries; 298 char fbuf[64]; 299 300 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 301 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 302 len, flags)); 303 304 mutex_enter(&sc->sc_exec_lock); 305 306 /* Clear status bits */ 307 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 308 LPCIB_SMB_HS_INTR | LPCIB_SMB_HS_DEVERR | 309 LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED); 310 bus_space_barrier(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 1, 311 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 312 313 /* Wait for bus to be idle */ 314 for (retries = 100; retries > 0; retries--) { 315 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 316 if (!(st & LPCIB_SMB_HS_BUSY)) 317 break; 318 DELAY(ICHIIC_DELAY); 319 } 320 #ifdef ICHIIC_DEBUG 321 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 322 printf("%s: exec: st %s\n", device_xname(sc->sc_dev), fbuf); 323 #endif 324 if (st & LPCIB_SMB_HS_BUSY) { 325 mutex_exit(&sc->sc_exec_lock); 326 return (EBUSY); 327 } 328 329 if (sc->sc_poll) 330 flags |= I2C_F_POLL; 331 332 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 333 (cmdlen == 0 && len > 1)) { 334 mutex_exit(&sc->sc_exec_lock); 335 return (EINVAL); 336 } 337 338 /* Setup transfer */ 339 sc->sc_i2c_xfer.op = op; 340 sc->sc_i2c_xfer.buf = buf; 341 sc->sc_i2c_xfer.len = len; 342 sc->sc_i2c_xfer.flags = flags; 343 sc->sc_i2c_xfer.error = 0; 344 sc->sc_i2c_xfer.done = false; 345 346 /* Set slave address and transfer direction */ 347 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 348 LPCIB_SMB_TXSLVA_ADDR(addr) | 349 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 350 351 b = (const uint8_t *)cmdbuf; 352 if (cmdlen > 0) 353 /* Set command byte */ 354 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 355 356 if (I2C_OP_WRITE_P(op)) { 357 /* Write data */ 358 b = buf; 359 if (cmdlen == 0 && len == 1) 360 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 361 LPCIB_SMB_HCMD, b[0]); 362 else if (len > 0) 363 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 364 LPCIB_SMB_HD0, b[0]); 365 if (len > 1) 366 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 367 LPCIB_SMB_HD1, b[1]); 368 } 369 370 /* Set SMBus command */ 371 if (cmdlen == 0) { 372 if (len == 0) 373 ctl = LPCIB_SMB_HC_CMD_QUICK; 374 else 375 ctl = LPCIB_SMB_HC_CMD_BYTE; 376 } else if (len == 1) 377 ctl = LPCIB_SMB_HC_CMD_BDATA; 378 else if (len == 2) 379 ctl = LPCIB_SMB_HC_CMD_WDATA; 380 381 if ((flags & I2C_F_POLL) == 0) 382 ctl |= LPCIB_SMB_HC_INTREN; 383 384 /* Start transaction */ 385 ctl |= LPCIB_SMB_HC_START; 386 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 387 388 if (flags & I2C_F_POLL) { 389 /* Poll for completion */ 390 DELAY(ICHIIC_DELAY); 391 for (retries = 1000; retries > 0; retries--) { 392 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 393 LPCIB_SMB_HS); 394 if ((st & LPCIB_SMB_HS_BUSY) == 0) 395 break; 396 DELAY(ICHIIC_DELAY); 397 } 398 if (st & LPCIB_SMB_HS_BUSY) 399 goto timeout; 400 ichsmb_intr(sc); 401 } else { 402 /* Wait for interrupt */ 403 while (! sc->sc_i2c_xfer.done) { 404 if (cv_timedwait(&sc->sc_exec_wait, &sc->sc_exec_lock, 405 ICHIIC_TIMEOUT * hz)) 406 goto timeout; 407 } 408 } 409 410 int error = sc->sc_i2c_xfer.error; 411 mutex_exit(&sc->sc_exec_lock); 412 413 return (error); 414 415 timeout: 416 /* 417 * Transfer timeout. Kill the transaction and clear status bits. 418 */ 419 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 420 aprint_error_dev(sc->sc_dev, 421 "exec: op %d, addr 0x%02x, cmdlen %zd, len %zd, " 422 "flags 0x%02x: timeout, status %s\n", 423 op, addr, cmdlen, len, flags, fbuf); 424 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 425 LPCIB_SMB_HC_KILL); 426 DELAY(ICHIIC_DELAY); 427 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 428 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 429 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 430 aprint_error_dev(sc->sc_dev, "abort failed, status %s\n", 431 fbuf); 432 } 433 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 434 mutex_exit(&sc->sc_exec_lock); 435 return (ETIMEDOUT); 436 } 437 438 static int 439 ichsmb_intr(void *arg) 440 { 441 struct ichsmb_softc *sc = arg; 442 uint8_t st; 443 uint8_t *b; 444 size_t len; 445 #ifdef ICHIIC_DEBUG 446 char fbuf[64]; 447 #endif 448 449 /* Read status */ 450 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 451 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 452 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 453 LPCIB_SMB_HS_SMBAL | LPCIB_SMB_HS_BDONE)) == 0) 454 /* Interrupt was not for us */ 455 return (0); 456 457 #ifdef ICHIIC_DEBUG 458 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 459 printf("%s: intr st %s\n", device_xname(sc->sc_dev), fbuf); 460 #endif 461 462 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 463 mutex_enter(&sc->sc_exec_lock); 464 465 /* Clear status bits */ 466 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 467 468 /* Check for errors */ 469 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 470 sc->sc_i2c_xfer.error = EIO; 471 goto done; 472 } 473 474 if (st & LPCIB_SMB_HS_INTR) { 475 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 476 goto done; 477 478 /* Read data */ 479 b = sc->sc_i2c_xfer.buf; 480 len = sc->sc_i2c_xfer.len; 481 if (len > 0) 482 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 483 LPCIB_SMB_HD0); 484 if (len > 1) 485 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 486 LPCIB_SMB_HD1); 487 } 488 489 done: 490 sc->sc_i2c_xfer.done = true; 491 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) { 492 cv_signal(&sc->sc_exec_wait); 493 mutex_exit(&sc->sc_exec_lock); 494 } 495 return (1); 496 } 497 498 MODULE(MODULE_CLASS_DRIVER, ichsmb, "pci,iic"); 499 500 #ifdef _MODULE 501 #include "ioconf.c" 502 #endif 503 504 static int 505 ichsmb_modcmd(modcmd_t cmd, void *opaque) 506 { 507 int error = 0; 508 509 switch (cmd) { 510 case MODULE_CMD_INIT: 511 #ifdef _MODULE 512 error = config_init_component(cfdriver_ioconf_ichsmb, 513 cfattach_ioconf_ichsmb, cfdata_ioconf_ichsmb); 514 #endif 515 break; 516 case MODULE_CMD_FINI: 517 #ifdef _MODULE 518 error = config_fini_component(cfdriver_ioconf_ichsmb, 519 cfattach_ioconf_ichsmb, cfdata_ioconf_ichsmb); 520 #endif 521 break; 522 default: 523 #ifdef _MODULE 524 error = ENOTTY; 525 #endif 526 break; 527 } 528 529 return error; 530 } 531
Indexes created Thu Oct 02 14:10:14 GMT 2025