ichsmb.c revision 1.68
1 /* $NetBSD: ichsmb.c,v 1.68 2020/04/22 07:17:01 msaitoh Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.18 2007/05/03 09:36:26 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.68 2020/04/22 07:17:01 msaitoh Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/condvar.h> 33 #include <sys/proc.h> 34 #include <sys/module.h> 35 36 #include <sys/bus.h> 37 38 #include <dev/pci/pcidevs.h> 39 #include <dev/pci/pcireg.h> 40 #include <dev/pci/pcivar.h> 41 42 #include <dev/ic/i82801lpcreg.h> 43 44 #include <dev/i2c/i2cvar.h> 45 46 #ifdef ICHIIC_DEBUG 47 #define DPRINTF(x) printf x 48 #else 49 #define DPRINTF(x) 50 #endif 51 52 #define ICHIIC_DELAY 100 53 #define ICHIIC_TIMEOUT 1 54 55 struct ichsmb_softc { 56 device_t sc_dev; 57 58 bus_space_tag_t sc_iot; 59 bus_space_handle_t sc_ioh; 60 bus_size_t sc_size; 61 pci_chipset_tag_t sc_pc; 62 void * sc_ih; 63 int sc_poll; 64 pci_intr_handle_t *sc_pihp; 65 66 kmutex_t sc_exec_lock; 67 kcondvar_t sc_exec_wait; 68 69 struct i2c_controller sc_i2c_tag; 70 struct { 71 i2c_op_t op; 72 void * buf; 73 size_t len; 74 int flags; 75 int error; 76 bool done; 77 } sc_i2c_xfer; 78 device_t sc_i2c_device; 79 }; 80 81 static int ichsmb_match(device_t, cfdata_t, void *); 82 static void ichsmb_attach(device_t, device_t, void *); 83 static int ichsmb_detach(device_t, int); 84 static int ichsmb_rescan(device_t, const char *, const int *); 85 static void ichsmb_chdet(device_t, device_t); 86 87 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 88 size_t, void *, size_t, int); 89 90 static int ichsmb_intr(void *); 91 92 #include "ioconf.h" 93 94 CFATTACH_DECL3_NEW(ichsmb, sizeof(struct ichsmb_softc), 95 ichsmb_match, ichsmb_attach, ichsmb_detach, NULL, ichsmb_rescan, 96 ichsmb_chdet, DVF_DETACH_SHUTDOWN); 97 98 99 static int 100 ichsmb_match(device_t parent, cfdata_t match, void *aux) 101 { 102 struct pci_attach_args *pa = aux; 103 104 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 105 switch (PCI_PRODUCT(pa->pa_id)) { 106 case PCI_PRODUCT_INTEL_6300ESB_SMB: 107 case PCI_PRODUCT_INTEL_63XXESB_SMB: 108 case PCI_PRODUCT_INTEL_82801AA_SMB: 109 case PCI_PRODUCT_INTEL_82801AB_SMB: 110 case PCI_PRODUCT_INTEL_82801BA_SMB: 111 case PCI_PRODUCT_INTEL_82801CA_SMB: 112 case PCI_PRODUCT_INTEL_82801DB_SMB: 113 case PCI_PRODUCT_INTEL_82801E_SMB: 114 case PCI_PRODUCT_INTEL_82801EB_SMB: 115 case PCI_PRODUCT_INTEL_82801FB_SMB: 116 case PCI_PRODUCT_INTEL_82801G_SMB: 117 case PCI_PRODUCT_INTEL_82801H_SMB: 118 case PCI_PRODUCT_INTEL_82801I_SMB: 119 case PCI_PRODUCT_INTEL_82801JD_SMB: 120 case PCI_PRODUCT_INTEL_82801JI_SMB: 121 case PCI_PRODUCT_INTEL_3400_SMB: 122 case PCI_PRODUCT_INTEL_6SERIES_SMB: 123 case PCI_PRODUCT_INTEL_7SERIES_SMB: 124 case PCI_PRODUCT_INTEL_8SERIES_SMB: 125 case PCI_PRODUCT_INTEL_9SERIES_SMB: 126 case PCI_PRODUCT_INTEL_100SERIES_SMB: 127 case PCI_PRODUCT_INTEL_100SERIES_LP_SMB: 128 case PCI_PRODUCT_INTEL_2HS_SMB: 129 case PCI_PRODUCT_INTEL_3HS_SMB: 130 case PCI_PRODUCT_INTEL_3HS_U_SMB: 131 case PCI_PRODUCT_INTEL_CORE4G_M_SMB: 132 case PCI_PRODUCT_INTEL_CORE5G_M_SMB: 133 case PCI_PRODUCT_INTEL_CMTLK_SMB: 134 case PCI_PRODUCT_INTEL_BAYTRAIL_PCU_SMB: 135 case PCI_PRODUCT_INTEL_BSW_PCU_SMB: 136 case PCI_PRODUCT_INTEL_APL_SMB: 137 case PCI_PRODUCT_INTEL_GLK_SMB: 138 case PCI_PRODUCT_INTEL_C600_SMBUS: 139 case PCI_PRODUCT_INTEL_C600_SMB_0: 140 case PCI_PRODUCT_INTEL_C600_SMB_1: 141 case PCI_PRODUCT_INTEL_C600_SMB_2: 142 case PCI_PRODUCT_INTEL_C610_SMB: 143 case PCI_PRODUCT_INTEL_C620_SMB: 144 case PCI_PRODUCT_INTEL_C620_SMB_S: 145 case PCI_PRODUCT_INTEL_EP80579_SMB: 146 case PCI_PRODUCT_INTEL_DH89XXCC_SMB: 147 case PCI_PRODUCT_INTEL_DH89XXCL_SMB: 148 case PCI_PRODUCT_INTEL_C2000_PCU_SMBUS: 149 case PCI_PRODUCT_INTEL_C3K_SMBUS_LEGACY: 150 return 1; 151 } 152 } 153 return 0; 154 } 155 156 static void 157 ichsmb_attach(device_t parent, device_t self, void *aux) 158 { 159 struct ichsmb_softc *sc = device_private(self); 160 struct pci_attach_args *pa = aux; 161 pcireg_t conf; 162 const char *intrstr = NULL; 163 char intrbuf[PCI_INTRSTR_LEN]; 164 int flags; 165 166 sc->sc_dev = self; 167 sc->sc_pc = pa->pa_pc; 168 169 pci_aprint_devinfo(pa, NULL); 170 171 mutex_init(&sc->sc_exec_lock, MUTEX_DEFAULT, IPL_BIO); 172 cv_init(&sc->sc_exec_wait, device_xname(self)); 173 174 /* Read configuration */ 175 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 176 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 177 178 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 179 aprint_error_dev(self, "SMBus disabled\n"); 180 goto out; 181 } 182 183 /* Map I/O space */ 184 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 185 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_size)) { 186 aprint_error_dev(self, "can't map I/O space\n"); 187 goto out; 188 } 189 190 sc->sc_poll = 1; 191 sc->sc_ih = NULL; 192 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 193 /* No PCI IRQ */ 194 aprint_normal_dev(self, "interrupting at SMI\n"); 195 } else { 196 /* Install interrupt handler */ 197 if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0) == 0) { 198 intrstr = pci_intr_string(pa->pa_pc, sc->sc_pihp[0], 199 intrbuf, sizeof(intrbuf)); 200 pci_intr_setattr(pa->pa_pc, &sc->sc_pihp[0], 201 PCI_INTR_MPSAFE, true); 202 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, 203 sc->sc_pihp[0], IPL_BIO, ichsmb_intr, sc, 204 device_xname(sc->sc_dev)); 205 if (sc->sc_ih != NULL) { 206 aprint_normal_dev(self, "interrupting at %s\n", 207 intrstr); 208 sc->sc_poll = 0; 209 } else { 210 pci_intr_release(pa->pa_pc, sc->sc_pihp, 1); 211 sc->sc_pihp = NULL; 212 } 213 } 214 if (sc->sc_poll) 215 aprint_normal_dev(self, "polling\n"); 216 } 217 218 sc->sc_i2c_device = NULL; 219 flags = 0; 220 ichsmb_rescan(self, "i2cbus", &flags); 221 222 out: if (!pmf_device_register(self, NULL, NULL)) 223 aprint_error_dev(self, "couldn't establish power handler\n"); 224 } 225 226 static int 227 ichsmb_rescan(device_t self, const char *ifattr, const int *flags) 228 { 229 struct ichsmb_softc *sc = device_private(self); 230 struct i2cbus_attach_args iba; 231 232 if (!ifattr_match(ifattr, "i2cbus")) 233 return 0; 234 235 if (sc->sc_i2c_device) 236 return 0; 237 238 /* Attach I2C bus */ 239 iic_tag_init(&sc->sc_i2c_tag); 240 sc->sc_i2c_tag.ic_cookie = sc; 241 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 242 243 memset(&iba, 0, sizeof(iba)); 244 iba.iba_tag = &sc->sc_i2c_tag; 245 sc->sc_i2c_device = config_found_ia(self, ifattr, &iba, iicbus_print); 246 247 return 0; 248 } 249 250 static int 251 ichsmb_detach(device_t self, int flags) 252 { 253 struct ichsmb_softc *sc = device_private(self); 254 int error; 255 256 if (sc->sc_i2c_device) { 257 error = config_detach(sc->sc_i2c_device, flags); 258 if (error) 259 return error; 260 } 261 262 iic_tag_fini(&sc->sc_i2c_tag); 263 264 if (sc->sc_ih) { 265 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 266 sc->sc_ih = NULL; 267 } 268 269 if (sc->sc_pihp) { 270 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 271 sc->sc_pihp = NULL; 272 } 273 274 if (sc->sc_size != 0) 275 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_size); 276 277 mutex_destroy(&sc->sc_exec_lock); 278 cv_destroy(&sc->sc_exec_wait); 279 280 return 0; 281 } 282 283 static void 284 ichsmb_chdet(device_t self, device_t child) 285 { 286 struct ichsmb_softc *sc = device_private(self); 287 288 if (sc->sc_i2c_device == child) 289 sc->sc_i2c_device = NULL; 290 } 291 292 static int 293 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 294 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 295 { 296 struct ichsmb_softc *sc = cookie; 297 const uint8_t *b; 298 uint8_t ctl = 0, st; 299 int retries; 300 char fbuf[64]; 301 302 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 303 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 304 len, flags)); 305 306 mutex_enter(&sc->sc_exec_lock); 307 308 /* Clear status bits */ 309 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 310 LPCIB_SMB_HS_INTR | LPCIB_SMB_HS_DEVERR | 311 LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED); 312 bus_space_barrier(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 1, 313 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 314 315 /* Wait for bus to be idle */ 316 for (retries = 100; retries > 0; retries--) { 317 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 318 if (!(st & LPCIB_SMB_HS_BUSY)) 319 break; 320 DELAY(ICHIIC_DELAY); 321 } 322 #ifdef ICHIIC_DEBUG 323 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 324 printf("%s: exec: st %s\n", device_xname(sc->sc_dev), fbuf); 325 #endif 326 if (st & LPCIB_SMB_HS_BUSY) { 327 mutex_exit(&sc->sc_exec_lock); 328 return (EBUSY); 329 } 330 331 if (sc->sc_poll) 332 flags |= I2C_F_POLL; 333 334 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 335 (cmdlen == 0 && len > 1)) { 336 mutex_exit(&sc->sc_exec_lock); 337 return (EINVAL); 338 } 339 340 /* Setup transfer */ 341 sc->sc_i2c_xfer.op = op; 342 sc->sc_i2c_xfer.buf = buf; 343 sc->sc_i2c_xfer.len = len; 344 sc->sc_i2c_xfer.flags = flags; 345 sc->sc_i2c_xfer.error = 0; 346 sc->sc_i2c_xfer.done = false; 347 348 /* Set slave address and transfer direction */ 349 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 350 LPCIB_SMB_TXSLVA_ADDR(addr) | 351 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 352 353 b = (const uint8_t *)cmdbuf; 354 if (cmdlen > 0) 355 /* Set command byte */ 356 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 357 358 if (I2C_OP_WRITE_P(op)) { 359 /* Write data */ 360 b = buf; 361 if (cmdlen == 0 && len == 1) 362 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 363 LPCIB_SMB_HCMD, b[0]); 364 else if (len > 0) 365 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 366 LPCIB_SMB_HD0, b[0]); 367 if (len > 1) 368 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 369 LPCIB_SMB_HD1, b[1]); 370 } 371 372 /* Set SMBus command */ 373 if (cmdlen == 0) { 374 if (len == 0) 375 ctl = LPCIB_SMB_HC_CMD_QUICK; 376 else 377 ctl = LPCIB_SMB_HC_CMD_BYTE; 378 } else if (len == 1) 379 ctl = LPCIB_SMB_HC_CMD_BDATA; 380 else if (len == 2) 381 ctl = LPCIB_SMB_HC_CMD_WDATA; 382 383 if ((flags & I2C_F_POLL) == 0) 384 ctl |= LPCIB_SMB_HC_INTREN; 385 386 /* Start transaction */ 387 ctl |= LPCIB_SMB_HC_START; 388 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 389 390 if (flags & I2C_F_POLL) { 391 /* Poll for completion */ 392 DELAY(ICHIIC_DELAY); 393 for (retries = 1000; retries > 0; retries--) { 394 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 395 LPCIB_SMB_HS); 396 if ((st & LPCIB_SMB_HS_BUSY) == 0) 397 break; 398 DELAY(ICHIIC_DELAY); 399 } 400 if (st & LPCIB_SMB_HS_BUSY) 401 goto timeout; 402 ichsmb_intr(sc); 403 } else { 404 /* Wait for interrupt */ 405 while (! sc->sc_i2c_xfer.done) { 406 if (cv_timedwait(&sc->sc_exec_wait, &sc->sc_exec_lock, 407 ICHIIC_TIMEOUT * hz)) 408 goto timeout; 409 } 410 } 411 412 int error = sc->sc_i2c_xfer.error; 413 mutex_exit(&sc->sc_exec_lock); 414 415 return (error); 416 417 timeout: 418 /* 419 * Transfer timeout. Kill the transaction and clear status bits. 420 */ 421 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 422 aprint_error_dev(sc->sc_dev, 423 "exec: op %d, addr 0x%02x, cmdlen %zd, len %zd, " 424 "flags 0x%02x: timeout, status %s\n", 425 op, addr, cmdlen, len, flags, fbuf); 426 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 427 LPCIB_SMB_HC_KILL); 428 DELAY(ICHIIC_DELAY); 429 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 430 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 431 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 432 aprint_error_dev(sc->sc_dev, "abort failed, status %s\n", 433 fbuf); 434 } 435 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 436 mutex_exit(&sc->sc_exec_lock); 437 return (ETIMEDOUT); 438 } 439 440 static int 441 ichsmb_intr(void *arg) 442 { 443 struct ichsmb_softc *sc = arg; 444 uint8_t st; 445 uint8_t *b; 446 size_t len; 447 #ifdef ICHIIC_DEBUG 448 char fbuf[64]; 449 #endif 450 451 /* Read status */ 452 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 453 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 454 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 455 LPCIB_SMB_HS_SMBAL | LPCIB_SMB_HS_BDONE)) == 0) 456 /* Interrupt was not for us */ 457 return (0); 458 459 #ifdef ICHIIC_DEBUG 460 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 461 printf("%s: intr st %s\n", device_xname(sc->sc_dev), fbuf); 462 #endif 463 464 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 465 mutex_enter(&sc->sc_exec_lock); 466 467 /* Clear status bits */ 468 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 469 470 /* Check for errors */ 471 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 472 sc->sc_i2c_xfer.error = EIO; 473 goto done; 474 } 475 476 if (st & LPCIB_SMB_HS_INTR) { 477 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 478 goto done; 479 480 /* Read data */ 481 b = sc->sc_i2c_xfer.buf; 482 len = sc->sc_i2c_xfer.len; 483 if (len > 0) 484 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 485 LPCIB_SMB_HD0); 486 if (len > 1) 487 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 488 LPCIB_SMB_HD1); 489 } 490 491 done: 492 sc->sc_i2c_xfer.done = true; 493 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) { 494 cv_signal(&sc->sc_exec_wait); 495 mutex_exit(&sc->sc_exec_lock); 496 } 497 return (1); 498 } 499 500 MODULE(MODULE_CLASS_DRIVER, ichsmb, "pci,iic"); 501 502 #ifdef _MODULE 503 #include "ioconf.c" 504 #endif 505 506 static int 507 ichsmb_modcmd(modcmd_t cmd, void *opaque) 508 { 509 int error = 0; 510 511 switch (cmd) { 512 case MODULE_CMD_INIT: 513 #ifdef _MODULE 514 error = config_init_component(cfdriver_ioconf_ichsmb, 515 cfattach_ioconf_ichsmb, cfdata_ioconf_ichsmb); 516 #endif 517 break; 518 case MODULE_CMD_FINI: 519 #ifdef _MODULE 520 error = config_fini_component(cfdriver_ioconf_ichsmb, 521 cfattach_ioconf_ichsmb, cfdata_ioconf_ichsmb); 522 #endif 523 break; 524 default: 525 #ifdef _MODULE 526 error = ENOTTY; 527 #endif 528 break; 529 } 530 531 return error; 532 } 533
Indexes created Thu Oct 02 14:10:14 GMT 2025