ichsmb.c revision 1.7
1 /* $NetBSD: ichsmb.c,v 1.7 2007/08/27 09:09:22 xtraeme Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.18 2007/05/03 09:36:26 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.7 2007/08/27 09:09:22 xtraeme Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/lock.h> 32 #include <sys/proc.h> 33 34 #include <machine/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/ic/i82801lpcreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #ifdef ICHIIC_DEBUG 45 #define DPRINTF(x) printf x 46 #else 47 #define DPRINTF(x) 48 #endif 49 50 #define ICHIIC_DELAY 100 51 #define ICHIIC_TIMEOUT 1 52 53 struct ichsmb_softc { 54 struct device sc_dev; 55 56 bus_space_tag_t sc_iot; 57 bus_space_handle_t sc_ioh; 58 void * sc_ih; 59 int sc_poll; 60 61 struct i2c_controller sc_i2c_tag; 62 struct lock sc_i2c_lock; 63 struct { 64 i2c_op_t op; 65 void * buf; 66 size_t len; 67 int flags; 68 volatile int error; 69 } sc_i2c_xfer; 70 }; 71 72 static int ichsmb_match(struct device *, struct cfdata *, void *); 73 static void ichsmb_attach(struct device *, struct device *, void *); 74 75 static int ichsmb_i2c_acquire_bus(void *, int); 76 static void ichsmb_i2c_release_bus(void *, int); 77 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 78 size_t, void *, size_t, int); 79 80 static int ichsmb_intr(void *); 81 82 83 CFATTACH_DECL(ichsmb, sizeof(struct ichsmb_softc), 84 ichsmb_match, ichsmb_attach, NULL, NULL); 85 86 87 static int 88 ichsmb_match(struct device *parent, struct cfdata *match, void *aux) 89 { 90 struct pci_attach_args *pa = aux; 91 92 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 93 switch (PCI_PRODUCT(pa->pa_id)) { 94 case PCI_PRODUCT_INTEL_6300ESB_SMB: 95 case PCI_PRODUCT_INTEL_63XXESB_SMB: 96 case PCI_PRODUCT_INTEL_82801AA_SMB: 97 case PCI_PRODUCT_INTEL_82801AB_SMB: 98 case PCI_PRODUCT_INTEL_82801BA_SMB: 99 case PCI_PRODUCT_INTEL_82801CA_SMB: 100 case PCI_PRODUCT_INTEL_82801DB_SMB: 101 case PCI_PRODUCT_INTEL_82801E_SMB: 102 case PCI_PRODUCT_INTEL_82801EB_SMB: 103 case PCI_PRODUCT_INTEL_82801FB_SMB: 104 case PCI_PRODUCT_INTEL_82801G_SMB: 105 case PCI_PRODUCT_INTEL_82801H_SMB: 106 case PCI_PRODUCT_INTEL_82801I_SMB: 107 return 1; 108 } 109 } 110 return 0; 111 } 112 113 static void 114 ichsmb_attach(struct device *parent, struct device *self, void *aux) 115 { 116 struct ichsmb_softc *sc = (struct ichsmb_softc *)self; 117 struct pci_attach_args *pa = aux; 118 struct i2cbus_attach_args iba; 119 pcireg_t conf; 120 bus_size_t iosize; 121 pci_intr_handle_t ih; 122 const char *intrstr = NULL; 123 char devinfo[256]; 124 125 aprint_naive("\n"); 126 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 127 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 128 PCI_REVISION(pa->pa_class)); 129 130 /* Read configuration */ 131 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 132 DPRINTF(("%s: conf 0x%08x", sc->sc_dev.dv_xname, conf)); 133 134 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 135 aprint_error("%s: SMBus disabled\n", sc->sc_dev.dv_xname); 136 return; 137 } 138 139 /* Map I/O space */ 140 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 141 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize)) { 142 aprint_error("%s: can't map I/O space\n", sc->sc_dev.dv_xname); 143 return; 144 } 145 146 sc->sc_poll = 1; 147 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 148 /* No PCI IRQ */ 149 aprint_normal("%s: SMI\n", sc->sc_dev.dv_xname); 150 } else { 151 /* Install interrupt handler */ 152 if (pci_intr_map(pa, &ih) == 0) { 153 intrstr = pci_intr_string(pa->pa_pc, ih); 154 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 155 ichsmb_intr, sc); 156 if (sc->sc_ih != NULL) { 157 aprint_normal("%s: interrupting at %s\n", 158 sc->sc_dev.dv_xname, intrstr); 159 sc->sc_poll = 0; 160 } 161 } 162 if (sc->sc_poll) 163 aprint_normal("%s: polling\n", sc->sc_dev.dv_xname); 164 } 165 166 /* Attach I2C bus */ 167 lockinit(&sc->sc_i2c_lock, PZERO, "smblk", 0, 0); 168 sc->sc_i2c_tag.ic_cookie = sc; 169 sc->sc_i2c_tag.ic_acquire_bus = ichsmb_i2c_acquire_bus; 170 sc->sc_i2c_tag.ic_release_bus = ichsmb_i2c_release_bus; 171 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 172 173 bzero(&iba, sizeof(iba)); 174 iba.iba_tag = &sc->sc_i2c_tag; 175 config_found(self, &iba, iicbus_print); 176 177 return; 178 } 179 180 static int 181 ichsmb_i2c_acquire_bus(void *cookie, int flags) 182 { 183 struct ichsmb_softc *sc = cookie; 184 185 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 186 return (0); 187 188 return (lockmgr(&sc->sc_i2c_lock, LK_EXCLUSIVE, NULL)); 189 } 190 191 static void 192 ichsmb_i2c_release_bus(void *cookie, int flags) 193 { 194 struct ichsmb_softc *sc = cookie; 195 196 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 197 return; 198 199 lockmgr(&sc->sc_i2c_lock, LK_RELEASE, NULL); 200 } 201 202 static int 203 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 204 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 205 { 206 struct ichsmb_softc *sc = cookie; 207 const uint8_t *b; 208 uint8_t ctl = 0, st; 209 int retries; 210 char fbuf[64]; 211 212 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %d, " 213 "flags 0x%02x\n", sc->sc_dev.dv_xname, op, addr, cmdlen, 214 len, flags)); 215 216 /* Wait for bus to be idle */ 217 for (retries = 100; retries > 0; retries--) { 218 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 219 if (!(st & LPCIB_SMB_HS_BUSY)) 220 break; 221 DELAY(ICHIIC_DELAY); 222 } 223 #ifdef ICHIIC_DEBUG 224 bitmask_snprintf(st, LPCIB_SMB_HS_BITS, fbuf, sizeof(fbuf)); 225 printf("%s: exec: st 0x%s\n", sc->sc_dev.dv_xname, fbuf); 226 #endif 227 if (st & LPCIB_SMB_HS_BUSY) 228 return (1); 229 230 if (cold || sc->sc_poll) 231 flags |= I2C_F_POLL; 232 233 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2) 234 return (1); 235 236 /* Setup transfer */ 237 sc->sc_i2c_xfer.op = op; 238 sc->sc_i2c_xfer.buf = buf; 239 sc->sc_i2c_xfer.len = len; 240 sc->sc_i2c_xfer.flags = flags; 241 sc->sc_i2c_xfer.error = 0; 242 243 /* Set slave address and transfer direction */ 244 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 245 LPCIB_SMB_TXSLVA_ADDR(addr) | 246 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 247 248 b = (const uint8_t *)cmdbuf; 249 if (cmdlen > 0) 250 /* Set command byte */ 251 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 252 253 if (I2C_OP_WRITE_P(op)) { 254 /* Write data */ 255 b = buf; 256 if (len > 0) 257 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 258 LPCIB_SMB_HD0, b[0]); 259 if (len > 1) 260 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 261 LPCIB_SMB_HD1, b[1]); 262 } 263 264 /* Set SMBus command */ 265 if (len == 0) 266 ctl = LPCIB_SMB_HC_CMD_BYTE; 267 else if (len == 1) 268 ctl = LPCIB_SMB_HC_CMD_BDATA; 269 else if (len == 2) 270 ctl = LPCIB_SMB_HC_CMD_WDATA; 271 272 if ((flags & I2C_F_POLL) == 0) 273 ctl |= LPCIB_SMB_HC_INTREN; 274 275 /* Start transaction */ 276 ctl |= LPCIB_SMB_HC_START; 277 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 278 279 if (flags & I2C_F_POLL) { 280 /* Poll for completion */ 281 DELAY(ICHIIC_DELAY); 282 for (retries = 1000; retries > 0; retries--) { 283 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 284 LPCIB_SMB_HS); 285 if ((st & LPCIB_SMB_HS_BUSY) == 0) 286 break; 287 DELAY(ICHIIC_DELAY); 288 } 289 if (st & LPCIB_SMB_HS_BUSY) 290 goto timeout; 291 ichsmb_intr(sc); 292 } else { 293 /* Wait for interrupt */ 294 if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz)) 295 goto timeout; 296 } 297 298 if (sc->sc_i2c_xfer.error) 299 return (1); 300 301 return (0); 302 303 timeout: 304 /* 305 * Transfer timeout. Kill the transaction and clear status bits. 306 */ 307 bitmask_snprintf(st, LPCIB_SMB_HS_BITS, fbuf, sizeof(fbuf)); 308 printf("%s: exec: op %d, addr 0x%02x, cmdlen %zd, len %zd, " 309 "flags 0x%02x: timeout, status 0x%s\n", 310 sc->sc_dev.dv_xname, op, addr, cmdlen, len, flags, fbuf); 311 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 312 LPCIB_SMB_HC_KILL); 313 DELAY(ICHIIC_DELAY); 314 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 315 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 316 bitmask_snprintf(st, LPCIB_SMB_HS_BITS, fbuf, sizeof(fbuf)); 317 printf("%s: abort failed, status 0x%s\n", 318 sc->sc_dev.dv_xname, fbuf); 319 } 320 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 321 return (1); 322 } 323 324 static int 325 ichsmb_intr(void *arg) 326 { 327 struct ichsmb_softc *sc = arg; 328 uint8_t st; 329 uint8_t *b; 330 size_t len; 331 #ifdef ICHIIC_DEBUG 332 char fbuf[64]; 333 #endif 334 335 /* Read status */ 336 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 337 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 338 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 339 LPCIB_SMB_HS_SMBAL | LPCIB_SMB_HS_BDONE)) == 0) 340 /* Interrupt was not for us */ 341 return (0); 342 343 #ifdef ICHIIC_DEBUG 344 bitmask_snprintf(st, LPCIB_SMB_HS_BITS, fbuf, sizeof(fbuf)); 345 printf("%s: intr st 0x%s\n", sc->sc_dev.dv_xname, fbuf); 346 #endif 347 348 /* Clear status bits */ 349 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 350 351 /* Check for errors */ 352 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 353 sc->sc_i2c_xfer.error = 1; 354 goto done; 355 } 356 357 if (st & LPCIB_SMB_HS_INTR) { 358 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 359 goto done; 360 361 /* Read data */ 362 b = sc->sc_i2c_xfer.buf; 363 len = sc->sc_i2c_xfer.len; 364 if (len > 0) 365 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 366 LPCIB_SMB_HD0); 367 if (len > 1) 368 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 369 LPCIB_SMB_HD1); 370 } 371 372 done: 373 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 374 wakeup(sc); 375 return (1); 376 } 377
Indexes created Thu Oct 02 14:10:14 GMT 2025