ichsmb.c revision 1.72
1 /* $NetBSD: ichsmb.c,v 1.72 2021/08/07 16:19:14 thorpej Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.44 2020/10/07 11:23:05 jsg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.72 2021/08/07 16:19:14 thorpej Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/condvar.h> 33 #include <sys/module.h> 34 35 #include <sys/bus.h> 36 37 #include <dev/pci/pcidevs.h> 38 #include <dev/pci/pcireg.h> 39 #include <dev/pci/pcivar.h> 40 41 #include <dev/ic/i82801lpcreg.h> 42 43 #include <dev/i2c/i2cvar.h> 44 45 #ifdef ICHIIC_DEBUG 46 #define DPRINTF(x) printf x 47 #else 48 #define DPRINTF(x) 49 #endif 50 51 #define ICHIIC_DELAY 100 52 #define ICHIIC_TIMEOUT 1 53 54 struct ichsmb_softc { 55 device_t sc_dev; 56 57 bus_space_tag_t sc_iot; 58 bus_space_handle_t sc_ioh; 59 bus_size_t sc_size; 60 pci_chipset_tag_t sc_pc; 61 void * sc_ih; 62 int sc_poll; 63 pci_intr_handle_t *sc_pihp; 64 65 kmutex_t sc_exec_lock; 66 kcondvar_t sc_exec_wait; 67 68 struct i2c_controller sc_i2c_tag; 69 struct { 70 i2c_op_t op; 71 void * buf; 72 size_t len; 73 int flags; 74 int error; 75 bool done; 76 } sc_i2c_xfer; 77 device_t sc_i2c_device; 78 }; 79 80 static int ichsmb_match(device_t, cfdata_t, void *); 81 static void ichsmb_attach(device_t, device_t, void *); 82 static int ichsmb_detach(device_t, int); 83 static int ichsmb_rescan(device_t, const char *, const int *); 84 static void ichsmb_chdet(device_t, device_t); 85 86 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 87 size_t, void *, size_t, int); 88 89 static int ichsmb_intr(void *); 90 91 #include "ioconf.h" 92 93 CFATTACH_DECL3_NEW(ichsmb, sizeof(struct ichsmb_softc), 94 ichsmb_match, ichsmb_attach, ichsmb_detach, NULL, ichsmb_rescan, 95 ichsmb_chdet, DVF_DETACH_SHUTDOWN); 96 97 98 static int 99 ichsmb_match(device_t parent, cfdata_t match, void *aux) 100 { 101 struct pci_attach_args *pa = aux; 102 103 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 104 switch (PCI_PRODUCT(pa->pa_id)) { 105 case PCI_PRODUCT_INTEL_6300ESB_SMB: 106 case PCI_PRODUCT_INTEL_63XXESB_SMB: 107 case PCI_PRODUCT_INTEL_82801AA_SMB: 108 case PCI_PRODUCT_INTEL_82801AB_SMB: 109 case PCI_PRODUCT_INTEL_82801BA_SMB: 110 case PCI_PRODUCT_INTEL_82801CA_SMB: 111 case PCI_PRODUCT_INTEL_82801DB_SMB: 112 case PCI_PRODUCT_INTEL_82801E_SMB: 113 case PCI_PRODUCT_INTEL_82801EB_SMB: 114 case PCI_PRODUCT_INTEL_82801FB_SMB: 115 case PCI_PRODUCT_INTEL_82801G_SMB: 116 case PCI_PRODUCT_INTEL_82801H_SMB: 117 case PCI_PRODUCT_INTEL_82801I_SMB: 118 case PCI_PRODUCT_INTEL_82801JD_SMB: 119 case PCI_PRODUCT_INTEL_82801JI_SMB: 120 case PCI_PRODUCT_INTEL_3400_SMB: 121 case PCI_PRODUCT_INTEL_6SERIES_SMB: 122 case PCI_PRODUCT_INTEL_7SERIES_SMB: 123 case PCI_PRODUCT_INTEL_8SERIES_SMB: 124 case PCI_PRODUCT_INTEL_9SERIES_SMB: 125 case PCI_PRODUCT_INTEL_100SERIES_SMB: 126 case PCI_PRODUCT_INTEL_100SERIES_LP_SMB: 127 case PCI_PRODUCT_INTEL_2HS_SMB: 128 case PCI_PRODUCT_INTEL_3HS_SMB: 129 case PCI_PRODUCT_INTEL_3HS_U_SMB: 130 case PCI_PRODUCT_INTEL_4HS_H_SMB: 131 case PCI_PRODUCT_INTEL_CORE4G_M_SMB: 132 case PCI_PRODUCT_INTEL_CORE5G_M_SMB: 133 case PCI_PRODUCT_INTEL_CMTLK_SMB: 134 case PCI_PRODUCT_INTEL_BAYTRAIL_PCU_SMB: 135 case PCI_PRODUCT_INTEL_BSW_PCU_SMB: 136 case PCI_PRODUCT_INTEL_APL_SMB: 137 case PCI_PRODUCT_INTEL_GLK_SMB: 138 case PCI_PRODUCT_INTEL_JSL_SMB: 139 case PCI_PRODUCT_INTEL_C600_SMBUS: 140 case PCI_PRODUCT_INTEL_C600_SMB_0: 141 case PCI_PRODUCT_INTEL_C600_SMB_1: 142 case PCI_PRODUCT_INTEL_C600_SMB_2: 143 case PCI_PRODUCT_INTEL_C610_SMB: 144 case PCI_PRODUCT_INTEL_C620_SMB: 145 case PCI_PRODUCT_INTEL_C620_SMB_S: 146 case PCI_PRODUCT_INTEL_EP80579_SMB: 147 case PCI_PRODUCT_INTEL_DH89XXCC_SMB: 148 case PCI_PRODUCT_INTEL_DH89XXCL_SMB: 149 case PCI_PRODUCT_INTEL_C2000_PCU_SMBUS: 150 case PCI_PRODUCT_INTEL_C3K_SMBUS_LEGACY: 151 case PCI_PRODUCT_INTEL_495_YU_SMB: 152 case PCI_PRODUCT_INTEL_5HS_LP_SMB: 153 return 1; 154 } 155 } 156 return 0; 157 } 158 159 static void 160 ichsmb_attach(device_t parent, device_t self, void *aux) 161 { 162 struct ichsmb_softc *sc = device_private(self); 163 struct pci_attach_args *pa = aux; 164 pcireg_t conf; 165 const char *intrstr = NULL; 166 char intrbuf[PCI_INTRSTR_LEN]; 167 168 sc->sc_dev = self; 169 sc->sc_pc = pa->pa_pc; 170 171 pci_aprint_devinfo(pa, NULL); 172 173 mutex_init(&sc->sc_exec_lock, MUTEX_DEFAULT, IPL_BIO); 174 cv_init(&sc->sc_exec_wait, device_xname(self)); 175 176 /* Read configuration */ 177 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 178 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 179 180 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 181 aprint_error_dev(self, "SMBus disabled\n"); 182 goto out; 183 } 184 185 /* Map I/O space */ 186 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 187 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_size)) { 188 aprint_error_dev(self, "can't map I/O space\n"); 189 goto out; 190 } 191 192 sc->sc_poll = 1; 193 sc->sc_ih = NULL; 194 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 195 /* No PCI IRQ */ 196 aprint_normal_dev(self, "interrupting at SMI\n"); 197 } else { 198 /* Install interrupt handler */ 199 if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0) == 0) { 200 intrstr = pci_intr_string(pa->pa_pc, sc->sc_pihp[0], 201 intrbuf, sizeof(intrbuf)); 202 pci_intr_setattr(pa->pa_pc, &sc->sc_pihp[0], 203 PCI_INTR_MPSAFE, true); 204 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, 205 sc->sc_pihp[0], IPL_BIO, ichsmb_intr, sc, 206 device_xname(sc->sc_dev)); 207 if (sc->sc_ih != NULL) { 208 aprint_normal_dev(self, "interrupting at %s\n", 209 intrstr); 210 sc->sc_poll = 0; 211 } else { 212 pci_intr_release(pa->pa_pc, sc->sc_pihp, 1); 213 sc->sc_pihp = NULL; 214 } 215 } 216 if (sc->sc_poll) 217 aprint_normal_dev(self, "polling\n"); 218 } 219 220 sc->sc_i2c_device = NULL; 221 ichsmb_rescan(self, NULL, NULL); 222 223 out: if (!pmf_device_register(self, NULL, NULL)) 224 aprint_error_dev(self, "couldn't establish power handler\n"); 225 } 226 227 static int 228 ichsmb_rescan(device_t self, const char *ifattr, const int *locators) 229 { 230 struct ichsmb_softc *sc = device_private(self); 231 struct i2cbus_attach_args iba; 232 233 if (sc->sc_i2c_device != NULL) 234 return 0; 235 236 /* Attach I2C bus */ 237 iic_tag_init(&sc->sc_i2c_tag); 238 sc->sc_i2c_tag.ic_cookie = sc; 239 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 240 241 memset(&iba, 0, sizeof(iba)); 242 iba.iba_tag = &sc->sc_i2c_tag; 243 sc->sc_i2c_device = config_found(self, &iba, iicbus_print, CFARGS_NONE); 244 245 return 0; 246 } 247 248 static int 249 ichsmb_detach(device_t self, int flags) 250 { 251 struct ichsmb_softc *sc = device_private(self); 252 int error; 253 254 if (sc->sc_i2c_device) { 255 error = config_detach(sc->sc_i2c_device, flags); 256 if (error) 257 return error; 258 } 259 260 iic_tag_fini(&sc->sc_i2c_tag); 261 262 if (sc->sc_ih) { 263 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 264 sc->sc_ih = NULL; 265 } 266 267 if (sc->sc_pihp) { 268 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 269 sc->sc_pihp = NULL; 270 } 271 272 if (sc->sc_size != 0) 273 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_size); 274 275 mutex_destroy(&sc->sc_exec_lock); 276 cv_destroy(&sc->sc_exec_wait); 277 278 return 0; 279 } 280 281 static void 282 ichsmb_chdet(device_t self, device_t child) 283 { 284 struct ichsmb_softc *sc = device_private(self); 285 286 if (sc->sc_i2c_device == child) 287 sc->sc_i2c_device = NULL; 288 } 289 290 static int 291 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 292 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 293 { 294 struct ichsmb_softc *sc = cookie; 295 const uint8_t *b; 296 uint8_t ctl = 0, st; 297 int retries; 298 char fbuf[64]; 299 300 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 301 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 302 len, flags)); 303 304 mutex_enter(&sc->sc_exec_lock); 305 306 /* Clear status bits */ 307 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 308 LPCIB_SMB_HS_INTR | LPCIB_SMB_HS_DEVERR | 309 LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED); 310 bus_space_barrier(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 1, 311 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 312 313 /* Wait for bus to be idle */ 314 for (retries = 100; retries > 0; retries--) { 315 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 316 if (!(st & LPCIB_SMB_HS_BUSY)) 317 break; 318 DELAY(ICHIIC_DELAY); 319 } 320 #ifdef ICHIIC_DEBUG 321 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 322 printf("%s: exec: st %s\n", device_xname(sc->sc_dev), fbuf); 323 #endif 324 if (st & LPCIB_SMB_HS_BUSY) { 325 mutex_exit(&sc->sc_exec_lock); 326 return (EBUSY); 327 } 328 329 if (sc->sc_poll) 330 flags |= I2C_F_POLL; 331 332 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 333 (cmdlen == 0 && len > 1)) { 334 mutex_exit(&sc->sc_exec_lock); 335 return (EINVAL); 336 } 337 338 /* Setup transfer */ 339 sc->sc_i2c_xfer.op = op; 340 sc->sc_i2c_xfer.buf = buf; 341 sc->sc_i2c_xfer.len = len; 342 sc->sc_i2c_xfer.flags = flags; 343 sc->sc_i2c_xfer.error = 0; 344 sc->sc_i2c_xfer.done = false; 345 346 /* Set slave address and transfer direction */ 347 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 348 LPCIB_SMB_TXSLVA_ADDR(addr) | 349 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 350 351 b = (const uint8_t *)cmdbuf; 352 if (cmdlen > 0) 353 /* Set command byte */ 354 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 355 356 if (I2C_OP_WRITE_P(op)) { 357 /* Write data */ 358 b = buf; 359 if (cmdlen == 0 && len == 1) 360 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 361 LPCIB_SMB_HCMD, b[0]); 362 else if (len > 0) 363 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 364 LPCIB_SMB_HD0, b[0]); 365 if (len > 1) 366 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 367 LPCIB_SMB_HD1, b[1]); 368 } 369 370 /* Set SMBus command */ 371 if (cmdlen == 0) { 372 if (len == 0) 373 ctl = LPCIB_SMB_HC_CMD_QUICK; 374 else 375 ctl = LPCIB_SMB_HC_CMD_BYTE; 376 } else if (len == 1) 377 ctl = LPCIB_SMB_HC_CMD_BDATA; 378 else if (len == 2) 379 ctl = LPCIB_SMB_HC_CMD_WDATA; 380 381 if ((flags & I2C_F_POLL) == 0) 382 ctl |= LPCIB_SMB_HC_INTREN; 383 384 /* Start transaction */ 385 ctl |= LPCIB_SMB_HC_START; 386 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 387 388 if (flags & I2C_F_POLL) { 389 /* Poll for completion */ 390 DELAY(ICHIIC_DELAY); 391 for (retries = 1000; retries > 0; retries--) { 392 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 393 LPCIB_SMB_HS); 394 if ((st & LPCIB_SMB_HS_BUSY) == 0) 395 break; 396 DELAY(ICHIIC_DELAY); 397 } 398 if (st & LPCIB_SMB_HS_BUSY) 399 goto timeout; 400 ichsmb_intr(sc); 401 } else { 402 /* Wait for interrupt */ 403 while (! sc->sc_i2c_xfer.done) { 404 if (cv_timedwait(&sc->sc_exec_wait, &sc->sc_exec_lock, 405 ICHIIC_TIMEOUT * hz)) 406 goto timeout; 407 } 408 } 409 410 int error = sc->sc_i2c_xfer.error; 411 mutex_exit(&sc->sc_exec_lock); 412 413 return (error); 414 415 timeout: 416 /* 417 * Transfer timeout. Kill the transaction and clear status bits. 418 */ 419 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 420 LPCIB_SMB_HC_KILL); 421 DELAY(ICHIIC_DELAY); 422 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 423 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 424 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 425 aprint_error_dev(sc->sc_dev, "abort failed, status %s\n", 426 fbuf); 427 } 428 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 429 mutex_exit(&sc->sc_exec_lock); 430 return (ETIMEDOUT); 431 } 432 433 static int 434 ichsmb_intr(void *arg) 435 { 436 struct ichsmb_softc *sc = arg; 437 uint8_t st; 438 uint8_t *b; 439 size_t len; 440 #ifdef ICHIIC_DEBUG 441 char fbuf[64]; 442 #endif 443 444 /* Read status */ 445 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 446 447 /* Clear status bits */ 448 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 449 450 /* XXX Ignore SMBALERT# for now */ 451 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 452 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 453 LPCIB_SMB_HS_BDONE)) == 0) 454 /* Interrupt was not for us */ 455 return (0); 456 457 #ifdef ICHIIC_DEBUG 458 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 459 printf("%s: intr st %s\n", device_xname(sc->sc_dev), fbuf); 460 #endif 461 462 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 463 mutex_enter(&sc->sc_exec_lock); 464 465 /* Check for errors */ 466 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 467 sc->sc_i2c_xfer.error = EIO; 468 goto done; 469 } 470 471 if (st & LPCIB_SMB_HS_INTR) { 472 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 473 goto done; 474 475 /* Read data */ 476 b = sc->sc_i2c_xfer.buf; 477 len = sc->sc_i2c_xfer.len; 478 if (len > 0) 479 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 480 LPCIB_SMB_HD0); 481 if (len > 1) 482 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 483 LPCIB_SMB_HD1); 484 } 485 486 done: 487 sc->sc_i2c_xfer.done = true; 488 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) { 489 cv_signal(&sc->sc_exec_wait); 490 mutex_exit(&sc->sc_exec_lock); 491 } 492 return (1); 493 } 494 495 MODULE(MODULE_CLASS_DRIVER, ichsmb, "pci,iic"); 496 497 #ifdef _MODULE 498 #include "ioconf.c" 499 #endif 500 501 static int 502 ichsmb_modcmd(modcmd_t cmd, void *opaque) 503 { 504 int error = 0; 505 506 switch (cmd) { 507 case MODULE_CMD_INIT: 508 #ifdef _MODULE 509 error = config_init_component(cfdriver_ioconf_ichsmb, 510 cfattach_ioconf_ichsmb, cfdata_ioconf_ichsmb); 511 #endif 512 break; 513 case MODULE_CMD_FINI: 514 #ifdef _MODULE 515 error = config_fini_component(cfdriver_ioconf_ichsmb, 516 cfattach_ioconf_ichsmb, cfdata_ioconf_ichsmb); 517 #endif 518 break; 519 default: 520 #ifdef _MODULE 521 error = ENOTTY; 522 #endif 523 break; 524 } 525 526 return error; 527 } 528
Indexes created Thu Oct 02 14:10:14 GMT 2025