ichsmb.c revision 1.74
1 /* $NetBSD: ichsmb.c,v 1.74 2021/10/12 14:15:34 msaitoh Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.44 2020/10/07 11:23:05 jsg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.74 2021/10/12 14:15:34 msaitoh Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/condvar.h> 33 #include <sys/module.h> 34 35 #include <sys/bus.h> 36 37 #include <dev/pci/pcidevs.h> 38 #include <dev/pci/pcireg.h> 39 #include <dev/pci/pcivar.h> 40 41 #include <dev/ic/i82801lpcreg.h> 42 43 #include <dev/i2c/i2cvar.h> 44 45 #ifdef ICHIIC_DEBUG 46 #define DPRINTF(x) printf x 47 #else 48 #define DPRINTF(x) 49 #endif 50 51 #define ICHIIC_DELAY 100 52 #define ICHIIC_TIMEOUT 1 53 54 struct ichsmb_softc { 55 device_t sc_dev; 56 57 bus_space_tag_t sc_iot; 58 bus_space_handle_t sc_ioh; 59 bus_size_t sc_size; 60 pci_chipset_tag_t sc_pc; 61 void * sc_ih; 62 int sc_poll; 63 pci_intr_handle_t *sc_pihp; 64 65 kmutex_t sc_exec_lock; 66 kcondvar_t sc_exec_wait; 67 68 struct i2c_controller sc_i2c_tag; 69 struct { 70 i2c_op_t op; 71 void * buf; 72 size_t len; 73 int flags; 74 int error; 75 bool done; 76 } sc_i2c_xfer; 77 device_t sc_i2c_device; 78 }; 79 80 static int ichsmb_match(device_t, cfdata_t, void *); 81 static void ichsmb_attach(device_t, device_t, void *); 82 static int ichsmb_detach(device_t, int); 83 static int ichsmb_rescan(device_t, const char *, const int *); 84 static void ichsmb_chdet(device_t, device_t); 85 86 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 87 size_t, void *, size_t, int); 88 89 static int ichsmb_intr(void *); 90 91 #include "ioconf.h" 92 93 CFATTACH_DECL3_NEW(ichsmb, sizeof(struct ichsmb_softc), 94 ichsmb_match, ichsmb_attach, ichsmb_detach, NULL, ichsmb_rescan, 95 ichsmb_chdet, DVF_DETACH_SHUTDOWN); 96 97 98 static int 99 ichsmb_match(device_t parent, cfdata_t match, void *aux) 100 { 101 struct pci_attach_args *pa = aux; 102 103 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 104 switch (PCI_PRODUCT(pa->pa_id)) { 105 case PCI_PRODUCT_INTEL_6300ESB_SMB: 106 case PCI_PRODUCT_INTEL_63XXESB_SMB: 107 case PCI_PRODUCT_INTEL_82801AA_SMB: 108 case PCI_PRODUCT_INTEL_82801AB_SMB: 109 case PCI_PRODUCT_INTEL_82801BA_SMB: 110 case PCI_PRODUCT_INTEL_82801CA_SMB: 111 case PCI_PRODUCT_INTEL_82801DB_SMB: 112 case PCI_PRODUCT_INTEL_82801E_SMB: 113 case PCI_PRODUCT_INTEL_82801EB_SMB: 114 case PCI_PRODUCT_INTEL_82801FB_SMB: 115 case PCI_PRODUCT_INTEL_82801G_SMB: 116 case PCI_PRODUCT_INTEL_82801H_SMB: 117 case PCI_PRODUCT_INTEL_82801I_SMB: 118 case PCI_PRODUCT_INTEL_82801JD_SMB: 119 case PCI_PRODUCT_INTEL_82801JI_SMB: 120 case PCI_PRODUCT_INTEL_3400_SMB: 121 case PCI_PRODUCT_INTEL_6SERIES_SMB: 122 case PCI_PRODUCT_INTEL_7SERIES_SMB: 123 case PCI_PRODUCT_INTEL_8SERIES_SMB: 124 case PCI_PRODUCT_INTEL_9SERIES_SMB: 125 case PCI_PRODUCT_INTEL_100SERIES_SMB: 126 case PCI_PRODUCT_INTEL_100SERIES_LP_SMB: 127 case PCI_PRODUCT_INTEL_2HS_SMB: 128 case PCI_PRODUCT_INTEL_3HS_SMB: 129 case PCI_PRODUCT_INTEL_3HS_U_SMB: 130 case PCI_PRODUCT_INTEL_4HS_H_SMB: 131 case PCI_PRODUCT_INTEL_4HS_V_SMB: 132 case PCI_PRODUCT_INTEL_CORE4G_M_SMB: 133 case PCI_PRODUCT_INTEL_CORE5G_M_SMB: 134 case PCI_PRODUCT_INTEL_CMTLK_SMB: 135 case PCI_PRODUCT_INTEL_BAYTRAIL_PCU_SMB: 136 case PCI_PRODUCT_INTEL_BSW_PCU_SMB: 137 case PCI_PRODUCT_INTEL_APL_SMB: 138 case PCI_PRODUCT_INTEL_GLK_SMB: 139 case PCI_PRODUCT_INTEL_JSL_SMB: 140 case PCI_PRODUCT_INTEL_C600_SMBUS: 141 case PCI_PRODUCT_INTEL_C600_SMB_0: 142 case PCI_PRODUCT_INTEL_C600_SMB_1: 143 case PCI_PRODUCT_INTEL_C600_SMB_2: 144 case PCI_PRODUCT_INTEL_C610_SMB: 145 case PCI_PRODUCT_INTEL_C620_SMB: 146 case PCI_PRODUCT_INTEL_C620_SMB_S: 147 case PCI_PRODUCT_INTEL_EP80579_SMB: 148 case PCI_PRODUCT_INTEL_DH89XXCC_SMB: 149 case PCI_PRODUCT_INTEL_DH89XXCL_SMB: 150 case PCI_PRODUCT_INTEL_C2000_PCU_SMBUS: 151 case PCI_PRODUCT_INTEL_C3K_SMBUS_LEGACY: 152 case PCI_PRODUCT_INTEL_495_YU_SMB: 153 case PCI_PRODUCT_INTEL_5HS_H_SMB: 154 case PCI_PRODUCT_INTEL_5HS_LP_SMB: 155 return 1; 156 } 157 } 158 return 0; 159 } 160 161 static void 162 ichsmb_attach(device_t parent, device_t self, void *aux) 163 { 164 struct ichsmb_softc *sc = device_private(self); 165 struct pci_attach_args *pa = aux; 166 pcireg_t conf; 167 const char *intrstr = NULL; 168 char intrbuf[PCI_INTRSTR_LEN]; 169 170 sc->sc_dev = self; 171 sc->sc_pc = pa->pa_pc; 172 173 pci_aprint_devinfo(pa, NULL); 174 175 mutex_init(&sc->sc_exec_lock, MUTEX_DEFAULT, IPL_BIO); 176 cv_init(&sc->sc_exec_wait, device_xname(self)); 177 178 /* Read configuration */ 179 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 180 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 181 182 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 183 aprint_error_dev(self, "SMBus disabled\n"); 184 goto out; 185 } 186 187 /* Map I/O space */ 188 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 189 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_size)) { 190 aprint_error_dev(self, "can't map I/O space\n"); 191 goto out; 192 } 193 194 sc->sc_poll = 1; 195 sc->sc_ih = NULL; 196 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 197 /* No PCI IRQ */ 198 aprint_normal_dev(self, "interrupting at SMI\n"); 199 } else { 200 /* Install interrupt handler */ 201 if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0) == 0) { 202 intrstr = pci_intr_string(pa->pa_pc, sc->sc_pihp[0], 203 intrbuf, sizeof(intrbuf)); 204 pci_intr_setattr(pa->pa_pc, &sc->sc_pihp[0], 205 PCI_INTR_MPSAFE, true); 206 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, 207 sc->sc_pihp[0], IPL_BIO, ichsmb_intr, sc, 208 device_xname(sc->sc_dev)); 209 if (sc->sc_ih != NULL) { 210 aprint_normal_dev(self, "interrupting at %s\n", 211 intrstr); 212 sc->sc_poll = 0; 213 } else { 214 pci_intr_release(pa->pa_pc, sc->sc_pihp, 1); 215 sc->sc_pihp = NULL; 216 } 217 } 218 if (sc->sc_poll) 219 aprint_normal_dev(self, "polling\n"); 220 } 221 222 sc->sc_i2c_device = NULL; 223 ichsmb_rescan(self, NULL, NULL); 224 225 out: if (!pmf_device_register(self, NULL, NULL)) 226 aprint_error_dev(self, "couldn't establish power handler\n"); 227 } 228 229 static int 230 ichsmb_rescan(device_t self, const char *ifattr, const int *locators) 231 { 232 struct ichsmb_softc *sc = device_private(self); 233 struct i2cbus_attach_args iba; 234 235 if (sc->sc_i2c_device != NULL) 236 return 0; 237 238 /* Attach I2C bus */ 239 iic_tag_init(&sc->sc_i2c_tag); 240 sc->sc_i2c_tag.ic_cookie = sc; 241 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 242 243 memset(&iba, 0, sizeof(iba)); 244 iba.iba_tag = &sc->sc_i2c_tag; 245 sc->sc_i2c_device = config_found(self, &iba, iicbus_print, CFARGS_NONE); 246 247 return 0; 248 } 249 250 static int 251 ichsmb_detach(device_t self, int flags) 252 { 253 struct ichsmb_softc *sc = device_private(self); 254 int error; 255 256 if (sc->sc_i2c_device) { 257 error = config_detach(sc->sc_i2c_device, flags); 258 if (error) 259 return error; 260 } 261 262 iic_tag_fini(&sc->sc_i2c_tag); 263 264 if (sc->sc_ih) { 265 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 266 sc->sc_ih = NULL; 267 } 268 269 if (sc->sc_pihp) { 270 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 271 sc->sc_pihp = NULL; 272 } 273 274 if (sc->sc_size != 0) 275 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_size); 276 277 mutex_destroy(&sc->sc_exec_lock); 278 cv_destroy(&sc->sc_exec_wait); 279 280 return 0; 281 } 282 283 static void 284 ichsmb_chdet(device_t self, device_t child) 285 { 286 struct ichsmb_softc *sc = device_private(self); 287 288 if (sc->sc_i2c_device == child) 289 sc->sc_i2c_device = NULL; 290 } 291 292 static int 293 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 294 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 295 { 296 struct ichsmb_softc *sc = cookie; 297 const uint8_t *b; 298 uint8_t ctl = 0, st; 299 int retries; 300 char fbuf[64]; 301 302 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 303 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 304 len, flags)); 305 306 mutex_enter(&sc->sc_exec_lock); 307 308 /* Clear status bits */ 309 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 310 LPCIB_SMB_HS_INTR | LPCIB_SMB_HS_DEVERR | 311 LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED); 312 bus_space_barrier(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 1, 313 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 314 315 /* Wait for bus to be idle */ 316 for (retries = 100; retries > 0; retries--) { 317 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 318 if (!(st & LPCIB_SMB_HS_BUSY)) 319 break; 320 DELAY(ICHIIC_DELAY); 321 } 322 #ifdef ICHIIC_DEBUG 323 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 324 printf("%s: exec: st %s\n", device_xname(sc->sc_dev), fbuf); 325 #endif 326 if (st & LPCIB_SMB_HS_BUSY) { 327 mutex_exit(&sc->sc_exec_lock); 328 return (EBUSY); 329 } 330 331 if (sc->sc_poll) 332 flags |= I2C_F_POLL; 333 334 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 335 (cmdlen == 0 && len > 1)) { 336 mutex_exit(&sc->sc_exec_lock); 337 return (EINVAL); 338 } 339 340 /* Setup transfer */ 341 sc->sc_i2c_xfer.op = op; 342 sc->sc_i2c_xfer.buf = buf; 343 sc->sc_i2c_xfer.len = len; 344 sc->sc_i2c_xfer.flags = flags; 345 sc->sc_i2c_xfer.error = 0; 346 sc->sc_i2c_xfer.done = false; 347 348 /* Set slave address and transfer direction */ 349 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 350 LPCIB_SMB_TXSLVA_ADDR(addr) | 351 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 352 353 b = (const uint8_t *)cmdbuf; 354 if (cmdlen > 0) 355 /* Set command byte */ 356 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 357 358 if (I2C_OP_WRITE_P(op)) { 359 /* Write data */ 360 b = buf; 361 if (cmdlen == 0 && len == 1) 362 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 363 LPCIB_SMB_HCMD, b[0]); 364 else if (len > 0) 365 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 366 LPCIB_SMB_HD0, b[0]); 367 if (len > 1) 368 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 369 LPCIB_SMB_HD1, b[1]); 370 } 371 372 /* Set SMBus command */ 373 if (cmdlen == 0) { 374 if (len == 0) 375 ctl = LPCIB_SMB_HC_CMD_QUICK; 376 else 377 ctl = LPCIB_SMB_HC_CMD_BYTE; 378 } else if (len == 1) 379 ctl = LPCIB_SMB_HC_CMD_BDATA; 380 else if (len == 2) 381 ctl = LPCIB_SMB_HC_CMD_WDATA; 382 383 if ((flags & I2C_F_POLL) == 0) 384 ctl |= LPCIB_SMB_HC_INTREN; 385 386 /* Start transaction */ 387 ctl |= LPCIB_SMB_HC_START; 388 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 389 390 if (flags & I2C_F_POLL) { 391 /* Poll for completion */ 392 DELAY(ICHIIC_DELAY); 393 for (retries = 1000; retries > 0; retries--) { 394 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 395 LPCIB_SMB_HS); 396 if ((st & LPCIB_SMB_HS_BUSY) == 0) 397 break; 398 DELAY(ICHIIC_DELAY); 399 } 400 if (st & LPCIB_SMB_HS_BUSY) 401 goto timeout; 402 ichsmb_intr(sc); 403 } else { 404 /* Wait for interrupt */ 405 while (! sc->sc_i2c_xfer.done) { 406 if (cv_timedwait(&sc->sc_exec_wait, &sc->sc_exec_lock, 407 ICHIIC_TIMEOUT * hz)) 408 goto timeout; 409 } 410 } 411 412 int error = sc->sc_i2c_xfer.error; 413 mutex_exit(&sc->sc_exec_lock); 414 415 return (error); 416 417 timeout: 418 /* 419 * Transfer timeout. Kill the transaction and clear status bits. 420 */ 421 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 422 LPCIB_SMB_HC_KILL); 423 DELAY(ICHIIC_DELAY); 424 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 425 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 426 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 427 aprint_error_dev(sc->sc_dev, "abort failed, status %s\n", 428 fbuf); 429 } 430 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 431 mutex_exit(&sc->sc_exec_lock); 432 return (ETIMEDOUT); 433 } 434 435 static int 436 ichsmb_intr(void *arg) 437 { 438 struct ichsmb_softc *sc = arg; 439 uint8_t st; 440 uint8_t *b; 441 size_t len; 442 #ifdef ICHIIC_DEBUG 443 char fbuf[64]; 444 #endif 445 446 /* Read status */ 447 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 448 449 /* Clear status bits */ 450 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 451 452 /* XXX Ignore SMBALERT# for now */ 453 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 454 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 455 LPCIB_SMB_HS_BDONE)) == 0) 456 /* Interrupt was not for us */ 457 return (0); 458 459 #ifdef ICHIIC_DEBUG 460 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 461 printf("%s: intr st %s\n", device_xname(sc->sc_dev), fbuf); 462 #endif 463 464 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 465 mutex_enter(&sc->sc_exec_lock); 466 467 /* Check for errors */ 468 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 469 sc->sc_i2c_xfer.error = EIO; 470 goto done; 471 } 472 473 if (st & LPCIB_SMB_HS_INTR) { 474 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 475 goto done; 476 477 /* Read data */ 478 b = sc->sc_i2c_xfer.buf; 479 len = sc->sc_i2c_xfer.len; 480 if (len > 0) 481 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 482 LPCIB_SMB_HD0); 483 if (len > 1) 484 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 485 LPCIB_SMB_HD1); 486 } 487 488 done: 489 sc->sc_i2c_xfer.done = true; 490 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) { 491 cv_signal(&sc->sc_exec_wait); 492 mutex_exit(&sc->sc_exec_lock); 493 } 494 return (1); 495 } 496 497 MODULE(MODULE_CLASS_DRIVER, ichsmb, "pci,iic"); 498 499 #ifdef _MODULE 500 #include "ioconf.c" 501 #endif 502 503 static int 504 ichsmb_modcmd(modcmd_t cmd, void *opaque) 505 { 506 int error = 0; 507 508 switch (cmd) { 509 case MODULE_CMD_INIT: 510 #ifdef _MODULE 511 error = config_init_component(cfdriver_ioconf_ichsmb, 512 cfattach_ioconf_ichsmb, cfdata_ioconf_ichsmb); 513 #endif 514 break; 515 case MODULE_CMD_FINI: 516 #ifdef _MODULE 517 error = config_fini_component(cfdriver_ioconf_ichsmb, 518 cfattach_ioconf_ichsmb, cfdata_ioconf_ichsmb); 519 #endif 520 break; 521 default: 522 #ifdef _MODULE 523 error = ENOTTY; 524 #endif 525 break; 526 } 527 528 return error; 529 } 530
Indexes created Thu Oct 02 14:10:14 GMT 2025