ichsmb.c revision 1.76
1 /* $NetBSD: ichsmb.c,v 1.76 2022/01/25 16:07:57 msaitoh Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.44 2020/10/07 11:23:05 jsg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.76 2022/01/25 16:07:57 msaitoh Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/condvar.h> 33 #include <sys/module.h> 34 35 #include <sys/bus.h> 36 37 #include <dev/pci/pcidevs.h> 38 #include <dev/pci/pcireg.h> 39 #include <dev/pci/pcivar.h> 40 41 #include <dev/ic/i82801lpcreg.h> 42 43 #include <dev/i2c/i2cvar.h> 44 45 #ifdef ICHIIC_DEBUG 46 #define DPRINTF(x) printf x 47 #else 48 #define DPRINTF(x) 49 #endif 50 51 #define ICHIIC_DELAY 100 52 #define ICHIIC_TIMEOUT 1 53 54 struct ichsmb_softc { 55 device_t sc_dev; 56 57 bus_space_tag_t sc_iot; 58 bus_space_handle_t sc_ioh; 59 bus_size_t sc_size; 60 pci_chipset_tag_t sc_pc; 61 void * sc_ih; 62 int sc_poll; 63 pci_intr_handle_t *sc_pihp; 64 65 kmutex_t sc_exec_lock; 66 kcondvar_t sc_exec_wait; 67 68 struct i2c_controller sc_i2c_tag; 69 struct { 70 i2c_op_t op; 71 void * buf; 72 size_t len; 73 int flags; 74 int error; 75 bool done; 76 } sc_i2c_xfer; 77 device_t sc_i2c_device; 78 }; 79 80 static int ichsmb_match(device_t, cfdata_t, void *); 81 static void ichsmb_attach(device_t, device_t, void *); 82 static int ichsmb_detach(device_t, int); 83 static int ichsmb_rescan(device_t, const char *, const int *); 84 static void ichsmb_chdet(device_t, device_t); 85 86 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 87 size_t, void *, size_t, int); 88 89 static int ichsmb_intr(void *); 90 91 #include "ioconf.h" 92 93 CFATTACH_DECL3_NEW(ichsmb, sizeof(struct ichsmb_softc), 94 ichsmb_match, ichsmb_attach, ichsmb_detach, NULL, ichsmb_rescan, 95 ichsmb_chdet, DVF_DETACH_SHUTDOWN); 96 97 98 static int 99 ichsmb_match(device_t parent, cfdata_t match, void *aux) 100 { 101 struct pci_attach_args *pa = aux; 102 103 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 104 switch (PCI_PRODUCT(pa->pa_id)) { 105 case PCI_PRODUCT_INTEL_6300ESB_SMB: 106 case PCI_PRODUCT_INTEL_63XXESB_SMB: 107 case PCI_PRODUCT_INTEL_82801AA_SMB: 108 case PCI_PRODUCT_INTEL_82801AB_SMB: 109 case PCI_PRODUCT_INTEL_82801BA_SMB: 110 case PCI_PRODUCT_INTEL_82801CA_SMB: 111 case PCI_PRODUCT_INTEL_82801DB_SMB: 112 case PCI_PRODUCT_INTEL_82801E_SMB: 113 case PCI_PRODUCT_INTEL_82801EB_SMB: 114 case PCI_PRODUCT_INTEL_82801FB_SMB: 115 case PCI_PRODUCT_INTEL_82801G_SMB: 116 case PCI_PRODUCT_INTEL_82801H_SMB: 117 case PCI_PRODUCT_INTEL_82801I_SMB: 118 case PCI_PRODUCT_INTEL_82801JD_SMB: 119 case PCI_PRODUCT_INTEL_82801JI_SMB: 120 case PCI_PRODUCT_INTEL_3400_SMB: 121 case PCI_PRODUCT_INTEL_6SERIES_SMB: 122 case PCI_PRODUCT_INTEL_7SERIES_SMB: 123 case PCI_PRODUCT_INTEL_8SERIES_SMB: 124 case PCI_PRODUCT_INTEL_9SERIES_SMB: 125 case PCI_PRODUCT_INTEL_100SERIES_SMB: 126 case PCI_PRODUCT_INTEL_100SERIES_LP_SMB: 127 case PCI_PRODUCT_INTEL_2HS_SMB: 128 case PCI_PRODUCT_INTEL_3HS_SMB: 129 case PCI_PRODUCT_INTEL_3HS_U_SMB: 130 case PCI_PRODUCT_INTEL_4HS_H_SMB: 131 case PCI_PRODUCT_INTEL_4HS_V_SMB: 132 case PCI_PRODUCT_INTEL_CORE4G_M_SMB: 133 case PCI_PRODUCT_INTEL_CORE5G_M_SMB: 134 case PCI_PRODUCT_INTEL_CMTLK_SMB: 135 case PCI_PRODUCT_INTEL_BAYTRAIL_PCU_SMB: 136 case PCI_PRODUCT_INTEL_BSW_PCU_SMB: 137 case PCI_PRODUCT_INTEL_APL_SMB: 138 case PCI_PRODUCT_INTEL_GLK_SMB: 139 case PCI_PRODUCT_INTEL_EHL_SMB: 140 case PCI_PRODUCT_INTEL_JSL_SMB: 141 case PCI_PRODUCT_INTEL_C600_SMBUS: 142 case PCI_PRODUCT_INTEL_C600_SMB_0: 143 case PCI_PRODUCT_INTEL_C600_SMB_1: 144 case PCI_PRODUCT_INTEL_C600_SMB_2: 145 case PCI_PRODUCT_INTEL_C610_SMB: 146 case PCI_PRODUCT_INTEL_C620_SMB: 147 case PCI_PRODUCT_INTEL_C620_SMB_S: 148 case PCI_PRODUCT_INTEL_EP80579_SMB: 149 case PCI_PRODUCT_INTEL_DH89XXCC_SMB: 150 case PCI_PRODUCT_INTEL_DH89XXCL_SMB: 151 case PCI_PRODUCT_INTEL_C2000_PCU_SMBUS: 152 case PCI_PRODUCT_INTEL_C3K_SMBUS_LEGACY: 153 case PCI_PRODUCT_INTEL_495_YU_SMB: 154 case PCI_PRODUCT_INTEL_5HS_H_SMB: 155 case PCI_PRODUCT_INTEL_5HS_LP_SMB: 156 case PCI_PRODUCT_INTEL_6HS_H_SMB: 157 return 1; 158 } 159 } 160 return 0; 161 } 162 163 static void 164 ichsmb_attach(device_t parent, device_t self, void *aux) 165 { 166 struct ichsmb_softc *sc = device_private(self); 167 struct pci_attach_args *pa = aux; 168 pcireg_t conf; 169 const char *intrstr = NULL; 170 char intrbuf[PCI_INTRSTR_LEN]; 171 172 sc->sc_dev = self; 173 sc->sc_pc = pa->pa_pc; 174 175 pci_aprint_devinfo(pa, NULL); 176 177 mutex_init(&sc->sc_exec_lock, MUTEX_DEFAULT, IPL_BIO); 178 cv_init(&sc->sc_exec_wait, device_xname(self)); 179 180 /* Read configuration */ 181 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 182 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 183 184 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 185 aprint_error_dev(self, "SMBus disabled\n"); 186 goto out; 187 } 188 189 /* Map I/O space */ 190 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 191 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_size)) { 192 aprint_error_dev(self, "can't map I/O space\n"); 193 goto out; 194 } 195 196 sc->sc_poll = 1; 197 sc->sc_ih = NULL; 198 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 199 /* No PCI IRQ */ 200 aprint_normal_dev(self, "interrupting at SMI\n"); 201 } else { 202 /* Install interrupt handler */ 203 if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0) == 0) { 204 intrstr = pci_intr_string(pa->pa_pc, sc->sc_pihp[0], 205 intrbuf, sizeof(intrbuf)); 206 pci_intr_setattr(pa->pa_pc, &sc->sc_pihp[0], 207 PCI_INTR_MPSAFE, true); 208 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, 209 sc->sc_pihp[0], IPL_BIO, ichsmb_intr, sc, 210 device_xname(sc->sc_dev)); 211 if (sc->sc_ih != NULL) { 212 aprint_normal_dev(self, "interrupting at %s\n", 213 intrstr); 214 sc->sc_poll = 0; 215 } else { 216 pci_intr_release(pa->pa_pc, sc->sc_pihp, 1); 217 sc->sc_pihp = NULL; 218 } 219 } 220 if (sc->sc_poll) 221 aprint_normal_dev(self, "polling\n"); 222 } 223 224 sc->sc_i2c_device = NULL; 225 ichsmb_rescan(self, NULL, NULL); 226 227 out: if (!pmf_device_register(self, NULL, NULL)) 228 aprint_error_dev(self, "couldn't establish power handler\n"); 229 } 230 231 static int 232 ichsmb_rescan(device_t self, const char *ifattr, const int *locators) 233 { 234 struct ichsmb_softc *sc = device_private(self); 235 struct i2cbus_attach_args iba; 236 237 if (sc->sc_i2c_device != NULL) 238 return 0; 239 240 /* Attach I2C bus */ 241 iic_tag_init(&sc->sc_i2c_tag); 242 sc->sc_i2c_tag.ic_cookie = sc; 243 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 244 245 memset(&iba, 0, sizeof(iba)); 246 iba.iba_tag = &sc->sc_i2c_tag; 247 sc->sc_i2c_device = config_found(self, &iba, iicbus_print, CFARGS_NONE); 248 249 return 0; 250 } 251 252 static int 253 ichsmb_detach(device_t self, int flags) 254 { 255 struct ichsmb_softc *sc = device_private(self); 256 int error; 257 258 if (sc->sc_i2c_device) { 259 error = config_detach(sc->sc_i2c_device, flags); 260 if (error) 261 return error; 262 } 263 264 iic_tag_fini(&sc->sc_i2c_tag); 265 266 if (sc->sc_ih) { 267 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 268 sc->sc_ih = NULL; 269 } 270 271 if (sc->sc_pihp) { 272 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 273 sc->sc_pihp = NULL; 274 } 275 276 if (sc->sc_size != 0) 277 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_size); 278 279 mutex_destroy(&sc->sc_exec_lock); 280 cv_destroy(&sc->sc_exec_wait); 281 282 return 0; 283 } 284 285 static void 286 ichsmb_chdet(device_t self, device_t child) 287 { 288 struct ichsmb_softc *sc = device_private(self); 289 290 if (sc->sc_i2c_device == child) 291 sc->sc_i2c_device = NULL; 292 } 293 294 static int 295 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 296 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 297 { 298 struct ichsmb_softc *sc = cookie; 299 const uint8_t *b; 300 uint8_t ctl = 0, st; 301 int retries; 302 char fbuf[64]; 303 304 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 305 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 306 len, flags)); 307 308 mutex_enter(&sc->sc_exec_lock); 309 310 /* Clear status bits */ 311 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 312 LPCIB_SMB_HS_INTR | LPCIB_SMB_HS_DEVERR | 313 LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED); 314 bus_space_barrier(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 1, 315 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 316 317 /* Wait for bus to be idle */ 318 for (retries = 100; retries > 0; retries--) { 319 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 320 if (!(st & LPCIB_SMB_HS_BUSY)) 321 break; 322 DELAY(ICHIIC_DELAY); 323 } 324 #ifdef ICHIIC_DEBUG 325 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 326 printf("%s: exec: st %s\n", device_xname(sc->sc_dev), fbuf); 327 #endif 328 if (st & LPCIB_SMB_HS_BUSY) { 329 mutex_exit(&sc->sc_exec_lock); 330 return (EBUSY); 331 } 332 333 if (sc->sc_poll) 334 flags |= I2C_F_POLL; 335 336 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 337 (cmdlen == 0 && len > 1)) { 338 mutex_exit(&sc->sc_exec_lock); 339 return (EINVAL); 340 } 341 342 /* Setup transfer */ 343 sc->sc_i2c_xfer.op = op; 344 sc->sc_i2c_xfer.buf = buf; 345 sc->sc_i2c_xfer.len = len; 346 sc->sc_i2c_xfer.flags = flags; 347 sc->sc_i2c_xfer.error = 0; 348 sc->sc_i2c_xfer.done = false; 349 350 /* Set slave address and transfer direction */ 351 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 352 LPCIB_SMB_TXSLVA_ADDR(addr) | 353 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 354 355 b = (const uint8_t *)cmdbuf; 356 if (cmdlen > 0) 357 /* Set command byte */ 358 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 359 360 if (I2C_OP_WRITE_P(op)) { 361 /* Write data */ 362 b = buf; 363 if (cmdlen == 0 && len == 1) 364 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 365 LPCIB_SMB_HCMD, b[0]); 366 else if (len > 0) 367 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 368 LPCIB_SMB_HD0, b[0]); 369 if (len > 1) 370 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 371 LPCIB_SMB_HD1, b[1]); 372 } 373 374 /* Set SMBus command */ 375 if (cmdlen == 0) { 376 if (len == 0) 377 ctl = LPCIB_SMB_HC_CMD_QUICK; 378 else 379 ctl = LPCIB_SMB_HC_CMD_BYTE; 380 } else if (len == 1) 381 ctl = LPCIB_SMB_HC_CMD_BDATA; 382 else if (len == 2) 383 ctl = LPCIB_SMB_HC_CMD_WDATA; 384 385 if ((flags & I2C_F_POLL) == 0) 386 ctl |= LPCIB_SMB_HC_INTREN; 387 388 /* Start transaction */ 389 ctl |= LPCIB_SMB_HC_START; 390 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 391 392 if (flags & I2C_F_POLL) { 393 /* Poll for completion */ 394 DELAY(ICHIIC_DELAY); 395 for (retries = 1000; retries > 0; retries--) { 396 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 397 LPCIB_SMB_HS); 398 if ((st & LPCIB_SMB_HS_BUSY) == 0) 399 break; 400 DELAY(ICHIIC_DELAY); 401 } 402 if (st & LPCIB_SMB_HS_BUSY) 403 goto timeout; 404 ichsmb_intr(sc); 405 } else { 406 /* Wait for interrupt */ 407 while (! sc->sc_i2c_xfer.done) { 408 if (cv_timedwait(&sc->sc_exec_wait, &sc->sc_exec_lock, 409 ICHIIC_TIMEOUT * hz)) 410 goto timeout; 411 } 412 } 413 414 int error = sc->sc_i2c_xfer.error; 415 mutex_exit(&sc->sc_exec_lock); 416 417 return (error); 418 419 timeout: 420 /* 421 * Transfer timeout. Kill the transaction and clear status bits. 422 */ 423 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 424 LPCIB_SMB_HC_KILL); 425 DELAY(ICHIIC_DELAY); 426 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 427 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 428 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 429 aprint_error_dev(sc->sc_dev, "abort failed, status %s\n", 430 fbuf); 431 } 432 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 433 mutex_exit(&sc->sc_exec_lock); 434 return (ETIMEDOUT); 435 } 436 437 static int 438 ichsmb_intr(void *arg) 439 { 440 struct ichsmb_softc *sc = arg; 441 uint8_t st; 442 uint8_t *b; 443 size_t len; 444 #ifdef ICHIIC_DEBUG 445 char fbuf[64]; 446 #endif 447 448 /* Read status */ 449 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 450 451 /* Clear status bits */ 452 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 453 454 /* XXX Ignore SMBALERT# for now */ 455 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 456 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 457 LPCIB_SMB_HS_BDONE)) == 0) 458 /* Interrupt was not for us */ 459 return (0); 460 461 #ifdef ICHIIC_DEBUG 462 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 463 printf("%s: intr st %s\n", device_xname(sc->sc_dev), fbuf); 464 #endif 465 466 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 467 mutex_enter(&sc->sc_exec_lock); 468 469 /* Check for errors */ 470 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 471 sc->sc_i2c_xfer.error = EIO; 472 goto done; 473 } 474 475 if (st & LPCIB_SMB_HS_INTR) { 476 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 477 goto done; 478 479 /* Read data */ 480 b = sc->sc_i2c_xfer.buf; 481 len = sc->sc_i2c_xfer.len; 482 if (len > 0) 483 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 484 LPCIB_SMB_HD0); 485 if (len > 1) 486 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 487 LPCIB_SMB_HD1); 488 } 489 490 done: 491 sc->sc_i2c_xfer.done = true; 492 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) { 493 cv_signal(&sc->sc_exec_wait); 494 mutex_exit(&sc->sc_exec_lock); 495 } 496 return (1); 497 } 498 499 MODULE(MODULE_CLASS_DRIVER, ichsmb, "pci,iic"); 500 501 #ifdef _MODULE 502 #include "ioconf.c" 503 #endif 504 505 static int 506 ichsmb_modcmd(modcmd_t cmd, void *opaque) 507 { 508 int error = 0; 509 510 switch (cmd) { 511 case MODULE_CMD_INIT: 512 #ifdef _MODULE 513 error = config_init_component(cfdriver_ioconf_ichsmb, 514 cfattach_ioconf_ichsmb, cfdata_ioconf_ichsmb); 515 #endif 516 break; 517 case MODULE_CMD_FINI: 518 #ifdef _MODULE 519 error = config_fini_component(cfdriver_ioconf_ichsmb, 520 cfattach_ioconf_ichsmb, cfdata_ioconf_ichsmb); 521 #endif 522 break; 523 default: 524 #ifdef _MODULE 525 error = ENOTTY; 526 #endif 527 break; 528 } 529 530 return error; 531 } 532
Indexes created Thu Oct 02 14:10:14 GMT 2025