ichsmb.c revision 1.81
1 /* $NetBSD: ichsmb.c,v 1.81 2022/09/22 14:45:33 riastradh Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.44 2020/10/07 11:23:05 jsg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.81 2022/09/22 14:45:33 riastradh Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/condvar.h> 33 #include <sys/module.h> 34 35 #include <sys/bus.h> 36 37 #include <dev/pci/pcidevs.h> 38 #include <dev/pci/pcireg.h> 39 #include <dev/pci/pcivar.h> 40 41 #include <dev/ic/i82801lpcreg.h> 42 43 #include <dev/i2c/i2cvar.h> 44 45 #ifdef ICHIIC_DEBUG 46 #define DPRINTF(x) printf x 47 #else 48 #define DPRINTF(x) 49 #endif 50 51 #define ICHIIC_DELAY 100 52 #define ICHIIC_TIMEOUT 1 53 54 struct ichsmb_softc { 55 device_t sc_dev; 56 57 bus_space_tag_t sc_iot; 58 bus_space_handle_t sc_ioh; 59 bus_size_t sc_size; 60 pci_chipset_tag_t sc_pc; 61 void * sc_ih; 62 int sc_poll; 63 pci_intr_handle_t *sc_pihp; 64 65 kmutex_t sc_exec_lock; 66 kcondvar_t sc_exec_wait; 67 68 struct i2c_controller sc_i2c_tag; 69 struct { 70 i2c_op_t op; 71 void * buf; 72 size_t len; 73 int flags; 74 int error; 75 bool done; 76 } sc_i2c_xfer; 77 device_t sc_i2c_device; 78 }; 79 80 static int ichsmb_match(device_t, cfdata_t, void *); 81 static void ichsmb_attach(device_t, device_t, void *); 82 static int ichsmb_detach(device_t, int); 83 static int ichsmb_rescan(device_t, const char *, const int *); 84 static void ichsmb_chdet(device_t, device_t); 85 86 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 87 size_t, void *, size_t, int); 88 89 static int ichsmb_intr(void *); 90 91 #include "ioconf.h" 92 93 CFATTACH_DECL3_NEW(ichsmb, sizeof(struct ichsmb_softc), 94 ichsmb_match, ichsmb_attach, ichsmb_detach, NULL, ichsmb_rescan, 95 ichsmb_chdet, DVF_DETACH_SHUTDOWN); 96 97 98 static int 99 ichsmb_match(device_t parent, cfdata_t match, void *aux) 100 { 101 struct pci_attach_args *pa = aux; 102 103 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 104 switch (PCI_PRODUCT(pa->pa_id)) { 105 case PCI_PRODUCT_INTEL_6300ESB_SMB: 106 case PCI_PRODUCT_INTEL_63XXESB_SMB: 107 case PCI_PRODUCT_INTEL_82801AA_SMB: 108 case PCI_PRODUCT_INTEL_82801AB_SMB: 109 case PCI_PRODUCT_INTEL_82801BA_SMB: 110 case PCI_PRODUCT_INTEL_82801CA_SMB: 111 case PCI_PRODUCT_INTEL_82801DB_SMB: 112 case PCI_PRODUCT_INTEL_82801E_SMB: 113 case PCI_PRODUCT_INTEL_82801EB_SMB: 114 case PCI_PRODUCT_INTEL_82801FB_SMB: 115 case PCI_PRODUCT_INTEL_82801G_SMB: 116 case PCI_PRODUCT_INTEL_82801H_SMB: 117 case PCI_PRODUCT_INTEL_82801I_SMB: 118 case PCI_PRODUCT_INTEL_82801JD_SMB: 119 case PCI_PRODUCT_INTEL_82801JI_SMB: 120 case PCI_PRODUCT_INTEL_3400_SMB: 121 case PCI_PRODUCT_INTEL_6SERIES_SMB: 122 case PCI_PRODUCT_INTEL_7SERIES_SMB: 123 case PCI_PRODUCT_INTEL_8SERIES_SMB: 124 case PCI_PRODUCT_INTEL_9SERIES_SMB: 125 case PCI_PRODUCT_INTEL_100SERIES_SMB: 126 case PCI_PRODUCT_INTEL_100SERIES_LP_SMB: 127 case PCI_PRODUCT_INTEL_2HS_SMB: 128 case PCI_PRODUCT_INTEL_3HS_SMB: 129 case PCI_PRODUCT_INTEL_3HS_U_SMB: 130 case PCI_PRODUCT_INTEL_4HS_H_SMB: 131 case PCI_PRODUCT_INTEL_4HS_V_SMB: 132 case PCI_PRODUCT_INTEL_CORE4G_M_SMB: 133 case PCI_PRODUCT_INTEL_CORE5G_M_SMB: 134 case PCI_PRODUCT_INTEL_CMTLK_SMB: 135 case PCI_PRODUCT_INTEL_BAYTRAIL_PCU_SMB: 136 case PCI_PRODUCT_INTEL_BSW_PCU_SMB: 137 case PCI_PRODUCT_INTEL_APL_SMB: 138 case PCI_PRODUCT_INTEL_GLK_SMB: 139 case PCI_PRODUCT_INTEL_EHL_SMB: 140 case PCI_PRODUCT_INTEL_JSL_SMB: 141 case PCI_PRODUCT_INTEL_C600_SMBUS: 142 case PCI_PRODUCT_INTEL_C600_SMB_0: 143 case PCI_PRODUCT_INTEL_C600_SMB_1: 144 case PCI_PRODUCT_INTEL_C600_SMB_2: 145 case PCI_PRODUCT_INTEL_C610_SMB: 146 case PCI_PRODUCT_INTEL_C620_SMB: 147 case PCI_PRODUCT_INTEL_C620_SMB_S: 148 case PCI_PRODUCT_INTEL_EP80579_SMB: 149 case PCI_PRODUCT_INTEL_DH89XXCC_SMB: 150 case PCI_PRODUCT_INTEL_DH89XXCL_SMB: 151 case PCI_PRODUCT_INTEL_C2000_PCU_SMBUS: 152 case PCI_PRODUCT_INTEL_C3K_SMBUS_LEGACY: 153 case PCI_PRODUCT_INTEL_495_YU_SMB: 154 case PCI_PRODUCT_INTEL_5HS_H_SMB: 155 case PCI_PRODUCT_INTEL_5HS_LP_SMB: 156 case PCI_PRODUCT_INTEL_6HS_H_SMB: 157 case PCI_PRODUCT_INTEL_6HS_LP_SMB: 158 return 1; 159 } 160 } 161 return 0; 162 } 163 164 static void 165 ichsmb_attach(device_t parent, device_t self, void *aux) 166 { 167 struct ichsmb_softc *sc = device_private(self); 168 struct pci_attach_args *pa = aux; 169 pcireg_t conf; 170 const char *intrstr = NULL; 171 char intrbuf[PCI_INTRSTR_LEN]; 172 173 sc->sc_dev = self; 174 sc->sc_pc = pa->pa_pc; 175 176 pci_aprint_devinfo(pa, NULL); 177 178 mutex_init(&sc->sc_exec_lock, MUTEX_DEFAULT, IPL_BIO); 179 cv_init(&sc->sc_exec_wait, device_xname(self)); 180 181 /* Read configuration */ 182 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, SMB_HOSTC); 183 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 184 185 if ((conf & SMB_HOSTC_HSTEN) == 0) { 186 aprint_error_dev(self, "SMBus disabled\n"); 187 goto out; 188 } 189 190 /* Map I/O space */ 191 if (pci_mapreg_map(pa, SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 192 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_size)) { 193 aprint_error_dev(self, "can't map I/O space\n"); 194 goto out; 195 } 196 197 sc->sc_poll = 1; 198 sc->sc_ih = NULL; 199 if (conf & SMB_HOSTC_SMIEN) { 200 /* No PCI IRQ */ 201 aprint_normal_dev(self, "interrupting at SMI\n"); 202 } else { 203 /* Install interrupt handler */ 204 if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0) == 0) { 205 intrstr = pci_intr_string(pa->pa_pc, sc->sc_pihp[0], 206 intrbuf, sizeof(intrbuf)); 207 pci_intr_setattr(pa->pa_pc, &sc->sc_pihp[0], 208 PCI_INTR_MPSAFE, true); 209 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, 210 sc->sc_pihp[0], IPL_BIO, ichsmb_intr, sc, 211 device_xname(sc->sc_dev)); 212 if (sc->sc_ih != NULL) { 213 aprint_normal_dev(self, "interrupting at %s\n", 214 intrstr); 215 sc->sc_poll = 0; 216 } else { 217 pci_intr_release(pa->pa_pc, sc->sc_pihp, 1); 218 sc->sc_pihp = NULL; 219 } 220 } 221 if (sc->sc_poll) 222 aprint_normal_dev(self, "polling\n"); 223 } 224 225 /* Attach I2C bus */ 226 iic_tag_init(&sc->sc_i2c_tag); 227 sc->sc_i2c_tag.ic_cookie = sc; 228 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 229 230 sc->sc_i2c_device = NULL; 231 ichsmb_rescan(self, NULL, NULL); 232 233 out: if (!pmf_device_register(self, NULL, NULL)) 234 aprint_error_dev(self, "couldn't establish power handler\n"); 235 } 236 237 static int 238 ichsmb_rescan(device_t self, const char *ifattr, const int *locators) 239 { 240 struct ichsmb_softc *sc = device_private(self); 241 242 if (ifattr_match(ifattr, "i2cbus") && sc->sc_i2c_device == NULL) { 243 struct i2cbus_attach_args iba; 244 245 memset(&iba, 0, sizeof(iba)); 246 iba.iba_tag = &sc->sc_i2c_tag; 247 sc->sc_i2c_device = config_found(self, &iba, iicbus_print, 248 CFARGS_NONE); 249 } 250 251 return 0; 252 } 253 254 static int 255 ichsmb_detach(device_t self, int flags) 256 { 257 struct ichsmb_softc *sc = device_private(self); 258 int error; 259 260 error = config_detach_children(self, flags); 261 if (error) 262 return error; 263 264 iic_tag_fini(&sc->sc_i2c_tag); 265 266 if (sc->sc_ih) { 267 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 268 sc->sc_ih = NULL; 269 } 270 271 if (sc->sc_pihp) { 272 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 273 sc->sc_pihp = NULL; 274 } 275 276 if (sc->sc_size != 0) 277 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_size); 278 279 mutex_destroy(&sc->sc_exec_lock); 280 cv_destroy(&sc->sc_exec_wait); 281 282 return 0; 283 } 284 285 static void 286 ichsmb_chdet(device_t self, device_t child) 287 { 288 struct ichsmb_softc *sc = device_private(self); 289 290 if (sc->sc_i2c_device == child) 291 sc->sc_i2c_device = NULL; 292 } 293 294 static int 295 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 296 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 297 { 298 struct ichsmb_softc *sc = cookie; 299 const uint8_t *b; 300 uint8_t ctl = 0, st; 301 int retries; 302 char fbuf[64]; 303 304 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 305 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 306 len, flags)); 307 308 mutex_enter(&sc->sc_exec_lock); 309 310 /* Clear status bits */ 311 bus_space_write_1(sc->sc_iot, sc->sc_ioh, SMB_HS, 312 SMB_HS_INTR | SMB_HS_DEVERR | SMB_HS_BUSERR | SMB_HS_FAILED); 313 bus_space_barrier(sc->sc_iot, sc->sc_ioh, SMB_HS, 1, 314 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 315 316 /* Wait for bus to be idle */ 317 for (retries = 100; retries > 0; retries--) { 318 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, SMB_HS); 319 if (!(st & SMB_HS_BUSY)) 320 break; 321 DELAY(ICHIIC_DELAY); 322 } 323 #ifdef ICHIIC_DEBUG 324 snprintb(fbuf, sizeof(fbuf), SMB_HS_BITS, st); 325 printf("%s: exec: st %s\n", device_xname(sc->sc_dev), fbuf); 326 #endif 327 if (st & SMB_HS_BUSY) { 328 mutex_exit(&sc->sc_exec_lock); 329 return (EBUSY); 330 } 331 332 if (sc->sc_poll) 333 flags |= I2C_F_POLL; 334 335 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 336 (cmdlen == 0 && len > 1)) { 337 mutex_exit(&sc->sc_exec_lock); 338 return (EINVAL); 339 } 340 341 /* Setup transfer */ 342 sc->sc_i2c_xfer.op = op; 343 sc->sc_i2c_xfer.buf = buf; 344 sc->sc_i2c_xfer.len = len; 345 sc->sc_i2c_xfer.flags = flags; 346 sc->sc_i2c_xfer.error = 0; 347 sc->sc_i2c_xfer.done = false; 348 349 /* Set slave address and transfer direction */ 350 bus_space_write_1(sc->sc_iot, sc->sc_ioh, SMB_TXSLVA, 351 SMB_TXSLVA_ADDR(addr) | 352 (I2C_OP_READ_P(op) ? SMB_TXSLVA_READ : 0)); 353 354 b = (const uint8_t *)cmdbuf; 355 if (cmdlen > 0) 356 /* Set command byte */ 357 bus_space_write_1(sc->sc_iot, sc->sc_ioh, SMB_HCMD, b[0]); 358 359 if (I2C_OP_WRITE_P(op)) { 360 /* Write data */ 361 b = buf; 362 if (cmdlen == 0 && len == 1) 363 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 364 SMB_HCMD, b[0]); 365 else if (len > 0) 366 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 367 SMB_HD0, b[0]); 368 if (len > 1) 369 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 370 SMB_HD1, b[1]); 371 } 372 373 /* Set SMBus command */ 374 if (cmdlen == 0) { 375 if (len == 0) 376 ctl = SMB_HC_CMD_QUICK; 377 else 378 ctl = SMB_HC_CMD_BYTE; 379 } else if (len == 1) 380 ctl = SMB_HC_CMD_BDATA; 381 else if (len == 2) 382 ctl = SMB_HC_CMD_WDATA; 383 384 if ((flags & I2C_F_POLL) == 0) 385 ctl |= SMB_HC_INTREN; 386 387 /* Start transaction */ 388 ctl |= SMB_HC_START; 389 bus_space_write_1(sc->sc_iot, sc->sc_ioh, SMB_HC, ctl); 390 391 if (flags & I2C_F_POLL) { 392 /* Poll for completion */ 393 DELAY(ICHIIC_DELAY); 394 for (retries = 1000; retries > 0; retries--) { 395 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, SMB_HS); 396 if ((st & SMB_HS_BUSY) == 0) 397 break; 398 DELAY(ICHIIC_DELAY); 399 } 400 if (st & SMB_HS_BUSY) 401 goto timeout; 402 ichsmb_intr(sc); 403 } else { 404 /* Wait for interrupt */ 405 while (! sc->sc_i2c_xfer.done) { 406 if (cv_timedwait(&sc->sc_exec_wait, &sc->sc_exec_lock, 407 ICHIIC_TIMEOUT * hz)) 408 goto timeout; 409 } 410 } 411 412 int error = sc->sc_i2c_xfer.error; 413 mutex_exit(&sc->sc_exec_lock); 414 415 return (error); 416 417 timeout: 418 /* 419 * Transfer timeout. Kill the transaction and clear status bits. 420 */ 421 bus_space_write_1(sc->sc_iot, sc->sc_ioh, SMB_HC, SMB_HC_KILL); 422 DELAY(ICHIIC_DELAY); 423 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, SMB_HS); 424 if ((st & SMB_HS_FAILED) == 0) { 425 snprintb(fbuf, sizeof(fbuf), SMB_HS_BITS, st); 426 aprint_error_dev(sc->sc_dev, "abort failed, status %s\n", 427 fbuf); 428 } 429 bus_space_write_1(sc->sc_iot, sc->sc_ioh, SMB_HS, st); 430 mutex_exit(&sc->sc_exec_lock); 431 return (ETIMEDOUT); 432 } 433 434 static int 435 ichsmb_intr(void *arg) 436 { 437 struct ichsmb_softc *sc = arg; 438 uint8_t st; 439 uint8_t *b; 440 size_t len; 441 #ifdef ICHIIC_DEBUG 442 char fbuf[64]; 443 #endif 444 445 /* Read status */ 446 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, SMB_HS); 447 448 /* Clear status bits */ 449 bus_space_write_1(sc->sc_iot, sc->sc_ioh, SMB_HS, st); 450 451 /* XXX Ignore SMBALERT# for now */ 452 if ((st & SMB_HS_BUSY) != 0 || 453 (st & (SMB_HS_INTR | SMB_HS_DEVERR | SMB_HS_BUSERR | 454 SMB_HS_FAILED | SMB_HS_BDONE)) == 0) 455 /* Interrupt was not for us */ 456 return (0); 457 458 #ifdef ICHIIC_DEBUG 459 snprintb(fbuf, sizeof(fbuf), SMB_HS_BITS, st); 460 printf("%s: intr st %s\n", device_xname(sc->sc_dev), fbuf); 461 #endif 462 463 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 464 mutex_enter(&sc->sc_exec_lock); 465 466 /* Check for errors */ 467 if (st & (SMB_HS_DEVERR | SMB_HS_BUSERR | SMB_HS_FAILED)) { 468 sc->sc_i2c_xfer.error = EIO; 469 goto done; 470 } 471 472 if (st & SMB_HS_INTR) { 473 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 474 goto done; 475 476 /* Read data */ 477 b = sc->sc_i2c_xfer.buf; 478 len = sc->sc_i2c_xfer.len; 479 if (len > 0) 480 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 481 SMB_HD0); 482 if (len > 1) 483 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 484 SMB_HD1); 485 } 486 487 done: 488 sc->sc_i2c_xfer.done = true; 489 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) { 490 cv_signal(&sc->sc_exec_wait); 491 mutex_exit(&sc->sc_exec_lock); 492 } 493 return (1); 494 } 495 496 MODULE(MODULE_CLASS_DRIVER, ichsmb, "pci,iic"); 497 498 #ifdef _MODULE 499 #include "ioconf.c" 500 #endif 501 502 static int 503 ichsmb_modcmd(modcmd_t cmd, void *opaque) 504 { 505 int error = 0; 506 507 switch (cmd) { 508 case MODULE_CMD_INIT: 509 #ifdef _MODULE 510 error = config_init_component(cfdriver_ioconf_ichsmb, 511 cfattach_ioconf_ichsmb, cfdata_ioconf_ichsmb); 512 #endif 513 break; 514 case MODULE_CMD_FINI: 515 #ifdef _MODULE 516 error = config_fini_component(cfdriver_ioconf_ichsmb, 517 cfattach_ioconf_ichsmb, cfdata_ioconf_ichsmb); 518 #endif 519 break; 520 default: 521 #ifdef _MODULE 522 error = ENOTTY; 523 #endif 524 break; 525 } 526 527 return error; 528 } 529
Indexes created Thu Oct 02 14:10:14 GMT 2025