icp_pci.c revision 1.14
1 /* $NetBSD: icp_pci.c,v 1.14 2007/10/19 12:00:44 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1999, 2000 Niklas Hallqvist. All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Niklas Hallqvist. 53 * 4. The name of the author may not be used to endorse or promote products 54 * derived from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 57 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 58 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 59 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 60 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 61 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 62 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 63 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 64 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 65 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 66 * 67 * from OpenBSD: icp_pci.c,v 1.11 2001/06/12 15:40:30 niklas Exp 68 */ 69 70 /* 71 * This driver would not have written if it was not for the hardware donations 72 * from both ICP-Vortex and ko.neT. I want to thank them for their support. 73 * 74 * Re-worked for NetBSD by Andrew Doran. Test hardware kindly supplied by 75 * Intel. 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: icp_pci.c,v 1.14 2007/10/19 12:00:44 ad Exp $"); 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/device.h> 84 #include <sys/kernel.h> 85 #include <sys/queue.h> 86 #include <sys/buf.h> 87 #include <sys/endian.h> 88 #include <sys/conf.h> 89 90 #include <uvm/uvm_extern.h> 91 92 #include <sys/bus.h> 93 94 #include <dev/pci/pcireg.h> 95 #include <dev/pci/pcivar.h> 96 #include <dev/pci/pcidevs.h> 97 98 #include <dev/ic/icpreg.h> 99 #include <dev/ic/icpvar.h> 100 101 /* Product numbers for Fibre-Channel are greater than or equal to 0x200 */ 102 #define ICP_PCI_PRODUCT_FC 0x200 103 104 /* Mapping registers for various areas */ 105 #define ICP_PCI_DPMEM 0x10 106 #define ICP_PCINEW_IOMEM 0x10 107 #define ICP_PCINEW_IO 0x14 108 #define ICP_PCINEW_DPMEM 0x18 109 110 /* PCI SRAM structure */ 111 #define ICP_MAGIC 0x00 /* u_int32_t, controller ID from BIOS */ 112 #define ICP_NEED_DEINIT 0x04 /* u_int16_t, switch between BIOS/driver */ 113 #define ICP_SWITCH_SUPPORT 0x06 /* u_int8_t, see ICP_NEED_DEINIT */ 114 #define ICP_OS_USED 0x10 /* u_int8_t [16], OS code per service */ 115 #define ICP_FW_MAGIC 0x3c /* u_int8_t, controller ID from firmware */ 116 #define ICP_SRAM_SZ 0x40 117 118 /* DPRAM PCI controllers */ 119 #define ICP_DPR_IF 0x00 /* interface area */ 120 #define ICP_6SR (0xff0 - ICP_SRAM_SZ) 121 #define ICP_SEMA1 0xff1 /* volatile u_int8_t, command semaphore */ 122 #define ICP_IRQEN 0xff5 /* u_int8_t, board interrupts enable */ 123 #define ICP_EVENT 0xff8 /* u_int8_t, release event */ 124 #define ICP_IRQDEL 0xffc /* u_int8_t, acknowledge board interrupt */ 125 #define ICP_DPRAM_SZ 0x1000 126 127 /* PLX register structure (new PCI controllers) */ 128 #define ICP_CFG_REG 0x00 /* u_int8_t, DPRAM cfg. (2: < 1MB, 0: any) */ 129 #define ICP_SEMA0_REG 0x40 /* volatile u_int8_t, command semaphore */ 130 #define ICP_SEMA1_REG 0x41 /* volatile u_int8_t, status semaphore */ 131 #define ICP_PLX_STATUS 0x44 /* volatile u_int16_t, command status */ 132 #define ICP_PLX_SERVICE 0x46 /* u_int16_t, service */ 133 #define ICP_PLX_INFO 0x48 /* u_int32_t [2], additional info */ 134 #define ICP_LDOOR_REG 0x60 /* u_int8_t, PCI to local doorbell */ 135 #define ICP_EDOOR_REG 0x64 /* volatile u_int8_t, local to PCI doorbell */ 136 #define ICP_CONTROL0 0x68 /* u_int8_t, control0 register (unused) */ 137 #define ICP_CONTROL1 0x69 /* u_int8_t, board interrupts enable */ 138 #define ICP_PLX_SZ 0x80 139 140 /* DPRAM new PCI controllers */ 141 #define ICP_IC 0x00 /* interface */ 142 #define ICP_PCINEW_6SR (0x4000 - ICP_SRAM_SZ) 143 /* SRAM structure */ 144 #define ICP_PCINEW_SZ 0x4000 145 146 /* i960 register structure (PCI MPR controllers) */ 147 #define ICP_MPR_SEMA0 0x10 /* volatile u_int8_t, command semaphore */ 148 #define ICP_MPR_SEMA1 0x12 /* volatile u_int8_t, status semaphore */ 149 #define ICP_MPR_STATUS 0x14 /* volatile u_int16_t, command status */ 150 #define ICP_MPR_SERVICE 0x16 /* u_int16_t, service */ 151 #define ICP_MPR_INFO 0x18 /* u_int32_t [2], additional info */ 152 #define ICP_MPR_LDOOR 0x20 /* u_int8_t, PCI to local doorbell */ 153 #define ICP_MPR_EDOOR 0x2c /* volatile u_int8_t, locl to PCI doorbell */ 154 #define ICP_EDOOR_EN 0x34 /* u_int8_t, board interrupts enable */ 155 #define ICP_SEVERITY 0xefc /* u_int8_t, event severity */ 156 #define ICP_EVT_BUF 0xf00 /* u_int8_t [256], event buffer */ 157 #define ICP_I960_SZ 0x1000 158 159 /* DPRAM PCI MPR controllers */ 160 #define ICP_I960R 0x00 /* 4KB i960 registers */ 161 #define ICP_MPR_IC ICP_I960_SZ 162 /* interface area */ 163 #define ICP_MPR_6SR (ICP_I960_SZ + 0x3000 - ICP_SRAM_SZ) 164 /* SRAM structure */ 165 #define ICP_MPR_SZ 0x4000 166 167 int icp_pci_match(struct device *, struct cfdata *, void *); 168 void icp_pci_attach(struct device *, struct device *, void *); 169 void icp_pci_enable_intr(struct icp_softc *); 170 int icp_pci_find_class(struct pci_attach_args *); 171 172 void icp_pci_copy_cmd(struct icp_softc *, struct icp_ccb *); 173 u_int8_t icp_pci_get_status(struct icp_softc *); 174 void icp_pci_intr(struct icp_softc *, struct icp_intr_ctx *); 175 void icp_pci_release_event(struct icp_softc *, struct icp_ccb *); 176 void icp_pci_set_sema0(struct icp_softc *); 177 int icp_pci_test_busy(struct icp_softc *); 178 179 void icp_pcinew_copy_cmd(struct icp_softc *, struct icp_ccb *); 180 u_int8_t icp_pcinew_get_status(struct icp_softc *); 181 void icp_pcinew_intr(struct icp_softc *, struct icp_intr_ctx *); 182 void icp_pcinew_release_event(struct icp_softc *, struct icp_ccb *); 183 void icp_pcinew_set_sema0(struct icp_softc *); 184 int icp_pcinew_test_busy(struct icp_softc *); 185 186 void icp_mpr_copy_cmd(struct icp_softc *, struct icp_ccb *); 187 u_int8_t icp_mpr_get_status(struct icp_softc *); 188 void icp_mpr_intr(struct icp_softc *, struct icp_intr_ctx *); 189 void icp_mpr_release_event(struct icp_softc *, struct icp_ccb *); 190 void icp_mpr_set_sema0(struct icp_softc *); 191 int icp_mpr_test_busy(struct icp_softc *); 192 193 CFATTACH_DECL(icp_pci, sizeof(struct icp_softc), 194 icp_pci_match, icp_pci_attach, NULL, NULL); 195 196 struct icp_pci_ident { 197 u_short gpi_vendor; 198 u_short gpi_product; 199 u_short gpi_class; 200 } const icp_pci_ident[] = { 201 { PCI_VENDOR_VORTEX, PCI_PRODUCT_VORTEX_GDT_60x0, ICP_PCI }, 202 { PCI_VENDOR_VORTEX, PCI_PRODUCT_VORTEX_GDT_6000B, ICP_PCI }, 203 204 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GDT_RAID1, ICP_MPR }, 205 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GDT_RAID2, ICP_MPR }, 206 }; 207 208 int 209 icp_pci_find_class(struct pci_attach_args *pa) 210 { 211 const struct icp_pci_ident *gpi, *maxgpi; 212 213 gpi = icp_pci_ident; 214 maxgpi = gpi + sizeof(icp_pci_ident) / sizeof(icp_pci_ident[0]); 215 216 for (; gpi < maxgpi; gpi++) 217 if (PCI_VENDOR(pa->pa_id) == gpi->gpi_vendor && 218 PCI_PRODUCT(pa->pa_id) == gpi->gpi_product) 219 return (gpi->gpi_class); 220 221 /* 222 * ICP-Vortex only make RAID controllers, so we employ a heuristic 223 * to match unlisted boards. 224 */ 225 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VORTEX) 226 return (PCI_PRODUCT(pa->pa_id) < 0x100 ? ICP_PCINEW : ICP_MPR); 227 228 return (-1); 229 } 230 231 int 232 icp_pci_match(struct device *parent, struct cfdata *match, 233 void *aux) 234 { 235 struct pci_attach_args *pa; 236 237 pa = aux; 238 239 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 240 return (0); 241 242 return (icp_pci_find_class(pa) != -1); 243 } 244 245 void 246 icp_pci_attach(struct device *parent, struct device *self, void *aux) 247 { 248 struct pci_attach_args *pa; 249 struct icp_softc *icp; 250 bus_space_tag_t dpmemt, iomemt, iot; 251 bus_space_handle_t dpmemh, iomemh, ioh; 252 bus_addr_t dpmembase, iomembase, iobase; 253 bus_size_t dpmemsize, iomemsize, iosize; 254 u_int32_t status; 255 #define DPMEM_MAPPED 1 256 #define IOMEM_MAPPED 2 257 #define IO_MAPPED 4 258 #define INTR_ESTABLISHED 8 259 int retries; 260 u_int8_t protocol; 261 pci_intr_handle_t ih; 262 const char *intrstr; 263 264 pa = aux; 265 status = 0; 266 icp = (struct icp_softc *)self; 267 icp->icp_class = icp_pci_find_class(pa); 268 269 aprint_naive(": RAID controller\n"); 270 aprint_normal(": "); 271 272 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VORTEX && 273 PCI_PRODUCT(pa->pa_id) >= ICP_PCI_PRODUCT_FC) 274 icp->icp_class |= ICP_FC; 275 276 if (pci_mapreg_map(pa, 277 ICP_CLASS(icp) == ICP_PCINEW ? ICP_PCINEW_DPMEM : ICP_PCI_DPMEM, 278 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, &dpmemt, 279 &dpmemh, &dpmembase, &dpmemsize)) { 280 if (pci_mapreg_map(pa, 281 ICP_CLASS(icp) == ICP_PCINEW ? ICP_PCINEW_DPMEM : 282 ICP_PCI_DPMEM, 283 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M, 0, 284 &dpmemt, &dpmemh, &dpmembase, &dpmemsize)) { 285 aprint_error("cannot map DPMEM\n"); 286 goto bail_out; 287 } 288 } 289 status |= DPMEM_MAPPED; 290 icp->icp_dpmemt = dpmemt; 291 icp->icp_dpmemh = dpmemh; 292 icp->icp_dpmembase = dpmembase; 293 icp->icp_dmat = pa->pa_dmat; 294 295 /* 296 * The ICP_PCINEW series also has two other regions to map. 297 */ 298 if (ICP_CLASS(icp) == ICP_PCINEW) { 299 if (pci_mapreg_map(pa, ICP_PCINEW_IOMEM, PCI_MAPREG_TYPE_MEM, 300 0, &iomemt, &iomemh, &iomembase, &iomemsize)) { 301 aprint_error("cannot map memory mapped I/O ports\n"); 302 goto bail_out; 303 } 304 status |= IOMEM_MAPPED; 305 306 if (pci_mapreg_map(pa, ICP_PCINEW_IO, PCI_MAPREG_TYPE_IO, 0, 307 &iot, &ioh, &iobase, &iosize)) { 308 aprint_error("cannot map I/O ports\n"); 309 goto bail_out; 310 } 311 status |= IO_MAPPED; 312 icp->icp_iot = iot; 313 icp->icp_ioh = ioh; 314 icp->icp_iobase = iobase; 315 } 316 317 switch (ICP_CLASS(icp)) { 318 case ICP_PCI: 319 bus_space_set_region_4(dpmemt, dpmemh, 0, 0, 320 ICP_DPR_IF_SZ >> 2); 321 if (bus_space_read_1(dpmemt, dpmemh, 0) != 0) { 322 aprint_error("cannot write to DPMEM\n"); 323 goto bail_out; 324 } 325 326 #if 0 327 /* disable board interrupts, deinit services */ 328 icph_writeb(0xff, &dp6_ptr->io.irqdel); 329 icph_writeb(0x00, &dp6_ptr->io.irqen); 330 icph_writeb(0x00, &dp6_ptr->u.ic.S_Status); 331 icph_writeb(0x00, &dp6_ptr->u.ic.Cmd_Index); 332 333 icph_writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]); 334 icph_writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx); 335 icph_writeb(0, &dp6_ptr->io.event); 336 retries = INIT_RETRIES; 337 icph_delay(20); 338 while (icph_readb(&dp6_ptr->u.ic.S_Status) != 0xff) { 339 if (--retries == 0) { 340 printk("initialization error (DEINIT failed)\n"); 341 icph_munmap(ha->brd); 342 return 0; 343 } 344 icph_delay(1); 345 } 346 prot_ver = (unchar)icph_readl(&dp6_ptr->u.ic.S_Info[0]); 347 icph_writeb(0, &dp6_ptr->u.ic.S_Status); 348 icph_writeb(0xff, &dp6_ptr->io.irqdel); 349 if (prot_ver != PROTOCOL_VERSION) { 350 printk("illegal protocol version\n"); 351 icph_munmap(ha->brd); 352 return 0; 353 } 354 355 ha->type = ICP_PCI; 356 ha->ic_all_size = sizeof(dp6_ptr->u); 357 358 /* special command to controller BIOS */ 359 icph_writel(0x00, &dp6_ptr->u.ic.S_Info[0]); 360 icph_writel(0x00, &dp6_ptr->u.ic.S_Info[1]); 361 icph_writel(0x01, &dp6_ptr->u.ic.S_Info[2]); 362 icph_writel(0x00, &dp6_ptr->u.ic.S_Info[3]); 363 icph_writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx); 364 icph_writeb(0, &dp6_ptr->io.event); 365 retries = INIT_RETRIES; 366 icph_delay(20); 367 while (icph_readb(&dp6_ptr->u.ic.S_Status) != 0xfe) { 368 if (--retries == 0) { 369 printk("initialization error\n"); 370 icph_munmap(ha->brd); 371 return 0; 372 } 373 icph_delay(1); 374 } 375 icph_writeb(0, &dp6_ptr->u.ic.S_Status); 376 icph_writeb(0xff, &dp6_ptr->io.irqdel); 377 #endif 378 379 icp->icp_ic_all_size = ICP_DPRAM_SZ; 380 381 icp->icp_copy_cmd = icp_pci_copy_cmd; 382 icp->icp_get_status = icp_pci_get_status; 383 icp->icp_intr = icp_pci_intr; 384 icp->icp_release_event = icp_pci_release_event; 385 icp->icp_set_sema0 = icp_pci_set_sema0; 386 icp->icp_test_busy = icp_pci_test_busy; 387 388 break; 389 390 case ICP_PCINEW: 391 bus_space_set_region_4(dpmemt, dpmemh, 0, 0, 392 ICP_DPR_IF_SZ >> 2); 393 if (bus_space_read_1(dpmemt, dpmemh, 0) != 0) { 394 aprint_error("cannot write to DPMEM\n"); 395 goto bail_out; 396 } 397 398 #if 0 399 /* disable board interrupts, deinit services */ 400 outb(0x00,PTR2USHORT(&ha->plx->control1)); 401 outb(0xff,PTR2USHORT(&ha->plx->edoor_reg)); 402 403 icph_writeb(0x00, &dp6c_ptr->u.ic.S_Status); 404 icph_writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index); 405 406 icph_writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]); 407 icph_writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx); 408 409 outb(1,PTR2USHORT(&ha->plx->ldoor_reg)); 410 411 retries = INIT_RETRIES; 412 icph_delay(20); 413 while (icph_readb(&dp6c_ptr->u.ic.S_Status) != 0xff) { 414 if (--retries == 0) { 415 printk("initialization error (DEINIT failed)\n"); 416 icph_munmap(ha->brd); 417 return 0; 418 } 419 icph_delay(1); 420 } 421 prot_ver = (unchar)icph_readl(&dp6c_ptr->u.ic.S_Info[0]); 422 icph_writeb(0, &dp6c_ptr->u.ic.Status); 423 if (prot_ver != PROTOCOL_VERSION) { 424 printk("illegal protocol version\n"); 425 icph_munmap(ha->brd); 426 return 0; 427 } 428 429 ha->type = ICP_PCINEW; 430 ha->ic_all_size = sizeof(dp6c_ptr->u); 431 432 /* special command to controller BIOS */ 433 icph_writel(0x00, &dp6c_ptr->u.ic.S_Info[0]); 434 icph_writel(0x00, &dp6c_ptr->u.ic.S_Info[1]); 435 icph_writel(0x01, &dp6c_ptr->u.ic.S_Info[2]); 436 icph_writel(0x00, &dp6c_ptr->u.ic.S_Info[3]); 437 icph_writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx); 438 439 outb(1,PTR2USHORT(&ha->plx->ldoor_reg)); 440 441 retries = INIT_RETRIES; 442 icph_delay(20); 443 while (icph_readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) { 444 if (--retries == 0) { 445 printk("initialization error\n"); 446 icph_munmap(ha->brd); 447 return 0; 448 } 449 icph_delay(1); 450 } 451 icph_writeb(0, &dp6c_ptr->u.ic.S_Status); 452 #endif 453 454 icp->icp_ic_all_size = ICP_PCINEW_SZ; 455 456 icp->icp_copy_cmd = icp_pcinew_copy_cmd; 457 icp->icp_get_status = icp_pcinew_get_status; 458 icp->icp_intr = icp_pcinew_intr; 459 icp->icp_release_event = icp_pcinew_release_event; 460 icp->icp_set_sema0 = icp_pcinew_set_sema0; 461 icp->icp_test_busy = icp_pcinew_test_busy; 462 463 break; 464 465 case ICP_MPR: 466 bus_space_write_4(dpmemt, dpmemh, ICP_MPR_IC, ICP_MPR_MAGIC); 467 if (bus_space_read_4(dpmemt, dpmemh, ICP_MPR_IC) != 468 ICP_MPR_MAGIC) { 469 aprint_error( 470 "cannot access DPMEM at 0x%lx (shadowed?)\n", 471 (u_long)dpmembase); 472 goto bail_out; 473 } 474 475 /* 476 * XXX Here the Linux driver has a weird remapping logic I 477 * don't understand. My controller does not need it, and I 478 * cannot see what purpose it serves, therefore I did not 479 * do anything similar. 480 */ 481 482 bus_space_set_region_4(dpmemt, dpmemh, ICP_I960_SZ, 0, 483 ICP_DPR_IF_SZ >> 2); 484 485 /* Disable everything. */ 486 bus_space_write_1(dpmemt, dpmemh, ICP_EDOOR_EN, 487 bus_space_read_1(dpmemt, dpmemh, ICP_EDOOR_EN) | 4); 488 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_EDOOR, 0xff); 489 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_STATUS, 490 0); 491 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_CMD_INDEX, 492 0); 493 494 bus_space_write_4(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_INFO, 495 htole32(dpmembase)); 496 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_CMD_INDX, 497 0xff); 498 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_LDOOR, 1); 499 500 DELAY(20); 501 retries = 1000000; 502 while (bus_space_read_1(dpmemt, dpmemh, 503 ICP_MPR_IC + ICP_S_STATUS) != 0xff) { 504 if (--retries == 0) { 505 aprint_error("DEINIT failed\n"); 506 goto bail_out; 507 } 508 DELAY(1); 509 } 510 511 protocol = (u_int8_t)bus_space_read_4(dpmemt, dpmemh, 512 ICP_MPR_IC + ICP_S_INFO); 513 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_STATUS, 514 0); 515 if (protocol != ICP_PROTOCOL_VERSION) { 516 aprint_error("unsupported protocol %d\n", protocol); 517 goto bail_out; 518 } 519 520 /* special commnd to controller BIOS */ 521 bus_space_write_4(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_INFO, 0); 522 bus_space_write_4(dpmemt, dpmemh, 523 ICP_MPR_IC + ICP_S_INFO + sizeof(u_int32_t), 0); 524 bus_space_write_4(dpmemt, dpmemh, 525 ICP_MPR_IC + ICP_S_INFO + 2 * sizeof(u_int32_t), 1); 526 bus_space_write_4(dpmemt, dpmemh, 527 ICP_MPR_IC + ICP_S_INFO + 3 * sizeof(u_int32_t), 0); 528 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_CMD_INDX, 529 0xfe); 530 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_LDOOR, 1); 531 532 DELAY(20); 533 retries = 1000000; 534 while (bus_space_read_1(dpmemt, dpmemh, 535 ICP_MPR_IC + ICP_S_STATUS) != 0xfe) { 536 if (--retries == 0) { 537 aprint_error("initialization error\n"); 538 goto bail_out; 539 } 540 DELAY(1); 541 } 542 543 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_STATUS, 544 0); 545 546 icp->icp_copy_cmd = icp_mpr_copy_cmd; 547 icp->icp_get_status = icp_mpr_get_status; 548 icp->icp_intr = icp_mpr_intr; 549 icp->icp_release_event = icp_mpr_release_event; 550 icp->icp_set_sema0 = icp_mpr_set_sema0; 551 icp->icp_test_busy = icp_mpr_test_busy; 552 break; 553 } 554 555 if (pci_intr_map(pa, &ih)) { 556 aprint_error("couldn't map interrupt\n"); 557 goto bail_out; 558 } 559 intrstr = pci_intr_string(pa->pa_pc, ih); 560 icp->icp_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, icp_intr, icp); 561 if (icp->icp_ih == NULL) { 562 aprint_error("couldn't establish interrupt"); 563 if (intrstr != NULL) 564 aprint_normal(" at %s", intrstr); 565 aprint_normal("\n"); 566 goto bail_out; 567 } 568 status |= INTR_ESTABLISHED; 569 570 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) 571 aprint_normal("Intel Storage RAID controller\n"); 572 else 573 aprint_normal("ICP-Vortex RAID controller\n"); 574 575 icp->icp_pci_bus = pa->pa_bus; 576 icp->icp_pci_device = pa->pa_device; 577 icp->icp_pci_device_id = PCI_PRODUCT(pa->pa_id); 578 icp->icp_pci_subdevice_id = pci_conf_read(pa->pa_pc, pa->pa_tag, 579 PCI_SUBSYS_ID_REG); 580 581 if (icp_init(icp, intrstr)) 582 goto bail_out; 583 584 icp_pci_enable_intr(icp); 585 return; 586 587 bail_out: 588 if ((status & DPMEM_MAPPED) != 0) 589 bus_space_unmap(dpmemt, dpmemh, dpmemsize); 590 if ((status & IOMEM_MAPPED) != 0) 591 bus_space_unmap(iomemt, iomemh, iomembase); 592 if ((status & IO_MAPPED) != 0) 593 bus_space_unmap(iot, ioh, iosize); 594 if ((status & INTR_ESTABLISHED) != 0) 595 pci_intr_disestablish(pa->pa_pc, icp->icp_ih); 596 } 597 598 /* 599 * Enable interrupts. 600 */ 601 void 602 icp_pci_enable_intr(struct icp_softc *icp) 603 { 604 605 switch (ICP_CLASS(icp)) { 606 case ICP_PCI: 607 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_IRQDEL, 608 1); 609 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, 610 ICP_CMD_INDEX, 0); 611 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_IRQEN, 612 1); 613 break; 614 615 case ICP_PCINEW: 616 bus_space_write_1(icp->icp_iot, icp->icp_ioh, ICP_EDOOR_REG, 617 0xff); 618 bus_space_write_1(icp->icp_iot, icp->icp_ioh, ICP_CONTROL1, 3); 619 break; 620 621 case ICP_MPR: 622 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, 623 ICP_MPR_EDOOR, 0xff); 624 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_EDOOR_EN, 625 bus_space_read_1(icp->icp_dpmemt, icp->icp_dpmemh, 626 ICP_EDOOR_EN) & ~4); 627 break; 628 } 629 } 630 631 /* 632 * "Old" PCI controller-specific functions. 633 */ 634 635 void 636 icp_pci_copy_cmd(struct icp_softc *icp, struct icp_ccb *ccb) 637 { 638 639 /* XXX Not yet implemented */ 640 } 641 642 u_int8_t 643 icp_pci_get_status(struct icp_softc *icp) 644 { 645 646 /* XXX Not yet implemented */ 647 return (0); 648 } 649 650 void 651 icp_pci_intr(struct icp_softc *icp, struct icp_intr_ctx *ctx) 652 { 653 654 /* XXX Not yet implemented */ 655 } 656 657 void 658 icp_pci_release_event(struct icp_softc *icp, 659 struct icp_ccb *ccb) 660 { 661 662 /* XXX Not yet implemented */ 663 } 664 665 void 666 icp_pci_set_sema0(struct icp_softc *icp) 667 { 668 669 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_SEMA0, 1); 670 } 671 672 int 673 icp_pci_test_busy(struct icp_softc *icp) 674 { 675 676 /* XXX Not yet implemented */ 677 return (0); 678 } 679 680 /* 681 * "New" PCI controller-specific functions. 682 */ 683 684 void 685 icp_pcinew_copy_cmd(struct icp_softc *icp, 686 struct icp_ccb *ccb) 687 { 688 689 /* XXX Not yet implemented */ 690 } 691 692 u_int8_t 693 icp_pcinew_get_status(struct icp_softc *icp) 694 { 695 696 /* XXX Not yet implemented */ 697 return (0); 698 } 699 700 void 701 icp_pcinew_intr(struct icp_softc *icp, 702 struct icp_intr_ctx *ctx) 703 { 704 705 /* XXX Not yet implemented */ 706 } 707 708 void 709 icp_pcinew_release_event(struct icp_softc *icp, 710 struct icp_ccb *ccb) 711 { 712 713 /* XXX Not yet implemented */ 714 } 715 716 void 717 icp_pcinew_set_sema0(struct icp_softc *icp) 718 { 719 720 bus_space_write_1(icp->icp_iot, icp->icp_ioh, ICP_SEMA0_REG, 1); 721 } 722 723 int 724 icp_pcinew_test_busy(struct icp_softc *icp) 725 { 726 727 /* XXX Not yet implemented */ 728 return (0); 729 } 730 731 /* 732 * MPR PCI controller-specific functions 733 */ 734 735 void 736 icp_mpr_copy_cmd(struct icp_softc *icp, struct icp_ccb *ic) 737 { 738 739 bus_space_write_2(icp->icp_dpmemt, icp->icp_dpmemh, 740 ICP_MPR_IC + ICP_COMM_QUEUE + 0 * ICP_COMM_Q_SZ + ICP_OFFSET, 741 ICP_DPR_CMD); 742 bus_space_write_2(icp->icp_dpmemt, icp->icp_dpmemh, 743 ICP_MPR_IC + ICP_COMM_QUEUE + 0 * ICP_COMM_Q_SZ + ICP_SERV_ID, 744 ic->ic_service); 745 bus_space_write_region_4(icp->icp_dpmemt, icp->icp_dpmemh, 746 ICP_MPR_IC + ICP_DPR_CMD, (u_int32_t *)&ic->ic_cmd, 747 ic->ic_cmdlen >> 2); 748 } 749 750 u_int8_t 751 icp_mpr_get_status(struct icp_softc *icp) 752 { 753 754 return (bus_space_read_1(icp->icp_dpmemt, icp->icp_dpmemh, 755 ICP_MPR_EDOOR)); 756 } 757 758 void 759 icp_mpr_intr(struct icp_softc *icp, struct icp_intr_ctx *ctx) 760 { 761 762 if ((ctx->istatus & 0x80) != 0) { /* error flag */ 763 ctx->istatus &= ~0x80; 764 ctx->cmd_status = bus_space_read_2(icp->icp_dpmemt, 765 icp->icp_dpmemh, ICP_MPR_STATUS); 766 } else 767 ctx->cmd_status = ICP_S_OK; 768 769 ctx->service = bus_space_read_2(icp->icp_dpmemt, icp->icp_dpmemh, 770 ICP_MPR_SERVICE); 771 ctx->info = bus_space_read_4(icp->icp_dpmemt, icp->icp_dpmemh, 772 ICP_MPR_INFO); 773 ctx->info2 = bus_space_read_4(icp->icp_dpmemt, icp->icp_dpmemh, 774 ICP_MPR_INFO + sizeof(u_int32_t)); 775 776 if (ctx->istatus == ICP_ASYNCINDEX) { 777 if (ctx->service != ICP_SCREENSERVICE && 778 (icp->icp_fw_vers & 0xff) >= 0x1a) { 779 int i; 780 781 icp->icp_evt.severity = 782 bus_space_read_1(icp->icp_dpmemt, 783 icp->icp_dpmemh, ICP_SEVERITY); 784 for (i = 0; 785 i < sizeof(icp->icp_evt.event_string); i++) { 786 icp->icp_evt.event_string[i] = 787 bus_space_read_1(icp->icp_dpmemt, 788 icp->icp_dpmemh, ICP_EVT_BUF + i); 789 if (icp->icp_evt.event_string[i] == '\0') 790 break; 791 } 792 } 793 } 794 795 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_MPR_EDOOR, 796 0xff); 797 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_MPR_SEMA1, 0); 798 } 799 800 void 801 icp_mpr_release_event(struct icp_softc *icp, struct icp_ccb *ic) 802 { 803 804 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_MPR_LDOOR, 1); 805 } 806 807 void 808 icp_mpr_set_sema0(struct icp_softc *icp) 809 { 810 811 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_MPR_SEMA0, 1); 812 } 813 814 int 815 icp_mpr_test_busy(struct icp_softc *icp) 816 { 817 818 return (bus_space_read_1(icp->icp_dpmemt, icp->icp_dpmemh, 819 ICP_MPR_SEMA0) & 1); 820 } 821
Indexes created Mon Sep 29 21:09:56 GMT 2025