icp_pci.c revision 1.14.18.1
1 /* $NetBSD: icp_pci.c,v 1.14.18.1 2008/05/18 12:34:19 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1999, 2000 Niklas Hallqvist. All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by Niklas Hallqvist. 46 * 4. The name of the author may not be used to endorse or promote products 47 * derived from this software without specific prior written permission. 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 50 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 51 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 52 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 53 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 54 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 55 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 56 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 57 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 58 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 59 * 60 * from OpenBSD: icp_pci.c,v 1.11 2001/06/12 15:40:30 niklas Exp 61 */ 62 63 /* 64 * This driver would not have written if it was not for the hardware donations 65 * from both ICP-Vortex and ko.neT. I want to thank them for their support. 66 * 67 * Re-worked for NetBSD by Andrew Doran. Test hardware kindly supplied by 68 * Intel. 69 */ 70 71 #include <sys/cdefs.h> 72 __KERNEL_RCSID(0, "$NetBSD: icp_pci.c,v 1.14.18.1 2008/05/18 12:34:19 yamt Exp $"); 73 74 #include <sys/param.h> 75 #include <sys/systm.h> 76 #include <sys/device.h> 77 #include <sys/kernel.h> 78 #include <sys/queue.h> 79 #include <sys/buf.h> 80 #include <sys/endian.h> 81 #include <sys/conf.h> 82 83 #include <uvm/uvm_extern.h> 84 85 #include <sys/bus.h> 86 87 #include <dev/pci/pcireg.h> 88 #include <dev/pci/pcivar.h> 89 #include <dev/pci/pcidevs.h> 90 91 #include <dev/ic/icpreg.h> 92 #include <dev/ic/icpvar.h> 93 94 /* Product numbers for Fibre-Channel are greater than or equal to 0x200 */ 95 #define ICP_PCI_PRODUCT_FC 0x200 96 97 /* Mapping registers for various areas */ 98 #define ICP_PCI_DPMEM 0x10 99 #define ICP_PCINEW_IOMEM 0x10 100 #define ICP_PCINEW_IO 0x14 101 #define ICP_PCINEW_DPMEM 0x18 102 103 /* PCI SRAM structure */ 104 #define ICP_MAGIC 0x00 /* u_int32_t, controller ID from BIOS */ 105 #define ICP_NEED_DEINIT 0x04 /* u_int16_t, switch between BIOS/driver */ 106 #define ICP_SWITCH_SUPPORT 0x06 /* u_int8_t, see ICP_NEED_DEINIT */ 107 #define ICP_OS_USED 0x10 /* u_int8_t [16], OS code per service */ 108 #define ICP_FW_MAGIC 0x3c /* u_int8_t, controller ID from firmware */ 109 #define ICP_SRAM_SZ 0x40 110 111 /* DPRAM PCI controllers */ 112 #define ICP_DPR_IF 0x00 /* interface area */ 113 #define ICP_6SR (0xff0 - ICP_SRAM_SZ) 114 #define ICP_SEMA1 0xff1 /* volatile u_int8_t, command semaphore */ 115 #define ICP_IRQEN 0xff5 /* u_int8_t, board interrupts enable */ 116 #define ICP_EVENT 0xff8 /* u_int8_t, release event */ 117 #define ICP_IRQDEL 0xffc /* u_int8_t, acknowledge board interrupt */ 118 #define ICP_DPRAM_SZ 0x1000 119 120 /* PLX register structure (new PCI controllers) */ 121 #define ICP_CFG_REG 0x00 /* u_int8_t, DPRAM cfg. (2: < 1MB, 0: any) */ 122 #define ICP_SEMA0_REG 0x40 /* volatile u_int8_t, command semaphore */ 123 #define ICP_SEMA1_REG 0x41 /* volatile u_int8_t, status semaphore */ 124 #define ICP_PLX_STATUS 0x44 /* volatile u_int16_t, command status */ 125 #define ICP_PLX_SERVICE 0x46 /* u_int16_t, service */ 126 #define ICP_PLX_INFO 0x48 /* u_int32_t [2], additional info */ 127 #define ICP_LDOOR_REG 0x60 /* u_int8_t, PCI to local doorbell */ 128 #define ICP_EDOOR_REG 0x64 /* volatile u_int8_t, local to PCI doorbell */ 129 #define ICP_CONTROL0 0x68 /* u_int8_t, control0 register (unused) */ 130 #define ICP_CONTROL1 0x69 /* u_int8_t, board interrupts enable */ 131 #define ICP_PLX_SZ 0x80 132 133 /* DPRAM new PCI controllers */ 134 #define ICP_IC 0x00 /* interface */ 135 #define ICP_PCINEW_6SR (0x4000 - ICP_SRAM_SZ) 136 /* SRAM structure */ 137 #define ICP_PCINEW_SZ 0x4000 138 139 /* i960 register structure (PCI MPR controllers) */ 140 #define ICP_MPR_SEMA0 0x10 /* volatile u_int8_t, command semaphore */ 141 #define ICP_MPR_SEMA1 0x12 /* volatile u_int8_t, status semaphore */ 142 #define ICP_MPR_STATUS 0x14 /* volatile u_int16_t, command status */ 143 #define ICP_MPR_SERVICE 0x16 /* u_int16_t, service */ 144 #define ICP_MPR_INFO 0x18 /* u_int32_t [2], additional info */ 145 #define ICP_MPR_LDOOR 0x20 /* u_int8_t, PCI to local doorbell */ 146 #define ICP_MPR_EDOOR 0x2c /* volatile u_int8_t, locl to PCI doorbell */ 147 #define ICP_EDOOR_EN 0x34 /* u_int8_t, board interrupts enable */ 148 #define ICP_SEVERITY 0xefc /* u_int8_t, event severity */ 149 #define ICP_EVT_BUF 0xf00 /* u_int8_t [256], event buffer */ 150 #define ICP_I960_SZ 0x1000 151 152 /* DPRAM PCI MPR controllers */ 153 #define ICP_I960R 0x00 /* 4KB i960 registers */ 154 #define ICP_MPR_IC ICP_I960_SZ 155 /* interface area */ 156 #define ICP_MPR_6SR (ICP_I960_SZ + 0x3000 - ICP_SRAM_SZ) 157 /* SRAM structure */ 158 #define ICP_MPR_SZ 0x4000 159 160 int icp_pci_match(struct device *, struct cfdata *, void *); 161 void icp_pci_attach(struct device *, struct device *, void *); 162 void icp_pci_enable_intr(struct icp_softc *); 163 int icp_pci_find_class(struct pci_attach_args *); 164 165 void icp_pci_copy_cmd(struct icp_softc *, struct icp_ccb *); 166 u_int8_t icp_pci_get_status(struct icp_softc *); 167 void icp_pci_intr(struct icp_softc *, struct icp_intr_ctx *); 168 void icp_pci_release_event(struct icp_softc *, struct icp_ccb *); 169 void icp_pci_set_sema0(struct icp_softc *); 170 int icp_pci_test_busy(struct icp_softc *); 171 172 void icp_pcinew_copy_cmd(struct icp_softc *, struct icp_ccb *); 173 u_int8_t icp_pcinew_get_status(struct icp_softc *); 174 void icp_pcinew_intr(struct icp_softc *, struct icp_intr_ctx *); 175 void icp_pcinew_release_event(struct icp_softc *, struct icp_ccb *); 176 void icp_pcinew_set_sema0(struct icp_softc *); 177 int icp_pcinew_test_busy(struct icp_softc *); 178 179 void icp_mpr_copy_cmd(struct icp_softc *, struct icp_ccb *); 180 u_int8_t icp_mpr_get_status(struct icp_softc *); 181 void icp_mpr_intr(struct icp_softc *, struct icp_intr_ctx *); 182 void icp_mpr_release_event(struct icp_softc *, struct icp_ccb *); 183 void icp_mpr_set_sema0(struct icp_softc *); 184 int icp_mpr_test_busy(struct icp_softc *); 185 186 CFATTACH_DECL(icp_pci, sizeof(struct icp_softc), 187 icp_pci_match, icp_pci_attach, NULL, NULL); 188 189 struct icp_pci_ident { 190 u_short gpi_vendor; 191 u_short gpi_product; 192 u_short gpi_class; 193 } const icp_pci_ident[] = { 194 { PCI_VENDOR_VORTEX, PCI_PRODUCT_VORTEX_GDT_60x0, ICP_PCI }, 195 { PCI_VENDOR_VORTEX, PCI_PRODUCT_VORTEX_GDT_6000B, ICP_PCI }, 196 197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GDT_RAID1, ICP_MPR }, 198 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GDT_RAID2, ICP_MPR }, 199 }; 200 201 int 202 icp_pci_find_class(struct pci_attach_args *pa) 203 { 204 const struct icp_pci_ident *gpi, *maxgpi; 205 206 gpi = icp_pci_ident; 207 maxgpi = gpi + sizeof(icp_pci_ident) / sizeof(icp_pci_ident[0]); 208 209 for (; gpi < maxgpi; gpi++) 210 if (PCI_VENDOR(pa->pa_id) == gpi->gpi_vendor && 211 PCI_PRODUCT(pa->pa_id) == gpi->gpi_product) 212 return (gpi->gpi_class); 213 214 /* 215 * ICP-Vortex only make RAID controllers, so we employ a heuristic 216 * to match unlisted boards. 217 */ 218 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VORTEX) 219 return (PCI_PRODUCT(pa->pa_id) < 0x100 ? ICP_PCINEW : ICP_MPR); 220 221 return (-1); 222 } 223 224 int 225 icp_pci_match(struct device *parent, struct cfdata *match, 226 void *aux) 227 { 228 struct pci_attach_args *pa; 229 230 pa = aux; 231 232 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 233 return (0); 234 235 return (icp_pci_find_class(pa) != -1); 236 } 237 238 void 239 icp_pci_attach(struct device *parent, struct device *self, void *aux) 240 { 241 struct pci_attach_args *pa; 242 struct icp_softc *icp; 243 bus_space_tag_t dpmemt, iomemt, iot; 244 bus_space_handle_t dpmemh, iomemh, ioh; 245 bus_addr_t dpmembase, iomembase, iobase; 246 bus_size_t dpmemsize, iomemsize, iosize; 247 u_int32_t status; 248 #define DPMEM_MAPPED 1 249 #define IOMEM_MAPPED 2 250 #define IO_MAPPED 4 251 #define INTR_ESTABLISHED 8 252 int retries; 253 u_int8_t protocol; 254 pci_intr_handle_t ih; 255 const char *intrstr; 256 257 pa = aux; 258 status = 0; 259 icp = (struct icp_softc *)self; 260 icp->icp_class = icp_pci_find_class(pa); 261 262 aprint_naive(": RAID controller\n"); 263 aprint_normal(": "); 264 265 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VORTEX && 266 PCI_PRODUCT(pa->pa_id) >= ICP_PCI_PRODUCT_FC) 267 icp->icp_class |= ICP_FC; 268 269 if (pci_mapreg_map(pa, 270 ICP_CLASS(icp) == ICP_PCINEW ? ICP_PCINEW_DPMEM : ICP_PCI_DPMEM, 271 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, &dpmemt, 272 &dpmemh, &dpmembase, &dpmemsize)) { 273 if (pci_mapreg_map(pa, 274 ICP_CLASS(icp) == ICP_PCINEW ? ICP_PCINEW_DPMEM : 275 ICP_PCI_DPMEM, 276 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M, 0, 277 &dpmemt, &dpmemh, &dpmembase, &dpmemsize)) { 278 aprint_error("cannot map DPMEM\n"); 279 goto bail_out; 280 } 281 } 282 status |= DPMEM_MAPPED; 283 icp->icp_dpmemt = dpmemt; 284 icp->icp_dpmemh = dpmemh; 285 icp->icp_dpmembase = dpmembase; 286 icp->icp_dmat = pa->pa_dmat; 287 288 /* 289 * The ICP_PCINEW series also has two other regions to map. 290 */ 291 if (ICP_CLASS(icp) == ICP_PCINEW) { 292 if (pci_mapreg_map(pa, ICP_PCINEW_IOMEM, PCI_MAPREG_TYPE_MEM, 293 0, &iomemt, &iomemh, &iomembase, &iomemsize)) { 294 aprint_error("cannot map memory mapped I/O ports\n"); 295 goto bail_out; 296 } 297 status |= IOMEM_MAPPED; 298 299 if (pci_mapreg_map(pa, ICP_PCINEW_IO, PCI_MAPREG_TYPE_IO, 0, 300 &iot, &ioh, &iobase, &iosize)) { 301 aprint_error("cannot map I/O ports\n"); 302 goto bail_out; 303 } 304 status |= IO_MAPPED; 305 icp->icp_iot = iot; 306 icp->icp_ioh = ioh; 307 icp->icp_iobase = iobase; 308 } 309 310 switch (ICP_CLASS(icp)) { 311 case ICP_PCI: 312 bus_space_set_region_4(dpmemt, dpmemh, 0, 0, 313 ICP_DPR_IF_SZ >> 2); 314 if (bus_space_read_1(dpmemt, dpmemh, 0) != 0) { 315 aprint_error("cannot write to DPMEM\n"); 316 goto bail_out; 317 } 318 319 #if 0 320 /* disable board interrupts, deinit services */ 321 icph_writeb(0xff, &dp6_ptr->io.irqdel); 322 icph_writeb(0x00, &dp6_ptr->io.irqen); 323 icph_writeb(0x00, &dp6_ptr->u.ic.S_Status); 324 icph_writeb(0x00, &dp6_ptr->u.ic.Cmd_Index); 325 326 icph_writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]); 327 icph_writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx); 328 icph_writeb(0, &dp6_ptr->io.event); 329 retries = INIT_RETRIES; 330 icph_delay(20); 331 while (icph_readb(&dp6_ptr->u.ic.S_Status) != 0xff) { 332 if (--retries == 0) { 333 printk("initialization error (DEINIT failed)\n"); 334 icph_munmap(ha->brd); 335 return 0; 336 } 337 icph_delay(1); 338 } 339 prot_ver = (unchar)icph_readl(&dp6_ptr->u.ic.S_Info[0]); 340 icph_writeb(0, &dp6_ptr->u.ic.S_Status); 341 icph_writeb(0xff, &dp6_ptr->io.irqdel); 342 if (prot_ver != PROTOCOL_VERSION) { 343 printk("illegal protocol version\n"); 344 icph_munmap(ha->brd); 345 return 0; 346 } 347 348 ha->type = ICP_PCI; 349 ha->ic_all_size = sizeof(dp6_ptr->u); 350 351 /* special command to controller BIOS */ 352 icph_writel(0x00, &dp6_ptr->u.ic.S_Info[0]); 353 icph_writel(0x00, &dp6_ptr->u.ic.S_Info[1]); 354 icph_writel(0x01, &dp6_ptr->u.ic.S_Info[2]); 355 icph_writel(0x00, &dp6_ptr->u.ic.S_Info[3]); 356 icph_writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx); 357 icph_writeb(0, &dp6_ptr->io.event); 358 retries = INIT_RETRIES; 359 icph_delay(20); 360 while (icph_readb(&dp6_ptr->u.ic.S_Status) != 0xfe) { 361 if (--retries == 0) { 362 printk("initialization error\n"); 363 icph_munmap(ha->brd); 364 return 0; 365 } 366 icph_delay(1); 367 } 368 icph_writeb(0, &dp6_ptr->u.ic.S_Status); 369 icph_writeb(0xff, &dp6_ptr->io.irqdel); 370 #endif 371 372 icp->icp_ic_all_size = ICP_DPRAM_SZ; 373 374 icp->icp_copy_cmd = icp_pci_copy_cmd; 375 icp->icp_get_status = icp_pci_get_status; 376 icp->icp_intr = icp_pci_intr; 377 icp->icp_release_event = icp_pci_release_event; 378 icp->icp_set_sema0 = icp_pci_set_sema0; 379 icp->icp_test_busy = icp_pci_test_busy; 380 381 break; 382 383 case ICP_PCINEW: 384 bus_space_set_region_4(dpmemt, dpmemh, 0, 0, 385 ICP_DPR_IF_SZ >> 2); 386 if (bus_space_read_1(dpmemt, dpmemh, 0) != 0) { 387 aprint_error("cannot write to DPMEM\n"); 388 goto bail_out; 389 } 390 391 #if 0 392 /* disable board interrupts, deinit services */ 393 outb(0x00,PTR2USHORT(&ha->plx->control1)); 394 outb(0xff,PTR2USHORT(&ha->plx->edoor_reg)); 395 396 icph_writeb(0x00, &dp6c_ptr->u.ic.S_Status); 397 icph_writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index); 398 399 icph_writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]); 400 icph_writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx); 401 402 outb(1,PTR2USHORT(&ha->plx->ldoor_reg)); 403 404 retries = INIT_RETRIES; 405 icph_delay(20); 406 while (icph_readb(&dp6c_ptr->u.ic.S_Status) != 0xff) { 407 if (--retries == 0) { 408 printk("initialization error (DEINIT failed)\n"); 409 icph_munmap(ha->brd); 410 return 0; 411 } 412 icph_delay(1); 413 } 414 prot_ver = (unchar)icph_readl(&dp6c_ptr->u.ic.S_Info[0]); 415 icph_writeb(0, &dp6c_ptr->u.ic.Status); 416 if (prot_ver != PROTOCOL_VERSION) { 417 printk("illegal protocol version\n"); 418 icph_munmap(ha->brd); 419 return 0; 420 } 421 422 ha->type = ICP_PCINEW; 423 ha->ic_all_size = sizeof(dp6c_ptr->u); 424 425 /* special command to controller BIOS */ 426 icph_writel(0x00, &dp6c_ptr->u.ic.S_Info[0]); 427 icph_writel(0x00, &dp6c_ptr->u.ic.S_Info[1]); 428 icph_writel(0x01, &dp6c_ptr->u.ic.S_Info[2]); 429 icph_writel(0x00, &dp6c_ptr->u.ic.S_Info[3]); 430 icph_writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx); 431 432 outb(1,PTR2USHORT(&ha->plx->ldoor_reg)); 433 434 retries = INIT_RETRIES; 435 icph_delay(20); 436 while (icph_readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) { 437 if (--retries == 0) { 438 printk("initialization error\n"); 439 icph_munmap(ha->brd); 440 return 0; 441 } 442 icph_delay(1); 443 } 444 icph_writeb(0, &dp6c_ptr->u.ic.S_Status); 445 #endif 446 447 icp->icp_ic_all_size = ICP_PCINEW_SZ; 448 449 icp->icp_copy_cmd = icp_pcinew_copy_cmd; 450 icp->icp_get_status = icp_pcinew_get_status; 451 icp->icp_intr = icp_pcinew_intr; 452 icp->icp_release_event = icp_pcinew_release_event; 453 icp->icp_set_sema0 = icp_pcinew_set_sema0; 454 icp->icp_test_busy = icp_pcinew_test_busy; 455 456 break; 457 458 case ICP_MPR: 459 bus_space_write_4(dpmemt, dpmemh, ICP_MPR_IC, ICP_MPR_MAGIC); 460 if (bus_space_read_4(dpmemt, dpmemh, ICP_MPR_IC) != 461 ICP_MPR_MAGIC) { 462 aprint_error( 463 "cannot access DPMEM at 0x%lx (shadowed?)\n", 464 (u_long)dpmembase); 465 goto bail_out; 466 } 467 468 /* 469 * XXX Here the Linux driver has a weird remapping logic I 470 * don't understand. My controller does not need it, and I 471 * cannot see what purpose it serves, therefore I did not 472 * do anything similar. 473 */ 474 475 bus_space_set_region_4(dpmemt, dpmemh, ICP_I960_SZ, 0, 476 ICP_DPR_IF_SZ >> 2); 477 478 /* Disable everything. */ 479 bus_space_write_1(dpmemt, dpmemh, ICP_EDOOR_EN, 480 bus_space_read_1(dpmemt, dpmemh, ICP_EDOOR_EN) | 4); 481 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_EDOOR, 0xff); 482 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_STATUS, 483 0); 484 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_CMD_INDEX, 485 0); 486 487 bus_space_write_4(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_INFO, 488 htole32(dpmembase)); 489 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_CMD_INDX, 490 0xff); 491 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_LDOOR, 1); 492 493 DELAY(20); 494 retries = 1000000; 495 while (bus_space_read_1(dpmemt, dpmemh, 496 ICP_MPR_IC + ICP_S_STATUS) != 0xff) { 497 if (--retries == 0) { 498 aprint_error("DEINIT failed\n"); 499 goto bail_out; 500 } 501 DELAY(1); 502 } 503 504 protocol = (u_int8_t)bus_space_read_4(dpmemt, dpmemh, 505 ICP_MPR_IC + ICP_S_INFO); 506 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_STATUS, 507 0); 508 if (protocol != ICP_PROTOCOL_VERSION) { 509 aprint_error("unsupported protocol %d\n", protocol); 510 goto bail_out; 511 } 512 513 /* special commnd to controller BIOS */ 514 bus_space_write_4(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_INFO, 0); 515 bus_space_write_4(dpmemt, dpmemh, 516 ICP_MPR_IC + ICP_S_INFO + sizeof(u_int32_t), 0); 517 bus_space_write_4(dpmemt, dpmemh, 518 ICP_MPR_IC + ICP_S_INFO + 2 * sizeof(u_int32_t), 1); 519 bus_space_write_4(dpmemt, dpmemh, 520 ICP_MPR_IC + ICP_S_INFO + 3 * sizeof(u_int32_t), 0); 521 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_CMD_INDX, 522 0xfe); 523 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_LDOOR, 1); 524 525 DELAY(20); 526 retries = 1000000; 527 while (bus_space_read_1(dpmemt, dpmemh, 528 ICP_MPR_IC + ICP_S_STATUS) != 0xfe) { 529 if (--retries == 0) { 530 aprint_error("initialization error\n"); 531 goto bail_out; 532 } 533 DELAY(1); 534 } 535 536 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_STATUS, 537 0); 538 539 icp->icp_copy_cmd = icp_mpr_copy_cmd; 540 icp->icp_get_status = icp_mpr_get_status; 541 icp->icp_intr = icp_mpr_intr; 542 icp->icp_release_event = icp_mpr_release_event; 543 icp->icp_set_sema0 = icp_mpr_set_sema0; 544 icp->icp_test_busy = icp_mpr_test_busy; 545 break; 546 } 547 548 if (pci_intr_map(pa, &ih)) { 549 aprint_error("couldn't map interrupt\n"); 550 goto bail_out; 551 } 552 intrstr = pci_intr_string(pa->pa_pc, ih); 553 icp->icp_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, icp_intr, icp); 554 if (icp->icp_ih == NULL) { 555 aprint_error("couldn't establish interrupt"); 556 if (intrstr != NULL) 557 aprint_normal(" at %s", intrstr); 558 aprint_normal("\n"); 559 goto bail_out; 560 } 561 status |= INTR_ESTABLISHED; 562 563 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) 564 aprint_normal("Intel Storage RAID controller\n"); 565 else 566 aprint_normal("ICP-Vortex RAID controller\n"); 567 568 icp->icp_pci_bus = pa->pa_bus; 569 icp->icp_pci_device = pa->pa_device; 570 icp->icp_pci_device_id = PCI_PRODUCT(pa->pa_id); 571 icp->icp_pci_subdevice_id = pci_conf_read(pa->pa_pc, pa->pa_tag, 572 PCI_SUBSYS_ID_REG); 573 574 if (icp_init(icp, intrstr)) 575 goto bail_out; 576 577 icp_pci_enable_intr(icp); 578 return; 579 580 bail_out: 581 if ((status & DPMEM_MAPPED) != 0) 582 bus_space_unmap(dpmemt, dpmemh, dpmemsize); 583 if ((status & IOMEM_MAPPED) != 0) 584 bus_space_unmap(iomemt, iomemh, iomembase); 585 if ((status & IO_MAPPED) != 0) 586 bus_space_unmap(iot, ioh, iosize); 587 if ((status & INTR_ESTABLISHED) != 0) 588 pci_intr_disestablish(pa->pa_pc, icp->icp_ih); 589 } 590 591 /* 592 * Enable interrupts. 593 */ 594 void 595 icp_pci_enable_intr(struct icp_softc *icp) 596 { 597 598 switch (ICP_CLASS(icp)) { 599 case ICP_PCI: 600 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_IRQDEL, 601 1); 602 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, 603 ICP_CMD_INDEX, 0); 604 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_IRQEN, 605 1); 606 break; 607 608 case ICP_PCINEW: 609 bus_space_write_1(icp->icp_iot, icp->icp_ioh, ICP_EDOOR_REG, 610 0xff); 611 bus_space_write_1(icp->icp_iot, icp->icp_ioh, ICP_CONTROL1, 3); 612 break; 613 614 case ICP_MPR: 615 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, 616 ICP_MPR_EDOOR, 0xff); 617 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_EDOOR_EN, 618 bus_space_read_1(icp->icp_dpmemt, icp->icp_dpmemh, 619 ICP_EDOOR_EN) & ~4); 620 break; 621 } 622 } 623 624 /* 625 * "Old" PCI controller-specific functions. 626 */ 627 628 void 629 icp_pci_copy_cmd(struct icp_softc *icp, struct icp_ccb *ccb) 630 { 631 632 /* XXX Not yet implemented */ 633 } 634 635 u_int8_t 636 icp_pci_get_status(struct icp_softc *icp) 637 { 638 639 /* XXX Not yet implemented */ 640 return (0); 641 } 642 643 void 644 icp_pci_intr(struct icp_softc *icp, struct icp_intr_ctx *ctx) 645 { 646 647 /* XXX Not yet implemented */ 648 } 649 650 void 651 icp_pci_release_event(struct icp_softc *icp, 652 struct icp_ccb *ccb) 653 { 654 655 /* XXX Not yet implemented */ 656 } 657 658 void 659 icp_pci_set_sema0(struct icp_softc *icp) 660 { 661 662 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_SEMA0, 1); 663 } 664 665 int 666 icp_pci_test_busy(struct icp_softc *icp) 667 { 668 669 /* XXX Not yet implemented */ 670 return (0); 671 } 672 673 /* 674 * "New" PCI controller-specific functions. 675 */ 676 677 void 678 icp_pcinew_copy_cmd(struct icp_softc *icp, 679 struct icp_ccb *ccb) 680 { 681 682 /* XXX Not yet implemented */ 683 } 684 685 u_int8_t 686 icp_pcinew_get_status(struct icp_softc *icp) 687 { 688 689 /* XXX Not yet implemented */ 690 return (0); 691 } 692 693 void 694 icp_pcinew_intr(struct icp_softc *icp, 695 struct icp_intr_ctx *ctx) 696 { 697 698 /* XXX Not yet implemented */ 699 } 700 701 void 702 icp_pcinew_release_event(struct icp_softc *icp, 703 struct icp_ccb *ccb) 704 { 705 706 /* XXX Not yet implemented */ 707 } 708 709 void 710 icp_pcinew_set_sema0(struct icp_softc *icp) 711 { 712 713 bus_space_write_1(icp->icp_iot, icp->icp_ioh, ICP_SEMA0_REG, 1); 714 } 715 716 int 717 icp_pcinew_test_busy(struct icp_softc *icp) 718 { 719 720 /* XXX Not yet implemented */ 721 return (0); 722 } 723 724 /* 725 * MPR PCI controller-specific functions 726 */ 727 728 void 729 icp_mpr_copy_cmd(struct icp_softc *icp, struct icp_ccb *ic) 730 { 731 732 bus_space_write_2(icp->icp_dpmemt, icp->icp_dpmemh, 733 ICP_MPR_IC + ICP_COMM_QUEUE + 0 * ICP_COMM_Q_SZ + ICP_OFFSET, 734 ICP_DPR_CMD); 735 bus_space_write_2(icp->icp_dpmemt, icp->icp_dpmemh, 736 ICP_MPR_IC + ICP_COMM_QUEUE + 0 * ICP_COMM_Q_SZ + ICP_SERV_ID, 737 ic->ic_service); 738 bus_space_write_region_4(icp->icp_dpmemt, icp->icp_dpmemh, 739 ICP_MPR_IC + ICP_DPR_CMD, (u_int32_t *)&ic->ic_cmd, 740 ic->ic_cmdlen >> 2); 741 } 742 743 u_int8_t 744 icp_mpr_get_status(struct icp_softc *icp) 745 { 746 747 return (bus_space_read_1(icp->icp_dpmemt, icp->icp_dpmemh, 748 ICP_MPR_EDOOR)); 749 } 750 751 void 752 icp_mpr_intr(struct icp_softc *icp, struct icp_intr_ctx *ctx) 753 { 754 755 if ((ctx->istatus & 0x80) != 0) { /* error flag */ 756 ctx->istatus &= ~0x80; 757 ctx->cmd_status = bus_space_read_2(icp->icp_dpmemt, 758 icp->icp_dpmemh, ICP_MPR_STATUS); 759 } else 760 ctx->cmd_status = ICP_S_OK; 761 762 ctx->service = bus_space_read_2(icp->icp_dpmemt, icp->icp_dpmemh, 763 ICP_MPR_SERVICE); 764 ctx->info = bus_space_read_4(icp->icp_dpmemt, icp->icp_dpmemh, 765 ICP_MPR_INFO); 766 ctx->info2 = bus_space_read_4(icp->icp_dpmemt, icp->icp_dpmemh, 767 ICP_MPR_INFO + sizeof(u_int32_t)); 768 769 if (ctx->istatus == ICP_ASYNCINDEX) { 770 if (ctx->service != ICP_SCREENSERVICE && 771 (icp->icp_fw_vers & 0xff) >= 0x1a) { 772 int i; 773 774 icp->icp_evt.severity = 775 bus_space_read_1(icp->icp_dpmemt, 776 icp->icp_dpmemh, ICP_SEVERITY); 777 for (i = 0; 778 i < sizeof(icp->icp_evt.event_string); i++) { 779 icp->icp_evt.event_string[i] = 780 bus_space_read_1(icp->icp_dpmemt, 781 icp->icp_dpmemh, ICP_EVT_BUF + i); 782 if (icp->icp_evt.event_string[i] == '\0') 783 break; 784 } 785 } 786 } 787 788 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_MPR_EDOOR, 789 0xff); 790 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_MPR_SEMA1, 0); 791 } 792 793 void 794 icp_mpr_release_event(struct icp_softc *icp, struct icp_ccb *ic) 795 { 796 797 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_MPR_LDOOR, 1); 798 } 799 800 void 801 icp_mpr_set_sema0(struct icp_softc *icp) 802 { 803 804 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_MPR_SEMA0, 1); 805 } 806 807 int 808 icp_mpr_test_busy(struct icp_softc *icp) 809 { 810 811 return (bus_space_read_1(icp->icp_dpmemt, icp->icp_dpmemh, 812 ICP_MPR_SEMA0) & 1); 813 } 814
Indexes created Thu Oct 02 10:09:58 GMT 2025