icp_pci.c revision 1.17
1 /* $NetBSD: icp_pci.c,v 1.17 2009/05/06 10:34:32 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1999, 2000 Niklas Hallqvist. All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by Niklas Hallqvist. 46 * 4. The name of the author may not be used to endorse or promote products 47 * derived from this software without specific prior written permission. 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 50 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 51 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 52 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 53 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 54 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 55 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 56 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 57 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 58 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 59 * 60 * from OpenBSD: icp_pci.c,v 1.11 2001/06/12 15:40:30 niklas Exp 61 */ 62 63 /* 64 * This driver would not have written if it was not for the hardware donations 65 * from both ICP-Vortex and ko.neT. I want to thank them for their support. 66 * 67 * Re-worked for NetBSD by Andrew Doran. Test hardware kindly supplied by 68 * Intel. 69 */ 70 71 #include <sys/cdefs.h> 72 __KERNEL_RCSID(0, "$NetBSD: icp_pci.c,v 1.17 2009/05/06 10:34:32 cegger Exp $"); 73 74 #include <sys/param.h> 75 #include <sys/systm.h> 76 #include <sys/device.h> 77 #include <sys/kernel.h> 78 #include <sys/queue.h> 79 #include <sys/buf.h> 80 #include <sys/endian.h> 81 #include <sys/conf.h> 82 83 #include <uvm/uvm_extern.h> 84 85 #include <sys/bus.h> 86 87 #include <dev/pci/pcireg.h> 88 #include <dev/pci/pcivar.h> 89 #include <dev/pci/pcidevs.h> 90 91 #include <dev/ic/icpreg.h> 92 #include <dev/ic/icpvar.h> 93 94 /* Product numbers for Fibre-Channel are greater than or equal to 0x200 */ 95 #define ICP_PCI_PRODUCT_FC 0x200 96 97 /* Mapping registers for various areas */ 98 #define ICP_PCI_DPMEM 0x10 99 #define ICP_PCINEW_IOMEM 0x10 100 #define ICP_PCINEW_IO 0x14 101 #define ICP_PCINEW_DPMEM 0x18 102 103 /* PCI SRAM structure */ 104 #define ICP_MAGIC 0x00 /* u_int32_t, controller ID from BIOS */ 105 #define ICP_NEED_DEINIT 0x04 /* u_int16_t, switch between BIOS/driver */ 106 #define ICP_SWITCH_SUPPORT 0x06 /* u_int8_t, see ICP_NEED_DEINIT */ 107 #define ICP_OS_USED 0x10 /* u_int8_t [16], OS code per service */ 108 #define ICP_FW_MAGIC 0x3c /* u_int8_t, controller ID from firmware */ 109 #define ICP_SRAM_SZ 0x40 110 111 /* DPRAM PCI controllers */ 112 #define ICP_DPR_IF 0x00 /* interface area */ 113 #define ICP_6SR (0xff0 - ICP_SRAM_SZ) 114 #define ICP_SEMA1 0xff1 /* volatile u_int8_t, command semaphore */ 115 #define ICP_IRQEN 0xff5 /* u_int8_t, board interrupts enable */ 116 #define ICP_EVENT 0xff8 /* u_int8_t, release event */ 117 #define ICP_IRQDEL 0xffc /* u_int8_t, acknowledge board interrupt */ 118 #define ICP_DPRAM_SZ 0x1000 119 120 /* PLX register structure (new PCI controllers) */ 121 #define ICP_CFG_REG 0x00 /* u_int8_t, DPRAM cfg. (2: < 1MB, 0: any) */ 122 #define ICP_SEMA0_REG 0x40 /* volatile u_int8_t, command semaphore */ 123 #define ICP_SEMA1_REG 0x41 /* volatile u_int8_t, status semaphore */ 124 #define ICP_PLX_STATUS 0x44 /* volatile u_int16_t, command status */ 125 #define ICP_PLX_SERVICE 0x46 /* u_int16_t, service */ 126 #define ICP_PLX_INFO 0x48 /* u_int32_t [2], additional info */ 127 #define ICP_LDOOR_REG 0x60 /* u_int8_t, PCI to local doorbell */ 128 #define ICP_EDOOR_REG 0x64 /* volatile u_int8_t, local to PCI doorbell */ 129 #define ICP_CONTROL0 0x68 /* u_int8_t, control0 register (unused) */ 130 #define ICP_CONTROL1 0x69 /* u_int8_t, board interrupts enable */ 131 #define ICP_PLX_SZ 0x80 132 133 /* DPRAM new PCI controllers */ 134 #define ICP_IC 0x00 /* interface */ 135 #define ICP_PCINEW_6SR (0x4000 - ICP_SRAM_SZ) 136 /* SRAM structure */ 137 #define ICP_PCINEW_SZ 0x4000 138 139 /* i960 register structure (PCI MPR controllers) */ 140 #define ICP_MPR_SEMA0 0x10 /* volatile u_int8_t, command semaphore */ 141 #define ICP_MPR_SEMA1 0x12 /* volatile u_int8_t, status semaphore */ 142 #define ICP_MPR_STATUS 0x14 /* volatile u_int16_t, command status */ 143 #define ICP_MPR_SERVICE 0x16 /* u_int16_t, service */ 144 #define ICP_MPR_INFO 0x18 /* u_int32_t [2], additional info */ 145 #define ICP_MPR_LDOOR 0x20 /* u_int8_t, PCI to local doorbell */ 146 #define ICP_MPR_EDOOR 0x2c /* volatile u_int8_t, locl to PCI doorbell */ 147 #define ICP_EDOOR_EN 0x34 /* u_int8_t, board interrupts enable */ 148 #define ICP_SEVERITY 0xefc /* u_int8_t, event severity */ 149 #define ICP_EVT_BUF 0xf00 /* u_int8_t [256], event buffer */ 150 #define ICP_I960_SZ 0x1000 151 152 /* DPRAM PCI MPR controllers */ 153 #define ICP_I960R 0x00 /* 4KB i960 registers */ 154 #define ICP_MPR_IC ICP_I960_SZ 155 /* interface area */ 156 #define ICP_MPR_6SR (ICP_I960_SZ + 0x3000 - ICP_SRAM_SZ) 157 /* SRAM structure */ 158 #define ICP_MPR_SZ 0x4000 159 160 int icp_pci_match(device_t, cfdata_t, void *); 161 void icp_pci_attach(device_t, device_t, void *); 162 void icp_pci_enable_intr(struct icp_softc *); 163 int icp_pci_find_class(struct pci_attach_args *); 164 165 void icp_pci_copy_cmd(struct icp_softc *, struct icp_ccb *); 166 u_int8_t icp_pci_get_status(struct icp_softc *); 167 void icp_pci_intr(struct icp_softc *, struct icp_intr_ctx *); 168 void icp_pci_release_event(struct icp_softc *, struct icp_ccb *); 169 void icp_pci_set_sema0(struct icp_softc *); 170 int icp_pci_test_busy(struct icp_softc *); 171 172 void icp_pcinew_copy_cmd(struct icp_softc *, struct icp_ccb *); 173 u_int8_t icp_pcinew_get_status(struct icp_softc *); 174 void icp_pcinew_intr(struct icp_softc *, struct icp_intr_ctx *); 175 void icp_pcinew_release_event(struct icp_softc *, struct icp_ccb *); 176 void icp_pcinew_set_sema0(struct icp_softc *); 177 int icp_pcinew_test_busy(struct icp_softc *); 178 179 void icp_mpr_copy_cmd(struct icp_softc *, struct icp_ccb *); 180 u_int8_t icp_mpr_get_status(struct icp_softc *); 181 void icp_mpr_intr(struct icp_softc *, struct icp_intr_ctx *); 182 void icp_mpr_release_event(struct icp_softc *, struct icp_ccb *); 183 void icp_mpr_set_sema0(struct icp_softc *); 184 int icp_mpr_test_busy(struct icp_softc *); 185 186 CFATTACH_DECL(icp_pci, sizeof(struct icp_softc), 187 icp_pci_match, icp_pci_attach, NULL, NULL); 188 189 struct icp_pci_ident { 190 u_short gpi_vendor; 191 u_short gpi_product; 192 u_short gpi_class; 193 } const icp_pci_ident[] = { 194 { PCI_VENDOR_VORTEX, PCI_PRODUCT_VORTEX_GDT_60x0, ICP_PCI }, 195 { PCI_VENDOR_VORTEX, PCI_PRODUCT_VORTEX_GDT_6000B, ICP_PCI }, 196 197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GDT_RAID1, ICP_MPR }, 198 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GDT_RAID2, ICP_MPR }, 199 }; 200 201 int 202 icp_pci_find_class(struct pci_attach_args *pa) 203 { 204 const struct icp_pci_ident *gpi, *maxgpi; 205 206 gpi = icp_pci_ident; 207 maxgpi = gpi + sizeof(icp_pci_ident) / sizeof(icp_pci_ident[0]); 208 209 for (; gpi < maxgpi; gpi++) 210 if (PCI_VENDOR(pa->pa_id) == gpi->gpi_vendor && 211 PCI_PRODUCT(pa->pa_id) == gpi->gpi_product) 212 return (gpi->gpi_class); 213 214 /* 215 * ICP-Vortex only make RAID controllers, so we employ a heuristic 216 * to match unlisted boards. 217 */ 218 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VORTEX) 219 return (PCI_PRODUCT(pa->pa_id) < 0x100 ? ICP_PCINEW : ICP_MPR); 220 221 return (-1); 222 } 223 224 int 225 icp_pci_match(device_t parent, cfdata_t match, void *aux) 226 { 227 struct pci_attach_args *pa; 228 229 pa = aux; 230 231 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 232 return (0); 233 234 return (icp_pci_find_class(pa) != -1); 235 } 236 237 void 238 icp_pci_attach(device_t parent, device_t self, void *aux) 239 { 240 struct pci_attach_args *pa; 241 struct icp_softc *icp; 242 bus_space_tag_t dpmemt, iomemt, iot; 243 bus_space_handle_t dpmemh, iomemh, ioh; 244 bus_addr_t dpmembase, iomembase, iobase; 245 bus_size_t dpmemsize, iomemsize, iosize; 246 u_int32_t status; 247 #define DPMEM_MAPPED 1 248 #define IOMEM_MAPPED 2 249 #define IO_MAPPED 4 250 #define INTR_ESTABLISHED 8 251 int retries; 252 u_int8_t protocol; 253 pci_intr_handle_t ih; 254 const char *intrstr; 255 256 pa = aux; 257 status = 0; 258 icp = (struct icp_softc *)self; 259 icp->icp_class = icp_pci_find_class(pa); 260 261 aprint_naive(": RAID controller\n"); 262 aprint_normal(": "); 263 264 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VORTEX && 265 PCI_PRODUCT(pa->pa_id) >= ICP_PCI_PRODUCT_FC) 266 icp->icp_class |= ICP_FC; 267 268 if (pci_mapreg_map(pa, 269 ICP_CLASS(icp) == ICP_PCINEW ? ICP_PCINEW_DPMEM : ICP_PCI_DPMEM, 270 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, &dpmemt, 271 &dpmemh, &dpmembase, &dpmemsize)) { 272 if (pci_mapreg_map(pa, 273 ICP_CLASS(icp) == ICP_PCINEW ? ICP_PCINEW_DPMEM : 274 ICP_PCI_DPMEM, 275 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M, 0, 276 &dpmemt, &dpmemh, &dpmembase, &dpmemsize)) { 277 aprint_error("cannot map DPMEM\n"); 278 goto bail_out; 279 } 280 } 281 status |= DPMEM_MAPPED; 282 icp->icp_dpmemt = dpmemt; 283 icp->icp_dpmemh = dpmemh; 284 icp->icp_dpmembase = dpmembase; 285 icp->icp_dmat = pa->pa_dmat; 286 287 /* 288 * The ICP_PCINEW series also has two other regions to map. 289 */ 290 if (ICP_CLASS(icp) == ICP_PCINEW) { 291 if (pci_mapreg_map(pa, ICP_PCINEW_IOMEM, PCI_MAPREG_TYPE_MEM, 292 0, &iomemt, &iomemh, &iomembase, &iomemsize)) { 293 aprint_error("cannot map memory mapped I/O ports\n"); 294 goto bail_out; 295 } 296 status |= IOMEM_MAPPED; 297 298 if (pci_mapreg_map(pa, ICP_PCINEW_IO, PCI_MAPREG_TYPE_IO, 0, 299 &iot, &ioh, &iobase, &iosize)) { 300 aprint_error("cannot map I/O ports\n"); 301 goto bail_out; 302 } 303 status |= IO_MAPPED; 304 icp->icp_iot = iot; 305 icp->icp_ioh = ioh; 306 icp->icp_iobase = iobase; 307 } 308 309 switch (ICP_CLASS(icp)) { 310 case ICP_PCI: 311 bus_space_set_region_4(dpmemt, dpmemh, 0, 0, 312 ICP_DPR_IF_SZ >> 2); 313 if (bus_space_read_1(dpmemt, dpmemh, 0) != 0) { 314 aprint_error("cannot write to DPMEM\n"); 315 goto bail_out; 316 } 317 318 #if 0 319 /* disable board interrupts, deinit services */ 320 icph_writeb(0xff, &dp6_ptr->io.irqdel); 321 icph_writeb(0x00, &dp6_ptr->io.irqen); 322 icph_writeb(0x00, &dp6_ptr->u.ic.S_Status); 323 icph_writeb(0x00, &dp6_ptr->u.ic.Cmd_Index); 324 325 icph_writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]); 326 icph_writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx); 327 icph_writeb(0, &dp6_ptr->io.event); 328 retries = INIT_RETRIES; 329 icph_delay(20); 330 while (icph_readb(&dp6_ptr->u.ic.S_Status) != 0xff) { 331 if (--retries == 0) { 332 printk("initialization error (DEINIT failed)\n"); 333 icph_munmap(ha->brd); 334 return 0; 335 } 336 icph_delay(1); 337 } 338 prot_ver = (unchar)icph_readl(&dp6_ptr->u.ic.S_Info[0]); 339 icph_writeb(0, &dp6_ptr->u.ic.S_Status); 340 icph_writeb(0xff, &dp6_ptr->io.irqdel); 341 if (prot_ver != PROTOCOL_VERSION) { 342 printk("illegal protocol version\n"); 343 icph_munmap(ha->brd); 344 return 0; 345 } 346 347 ha->type = ICP_PCI; 348 ha->ic_all_size = sizeof(dp6_ptr->u); 349 350 /* special command to controller BIOS */ 351 icph_writel(0x00, &dp6_ptr->u.ic.S_Info[0]); 352 icph_writel(0x00, &dp6_ptr->u.ic.S_Info[1]); 353 icph_writel(0x01, &dp6_ptr->u.ic.S_Info[2]); 354 icph_writel(0x00, &dp6_ptr->u.ic.S_Info[3]); 355 icph_writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx); 356 icph_writeb(0, &dp6_ptr->io.event); 357 retries = INIT_RETRIES; 358 icph_delay(20); 359 while (icph_readb(&dp6_ptr->u.ic.S_Status) != 0xfe) { 360 if (--retries == 0) { 361 printk("initialization error\n"); 362 icph_munmap(ha->brd); 363 return 0; 364 } 365 icph_delay(1); 366 } 367 icph_writeb(0, &dp6_ptr->u.ic.S_Status); 368 icph_writeb(0xff, &dp6_ptr->io.irqdel); 369 #endif 370 371 icp->icp_ic_all_size = ICP_DPRAM_SZ; 372 373 icp->icp_copy_cmd = icp_pci_copy_cmd; 374 icp->icp_get_status = icp_pci_get_status; 375 icp->icp_intr = icp_pci_intr; 376 icp->icp_release_event = icp_pci_release_event; 377 icp->icp_set_sema0 = icp_pci_set_sema0; 378 icp->icp_test_busy = icp_pci_test_busy; 379 380 break; 381 382 case ICP_PCINEW: 383 bus_space_set_region_4(dpmemt, dpmemh, 0, 0, 384 ICP_DPR_IF_SZ >> 2); 385 if (bus_space_read_1(dpmemt, dpmemh, 0) != 0) { 386 aprint_error("cannot write to DPMEM\n"); 387 goto bail_out; 388 } 389 390 #if 0 391 /* disable board interrupts, deinit services */ 392 outb(0x00,PTR2USHORT(&ha->plx->control1)); 393 outb(0xff,PTR2USHORT(&ha->plx->edoor_reg)); 394 395 icph_writeb(0x00, &dp6c_ptr->u.ic.S_Status); 396 icph_writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index); 397 398 icph_writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]); 399 icph_writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx); 400 401 outb(1,PTR2USHORT(&ha->plx->ldoor_reg)); 402 403 retries = INIT_RETRIES; 404 icph_delay(20); 405 while (icph_readb(&dp6c_ptr->u.ic.S_Status) != 0xff) { 406 if (--retries == 0) { 407 printk("initialization error (DEINIT failed)\n"); 408 icph_munmap(ha->brd); 409 return 0; 410 } 411 icph_delay(1); 412 } 413 prot_ver = (unchar)icph_readl(&dp6c_ptr->u.ic.S_Info[0]); 414 icph_writeb(0, &dp6c_ptr->u.ic.Status); 415 if (prot_ver != PROTOCOL_VERSION) { 416 printk("illegal protocol version\n"); 417 icph_munmap(ha->brd); 418 return 0; 419 } 420 421 ha->type = ICP_PCINEW; 422 ha->ic_all_size = sizeof(dp6c_ptr->u); 423 424 /* special command to controller BIOS */ 425 icph_writel(0x00, &dp6c_ptr->u.ic.S_Info[0]); 426 icph_writel(0x00, &dp6c_ptr->u.ic.S_Info[1]); 427 icph_writel(0x01, &dp6c_ptr->u.ic.S_Info[2]); 428 icph_writel(0x00, &dp6c_ptr->u.ic.S_Info[3]); 429 icph_writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx); 430 431 outb(1,PTR2USHORT(&ha->plx->ldoor_reg)); 432 433 retries = INIT_RETRIES; 434 icph_delay(20); 435 while (icph_readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) { 436 if (--retries == 0) { 437 printk("initialization error\n"); 438 icph_munmap(ha->brd); 439 return 0; 440 } 441 icph_delay(1); 442 } 443 icph_writeb(0, &dp6c_ptr->u.ic.S_Status); 444 #endif 445 446 icp->icp_ic_all_size = ICP_PCINEW_SZ; 447 448 icp->icp_copy_cmd = icp_pcinew_copy_cmd; 449 icp->icp_get_status = icp_pcinew_get_status; 450 icp->icp_intr = icp_pcinew_intr; 451 icp->icp_release_event = icp_pcinew_release_event; 452 icp->icp_set_sema0 = icp_pcinew_set_sema0; 453 icp->icp_test_busy = icp_pcinew_test_busy; 454 455 break; 456 457 case ICP_MPR: 458 bus_space_write_4(dpmemt, dpmemh, ICP_MPR_IC, ICP_MPR_MAGIC); 459 if (bus_space_read_4(dpmemt, dpmemh, ICP_MPR_IC) != 460 ICP_MPR_MAGIC) { 461 aprint_error( 462 "cannot access DPMEM at 0x%lx (shadowed?)\n", 463 (u_long)dpmembase); 464 goto bail_out; 465 } 466 467 /* 468 * XXX Here the Linux driver has a weird remapping logic I 469 * don't understand. My controller does not need it, and I 470 * cannot see what purpose it serves, therefore I did not 471 * do anything similar. 472 */ 473 474 bus_space_set_region_4(dpmemt, dpmemh, ICP_I960_SZ, 0, 475 ICP_DPR_IF_SZ >> 2); 476 477 /* Disable everything. */ 478 bus_space_write_1(dpmemt, dpmemh, ICP_EDOOR_EN, 479 bus_space_read_1(dpmemt, dpmemh, ICP_EDOOR_EN) | 4); 480 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_EDOOR, 0xff); 481 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_STATUS, 482 0); 483 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_CMD_INDEX, 484 0); 485 486 bus_space_write_4(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_INFO, 487 htole32(dpmembase)); 488 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_CMD_INDX, 489 0xff); 490 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_LDOOR, 1); 491 492 DELAY(20); 493 retries = 1000000; 494 while (bus_space_read_1(dpmemt, dpmemh, 495 ICP_MPR_IC + ICP_S_STATUS) != 0xff) { 496 if (--retries == 0) { 497 aprint_error("DEINIT failed\n"); 498 goto bail_out; 499 } 500 DELAY(1); 501 } 502 503 protocol = (u_int8_t)bus_space_read_4(dpmemt, dpmemh, 504 ICP_MPR_IC + ICP_S_INFO); 505 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_STATUS, 506 0); 507 if (protocol != ICP_PROTOCOL_VERSION) { 508 aprint_error("unsupported protocol %d\n", protocol); 509 goto bail_out; 510 } 511 512 /* special commnd to controller BIOS */ 513 bus_space_write_4(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_INFO, 0); 514 bus_space_write_4(dpmemt, dpmemh, 515 ICP_MPR_IC + ICP_S_INFO + sizeof(u_int32_t), 0); 516 bus_space_write_4(dpmemt, dpmemh, 517 ICP_MPR_IC + ICP_S_INFO + 2 * sizeof(u_int32_t), 1); 518 bus_space_write_4(dpmemt, dpmemh, 519 ICP_MPR_IC + ICP_S_INFO + 3 * sizeof(u_int32_t), 0); 520 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_CMD_INDX, 521 0xfe); 522 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_LDOOR, 1); 523 524 DELAY(20); 525 retries = 1000000; 526 while (bus_space_read_1(dpmemt, dpmemh, 527 ICP_MPR_IC + ICP_S_STATUS) != 0xfe) { 528 if (--retries == 0) { 529 aprint_error("initialization error\n"); 530 goto bail_out; 531 } 532 DELAY(1); 533 } 534 535 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_STATUS, 536 0); 537 538 icp->icp_copy_cmd = icp_mpr_copy_cmd; 539 icp->icp_get_status = icp_mpr_get_status; 540 icp->icp_intr = icp_mpr_intr; 541 icp->icp_release_event = icp_mpr_release_event; 542 icp->icp_set_sema0 = icp_mpr_set_sema0; 543 icp->icp_test_busy = icp_mpr_test_busy; 544 break; 545 } 546 547 if (pci_intr_map(pa, &ih)) { 548 aprint_error("couldn't map interrupt\n"); 549 goto bail_out; 550 } 551 intrstr = pci_intr_string(pa->pa_pc, ih); 552 icp->icp_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, icp_intr, icp); 553 if (icp->icp_ih == NULL) { 554 aprint_error("couldn't establish interrupt"); 555 if (intrstr != NULL) 556 aprint_normal(" at %s", intrstr); 557 aprint_normal("\n"); 558 goto bail_out; 559 } 560 status |= INTR_ESTABLISHED; 561 562 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) 563 aprint_normal("Intel Storage RAID controller\n"); 564 else 565 aprint_normal("ICP-Vortex RAID controller\n"); 566 567 icp->icp_pci_bus = pa->pa_bus; 568 icp->icp_pci_device = pa->pa_device; 569 icp->icp_pci_device_id = PCI_PRODUCT(pa->pa_id); 570 icp->icp_pci_subdevice_id = pci_conf_read(pa->pa_pc, pa->pa_tag, 571 PCI_SUBSYS_ID_REG); 572 573 if (icp_init(icp, intrstr)) 574 goto bail_out; 575 576 icp_pci_enable_intr(icp); 577 return; 578 579 bail_out: 580 if ((status & DPMEM_MAPPED) != 0) 581 bus_space_unmap(dpmemt, dpmemh, dpmemsize); 582 if ((status & IOMEM_MAPPED) != 0) 583 bus_space_unmap(iomemt, iomemh, iomembase); 584 if ((status & IO_MAPPED) != 0) 585 bus_space_unmap(iot, ioh, iosize); 586 if ((status & INTR_ESTABLISHED) != 0) 587 pci_intr_disestablish(pa->pa_pc, icp->icp_ih); 588 } 589 590 /* 591 * Enable interrupts. 592 */ 593 void 594 icp_pci_enable_intr(struct icp_softc *icp) 595 { 596 597 switch (ICP_CLASS(icp)) { 598 case ICP_PCI: 599 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_IRQDEL, 600 1); 601 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, 602 ICP_CMD_INDEX, 0); 603 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_IRQEN, 604 1); 605 break; 606 607 case ICP_PCINEW: 608 bus_space_write_1(icp->icp_iot, icp->icp_ioh, ICP_EDOOR_REG, 609 0xff); 610 bus_space_write_1(icp->icp_iot, icp->icp_ioh, ICP_CONTROL1, 3); 611 break; 612 613 case ICP_MPR: 614 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, 615 ICP_MPR_EDOOR, 0xff); 616 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_EDOOR_EN, 617 bus_space_read_1(icp->icp_dpmemt, icp->icp_dpmemh, 618 ICP_EDOOR_EN) & ~4); 619 break; 620 } 621 } 622 623 /* 624 * "Old" PCI controller-specific functions. 625 */ 626 627 void 628 icp_pci_copy_cmd(struct icp_softc *icp, struct icp_ccb *ccb) 629 { 630 631 /* XXX Not yet implemented */ 632 } 633 634 u_int8_t 635 icp_pci_get_status(struct icp_softc *icp) 636 { 637 638 /* XXX Not yet implemented */ 639 return (0); 640 } 641 642 void 643 icp_pci_intr(struct icp_softc *icp, struct icp_intr_ctx *ctx) 644 { 645 646 /* XXX Not yet implemented */ 647 } 648 649 void 650 icp_pci_release_event(struct icp_softc *icp, 651 struct icp_ccb *ccb) 652 { 653 654 /* XXX Not yet implemented */ 655 } 656 657 void 658 icp_pci_set_sema0(struct icp_softc *icp) 659 { 660 661 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_SEMA0, 1); 662 } 663 664 int 665 icp_pci_test_busy(struct icp_softc *icp) 666 { 667 668 /* XXX Not yet implemented */ 669 return (0); 670 } 671 672 /* 673 * "New" PCI controller-specific functions. 674 */ 675 676 void 677 icp_pcinew_copy_cmd(struct icp_softc *icp, 678 struct icp_ccb *ccb) 679 { 680 681 /* XXX Not yet implemented */ 682 } 683 684 u_int8_t 685 icp_pcinew_get_status(struct icp_softc *icp) 686 { 687 688 /* XXX Not yet implemented */ 689 return (0); 690 } 691 692 void 693 icp_pcinew_intr(struct icp_softc *icp, 694 struct icp_intr_ctx *ctx) 695 { 696 697 /* XXX Not yet implemented */ 698 } 699 700 void 701 icp_pcinew_release_event(struct icp_softc *icp, 702 struct icp_ccb *ccb) 703 { 704 705 /* XXX Not yet implemented */ 706 } 707 708 void 709 icp_pcinew_set_sema0(struct icp_softc *icp) 710 { 711 712 bus_space_write_1(icp->icp_iot, icp->icp_ioh, ICP_SEMA0_REG, 1); 713 } 714 715 int 716 icp_pcinew_test_busy(struct icp_softc *icp) 717 { 718 719 /* XXX Not yet implemented */ 720 return (0); 721 } 722 723 /* 724 * MPR PCI controller-specific functions 725 */ 726 727 void 728 icp_mpr_copy_cmd(struct icp_softc *icp, struct icp_ccb *ic) 729 { 730 731 bus_space_write_2(icp->icp_dpmemt, icp->icp_dpmemh, 732 ICP_MPR_IC + ICP_COMM_QUEUE + 0 * ICP_COMM_Q_SZ + ICP_OFFSET, 733 ICP_DPR_CMD); 734 bus_space_write_2(icp->icp_dpmemt, icp->icp_dpmemh, 735 ICP_MPR_IC + ICP_COMM_QUEUE + 0 * ICP_COMM_Q_SZ + ICP_SERV_ID, 736 ic->ic_service); 737 bus_space_write_region_4(icp->icp_dpmemt, icp->icp_dpmemh, 738 ICP_MPR_IC + ICP_DPR_CMD, (u_int32_t *)&ic->ic_cmd, 739 ic->ic_cmdlen >> 2); 740 } 741 742 u_int8_t 743 icp_mpr_get_status(struct icp_softc *icp) 744 { 745 746 return (bus_space_read_1(icp->icp_dpmemt, icp->icp_dpmemh, 747 ICP_MPR_EDOOR)); 748 } 749 750 void 751 icp_mpr_intr(struct icp_softc *icp, struct icp_intr_ctx *ctx) 752 { 753 754 if ((ctx->istatus & 0x80) != 0) { /* error flag */ 755 ctx->istatus &= ~0x80; 756 ctx->cmd_status = bus_space_read_2(icp->icp_dpmemt, 757 icp->icp_dpmemh, ICP_MPR_STATUS); 758 } else 759 ctx->cmd_status = ICP_S_OK; 760 761 ctx->service = bus_space_read_2(icp->icp_dpmemt, icp->icp_dpmemh, 762 ICP_MPR_SERVICE); 763 ctx->info = bus_space_read_4(icp->icp_dpmemt, icp->icp_dpmemh, 764 ICP_MPR_INFO); 765 ctx->info2 = bus_space_read_4(icp->icp_dpmemt, icp->icp_dpmemh, 766 ICP_MPR_INFO + sizeof(u_int32_t)); 767 768 if (ctx->istatus == ICP_ASYNCINDEX) { 769 if (ctx->service != ICP_SCREENSERVICE && 770 (icp->icp_fw_vers & 0xff) >= 0x1a) { 771 int i; 772 773 icp->icp_evt.severity = 774 bus_space_read_1(icp->icp_dpmemt, 775 icp->icp_dpmemh, ICP_SEVERITY); 776 for (i = 0; 777 i < sizeof(icp->icp_evt.event_string); i++) { 778 icp->icp_evt.event_string[i] = 779 bus_space_read_1(icp->icp_dpmemt, 780 icp->icp_dpmemh, ICP_EVT_BUF + i); 781 if (icp->icp_evt.event_string[i] == '\0') 782 break; 783 } 784 } 785 } 786 787 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_MPR_EDOOR, 788 0xff); 789 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_MPR_SEMA1, 0); 790 } 791 792 void 793 icp_mpr_release_event(struct icp_softc *icp, struct icp_ccb *ic) 794 { 795 796 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_MPR_LDOOR, 1); 797 } 798 799 void 800 icp_mpr_set_sema0(struct icp_softc *icp) 801 { 802 803 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_MPR_SEMA0, 1); 804 } 805 806 int 807 icp_mpr_test_busy(struct icp_softc *icp) 808 { 809 810 return (bus_space_read_1(icp->icp_dpmemt, icp->icp_dpmemh, 811 ICP_MPR_SEMA0) & 1); 812 } 813
Indexes created Mon Sep 29 21:09:56 GMT 2025