icp_pci.c revision 1.21
1 /* $NetBSD: icp_pci.c,v 1.21 2012/10/27 17:18:32 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1999, 2000 Niklas Hallqvist. All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by Niklas Hallqvist. 46 * 4. The name of the author may not be used to endorse or promote products 47 * derived from this software without specific prior written permission. 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 50 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 51 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 52 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 53 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 54 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 55 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 56 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 57 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 58 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 59 * 60 * from OpenBSD: icp_pci.c,v 1.11 2001/06/12 15:40:30 niklas Exp 61 */ 62 63 /* 64 * This driver would not have written if it was not for the hardware donations 65 * from both ICP-Vortex and ko.neT. I want to thank them for their support. 66 * 67 * Re-worked for NetBSD by Andrew Doran. Test hardware kindly supplied by 68 * Intel. 69 */ 70 71 #include <sys/cdefs.h> 72 __KERNEL_RCSID(0, "$NetBSD: icp_pci.c,v 1.21 2012/10/27 17:18:32 chs Exp $"); 73 74 #include <sys/param.h> 75 #include <sys/systm.h> 76 #include <sys/device.h> 77 #include <sys/kernel.h> 78 #include <sys/queue.h> 79 #include <sys/buf.h> 80 #include <sys/endian.h> 81 #include <sys/conf.h> 82 83 #include <sys/bus.h> 84 85 #include <dev/pci/pcireg.h> 86 #include <dev/pci/pcivar.h> 87 #include <dev/pci/pcidevs.h> 88 89 #include <dev/ic/icpreg.h> 90 #include <dev/ic/icpvar.h> 91 92 /* Product numbers for Fibre-Channel are greater than or equal to 0x200 */ 93 #define ICP_PCI_PRODUCT_FC 0x200 94 95 /* Mapping registers for various areas */ 96 #define ICP_PCI_DPMEM 0x10 97 #define ICP_PCINEW_IOMEM 0x10 98 #define ICP_PCINEW_IO 0x14 99 #define ICP_PCINEW_DPMEM 0x18 100 101 /* PCI SRAM structure */ 102 #define ICP_MAGIC 0x00 /* u_int32_t, controller ID from BIOS */ 103 #define ICP_NEED_DEINIT 0x04 /* u_int16_t, switch between BIOS/driver */ 104 #define ICP_SWITCH_SUPPORT 0x06 /* u_int8_t, see ICP_NEED_DEINIT */ 105 #define ICP_OS_USED 0x10 /* u_int8_t [16], OS code per service */ 106 #define ICP_FW_MAGIC 0x3c /* u_int8_t, controller ID from firmware */ 107 #define ICP_SRAM_SZ 0x40 108 109 /* DPRAM PCI controllers */ 110 #define ICP_DPR_IF 0x00 /* interface area */ 111 #define ICP_6SR (0xff0 - ICP_SRAM_SZ) 112 #define ICP_SEMA1 0xff1 /* volatile u_int8_t, command semaphore */ 113 #define ICP_IRQEN 0xff5 /* u_int8_t, board interrupts enable */ 114 #define ICP_EVENT 0xff8 /* u_int8_t, release event */ 115 #define ICP_IRQDEL 0xffc /* u_int8_t, acknowledge board interrupt */ 116 #define ICP_DPRAM_SZ 0x1000 117 118 /* PLX register structure (new PCI controllers) */ 119 #define ICP_CFG_REG 0x00 /* u_int8_t, DPRAM cfg. (2: < 1MB, 0: any) */ 120 #define ICP_SEMA0_REG 0x40 /* volatile u_int8_t, command semaphore */ 121 #define ICP_SEMA1_REG 0x41 /* volatile u_int8_t, status semaphore */ 122 #define ICP_PLX_STATUS 0x44 /* volatile u_int16_t, command status */ 123 #define ICP_PLX_SERVICE 0x46 /* u_int16_t, service */ 124 #define ICP_PLX_INFO 0x48 /* u_int32_t [2], additional info */ 125 #define ICP_LDOOR_REG 0x60 /* u_int8_t, PCI to local doorbell */ 126 #define ICP_EDOOR_REG 0x64 /* volatile u_int8_t, local to PCI doorbell */ 127 #define ICP_CONTROL0 0x68 /* u_int8_t, control0 register (unused) */ 128 #define ICP_CONTROL1 0x69 /* u_int8_t, board interrupts enable */ 129 #define ICP_PLX_SZ 0x80 130 131 /* DPRAM new PCI controllers */ 132 #define ICP_IC 0x00 /* interface */ 133 #define ICP_PCINEW_6SR (0x4000 - ICP_SRAM_SZ) 134 /* SRAM structure */ 135 #define ICP_PCINEW_SZ 0x4000 136 137 /* i960 register structure (PCI MPR controllers) */ 138 #define ICP_MPR_SEMA0 0x10 /* volatile u_int8_t, command semaphore */ 139 #define ICP_MPR_SEMA1 0x12 /* volatile u_int8_t, status semaphore */ 140 #define ICP_MPR_STATUS 0x14 /* volatile u_int16_t, command status */ 141 #define ICP_MPR_SERVICE 0x16 /* u_int16_t, service */ 142 #define ICP_MPR_INFO 0x18 /* u_int32_t [2], additional info */ 143 #define ICP_MPR_LDOOR 0x20 /* u_int8_t, PCI to local doorbell */ 144 #define ICP_MPR_EDOOR 0x2c /* volatile u_int8_t, locl to PCI doorbell */ 145 #define ICP_EDOOR_EN 0x34 /* u_int8_t, board interrupts enable */ 146 #define ICP_SEVERITY 0xefc /* u_int8_t, event severity */ 147 #define ICP_EVT_BUF 0xf00 /* u_int8_t [256], event buffer */ 148 #define ICP_I960_SZ 0x1000 149 150 /* DPRAM PCI MPR controllers */ 151 #define ICP_I960R 0x00 /* 4KB i960 registers */ 152 #define ICP_MPR_IC ICP_I960_SZ 153 /* interface area */ 154 #define ICP_MPR_6SR (ICP_I960_SZ + 0x3000 - ICP_SRAM_SZ) 155 /* SRAM structure */ 156 #define ICP_MPR_SZ 0x4000 157 158 int icp_pci_match(device_t, cfdata_t, void *); 159 void icp_pci_attach(device_t, device_t, void *); 160 void icp_pci_enable_intr(struct icp_softc *); 161 int icp_pci_find_class(struct pci_attach_args *); 162 163 void icp_pci_copy_cmd(struct icp_softc *, struct icp_ccb *); 164 u_int8_t icp_pci_get_status(struct icp_softc *); 165 void icp_pci_intr(struct icp_softc *, struct icp_intr_ctx *); 166 void icp_pci_release_event(struct icp_softc *, struct icp_ccb *); 167 void icp_pci_set_sema0(struct icp_softc *); 168 int icp_pci_test_busy(struct icp_softc *); 169 170 void icp_pcinew_copy_cmd(struct icp_softc *, struct icp_ccb *); 171 u_int8_t icp_pcinew_get_status(struct icp_softc *); 172 void icp_pcinew_intr(struct icp_softc *, struct icp_intr_ctx *); 173 void icp_pcinew_release_event(struct icp_softc *, struct icp_ccb *); 174 void icp_pcinew_set_sema0(struct icp_softc *); 175 int icp_pcinew_test_busy(struct icp_softc *); 176 177 void icp_mpr_copy_cmd(struct icp_softc *, struct icp_ccb *); 178 u_int8_t icp_mpr_get_status(struct icp_softc *); 179 void icp_mpr_intr(struct icp_softc *, struct icp_intr_ctx *); 180 void icp_mpr_release_event(struct icp_softc *, struct icp_ccb *); 181 void icp_mpr_set_sema0(struct icp_softc *); 182 int icp_mpr_test_busy(struct icp_softc *); 183 184 CFATTACH_DECL_NEW(icp_pci, sizeof(struct icp_softc), 185 icp_pci_match, icp_pci_attach, NULL, NULL); 186 187 struct icp_pci_ident { 188 u_short gpi_vendor; 189 u_short gpi_product; 190 u_short gpi_class; 191 } const icp_pci_ident[] = { 192 { PCI_VENDOR_VORTEX, PCI_PRODUCT_VORTEX_GDT_60x0, ICP_PCI }, 193 { PCI_VENDOR_VORTEX, PCI_PRODUCT_VORTEX_GDT_6000B, ICP_PCI }, 194 195 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GDT_RAID1, ICP_MPR }, 196 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GDT_RAID2, ICP_MPR }, 197 }; 198 199 int 200 icp_pci_find_class(struct pci_attach_args *pa) 201 { 202 const struct icp_pci_ident *gpi, *maxgpi; 203 204 gpi = icp_pci_ident; 205 maxgpi = gpi + sizeof(icp_pci_ident) / sizeof(icp_pci_ident[0]); 206 207 for (; gpi < maxgpi; gpi++) 208 if (PCI_VENDOR(pa->pa_id) == gpi->gpi_vendor && 209 PCI_PRODUCT(pa->pa_id) == gpi->gpi_product) 210 return (gpi->gpi_class); 211 212 /* 213 * ICP-Vortex only make RAID controllers, so we employ a heuristic 214 * to match unlisted boards. 215 */ 216 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VORTEX) 217 return (PCI_PRODUCT(pa->pa_id) < 0x100 ? ICP_PCINEW : ICP_MPR); 218 219 return (-1); 220 } 221 222 int 223 icp_pci_match(device_t parent, cfdata_t match, void *aux) 224 { 225 struct pci_attach_args *pa; 226 227 pa = aux; 228 229 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 230 return (0); 231 232 return (icp_pci_find_class(pa) != -1); 233 } 234 235 void 236 icp_pci_attach(device_t parent, device_t self, void *aux) 237 { 238 struct pci_attach_args *pa; 239 struct icp_softc *icp; 240 bus_space_tag_t dpmemt, iomemt, iot; 241 bus_space_handle_t dpmemh, iomemh, ioh; 242 bus_addr_t dpmembase, iomembase, iobase; 243 bus_size_t dpmemsize, iomemsize, iosize; 244 u_int32_t status; 245 #define DPMEM_MAPPED 1 246 #define IOMEM_MAPPED 2 247 #define IO_MAPPED 4 248 #define INTR_ESTABLISHED 8 249 int retries; 250 u_int8_t protocol; 251 pci_intr_handle_t ih; 252 const char *intrstr; 253 254 pa = aux; 255 status = 0; 256 icp = device_private(self); 257 icp->icp_dv = self; 258 icp->icp_class = icp_pci_find_class(pa); 259 260 aprint_naive(": RAID controller\n"); 261 aprint_normal(": "); 262 263 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VORTEX && 264 PCI_PRODUCT(pa->pa_id) >= ICP_PCI_PRODUCT_FC) 265 icp->icp_class |= ICP_FC; 266 267 if (pci_mapreg_map(pa, 268 ICP_CLASS(icp) == ICP_PCINEW ? ICP_PCINEW_DPMEM : ICP_PCI_DPMEM, 269 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, &dpmemt, 270 &dpmemh, &dpmembase, &dpmemsize)) { 271 if (pci_mapreg_map(pa, 272 ICP_CLASS(icp) == ICP_PCINEW ? ICP_PCINEW_DPMEM : 273 ICP_PCI_DPMEM, 274 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M, 0, 275 &dpmemt, &dpmemh, &dpmembase, &dpmemsize)) { 276 aprint_error("cannot map DPMEM\n"); 277 goto bail_out; 278 } 279 } 280 status |= DPMEM_MAPPED; 281 icp->icp_dpmemt = dpmemt; 282 icp->icp_dpmemh = dpmemh; 283 icp->icp_dpmembase = dpmembase; 284 icp->icp_dmat = pa->pa_dmat; 285 286 /* 287 * The ICP_PCINEW series also has two other regions to map. 288 */ 289 if (ICP_CLASS(icp) == ICP_PCINEW) { 290 if (pci_mapreg_map(pa, ICP_PCINEW_IOMEM, PCI_MAPREG_TYPE_MEM, 291 0, &iomemt, &iomemh, &iomembase, &iomemsize)) { 292 aprint_error("cannot map memory mapped I/O ports\n"); 293 goto bail_out; 294 } 295 status |= IOMEM_MAPPED; 296 297 if (pci_mapreg_map(pa, ICP_PCINEW_IO, PCI_MAPREG_TYPE_IO, 0, 298 &iot, &ioh, &iobase, &iosize)) { 299 aprint_error("cannot map I/O ports\n"); 300 goto bail_out; 301 } 302 status |= IO_MAPPED; 303 icp->icp_iot = iot; 304 icp->icp_ioh = ioh; 305 icp->icp_iobase = iobase; 306 } 307 308 switch (ICP_CLASS(icp)) { 309 case ICP_PCI: 310 bus_space_set_region_4(dpmemt, dpmemh, 0, 0, 311 ICP_DPR_IF_SZ >> 2); 312 if (bus_space_read_1(dpmemt, dpmemh, 0) != 0) { 313 aprint_error("cannot write to DPMEM\n"); 314 goto bail_out; 315 } 316 317 #if 0 318 /* disable board interrupts, deinit services */ 319 icph_writeb(0xff, &dp6_ptr->io.irqdel); 320 icph_writeb(0x00, &dp6_ptr->io.irqen); 321 icph_writeb(0x00, &dp6_ptr->u.ic.S_Status); 322 icph_writeb(0x00, &dp6_ptr->u.ic.Cmd_Index); 323 324 icph_writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]); 325 icph_writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx); 326 icph_writeb(0, &dp6_ptr->io.event); 327 retries = INIT_RETRIES; 328 icph_delay(20); 329 while (icph_readb(&dp6_ptr->u.ic.S_Status) != 0xff) { 330 if (--retries == 0) { 331 printk("initialization error (DEINIT failed)\n"); 332 icph_munmap(ha->brd); 333 return 0; 334 } 335 icph_delay(1); 336 } 337 prot_ver = (unchar)icph_readl(&dp6_ptr->u.ic.S_Info[0]); 338 icph_writeb(0, &dp6_ptr->u.ic.S_Status); 339 icph_writeb(0xff, &dp6_ptr->io.irqdel); 340 if (prot_ver != PROTOCOL_VERSION) { 341 printk("illegal protocol version\n"); 342 icph_munmap(ha->brd); 343 return 0; 344 } 345 346 ha->type = ICP_PCI; 347 ha->ic_all_size = sizeof(dp6_ptr->u); 348 349 /* special command to controller BIOS */ 350 icph_writel(0x00, &dp6_ptr->u.ic.S_Info[0]); 351 icph_writel(0x00, &dp6_ptr->u.ic.S_Info[1]); 352 icph_writel(0x01, &dp6_ptr->u.ic.S_Info[2]); 353 icph_writel(0x00, &dp6_ptr->u.ic.S_Info[3]); 354 icph_writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx); 355 icph_writeb(0, &dp6_ptr->io.event); 356 retries = INIT_RETRIES; 357 icph_delay(20); 358 while (icph_readb(&dp6_ptr->u.ic.S_Status) != 0xfe) { 359 if (--retries == 0) { 360 printk("initialization error\n"); 361 icph_munmap(ha->brd); 362 return 0; 363 } 364 icph_delay(1); 365 } 366 icph_writeb(0, &dp6_ptr->u.ic.S_Status); 367 icph_writeb(0xff, &dp6_ptr->io.irqdel); 368 #endif 369 370 icp->icp_ic_all_size = ICP_DPRAM_SZ; 371 372 icp->icp_copy_cmd = icp_pci_copy_cmd; 373 icp->icp_get_status = icp_pci_get_status; 374 icp->icp_intr = icp_pci_intr; 375 icp->icp_release_event = icp_pci_release_event; 376 icp->icp_set_sema0 = icp_pci_set_sema0; 377 icp->icp_test_busy = icp_pci_test_busy; 378 379 break; 380 381 case ICP_PCINEW: 382 bus_space_set_region_4(dpmemt, dpmemh, 0, 0, 383 ICP_DPR_IF_SZ >> 2); 384 if (bus_space_read_1(dpmemt, dpmemh, 0) != 0) { 385 aprint_error("cannot write to DPMEM\n"); 386 goto bail_out; 387 } 388 389 #if 0 390 /* disable board interrupts, deinit services */ 391 outb(0x00,PTR2USHORT(&ha->plx->control1)); 392 outb(0xff,PTR2USHORT(&ha->plx->edoor_reg)); 393 394 icph_writeb(0x00, &dp6c_ptr->u.ic.S_Status); 395 icph_writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index); 396 397 icph_writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]); 398 icph_writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx); 399 400 outb(1,PTR2USHORT(&ha->plx->ldoor_reg)); 401 402 retries = INIT_RETRIES; 403 icph_delay(20); 404 while (icph_readb(&dp6c_ptr->u.ic.S_Status) != 0xff) { 405 if (--retries == 0) { 406 printk("initialization error (DEINIT failed)\n"); 407 icph_munmap(ha->brd); 408 return 0; 409 } 410 icph_delay(1); 411 } 412 prot_ver = (unchar)icph_readl(&dp6c_ptr->u.ic.S_Info[0]); 413 icph_writeb(0, &dp6c_ptr->u.ic.Status); 414 if (prot_ver != PROTOCOL_VERSION) { 415 printk("illegal protocol version\n"); 416 icph_munmap(ha->brd); 417 return 0; 418 } 419 420 ha->type = ICP_PCINEW; 421 ha->ic_all_size = sizeof(dp6c_ptr->u); 422 423 /* special command to controller BIOS */ 424 icph_writel(0x00, &dp6c_ptr->u.ic.S_Info[0]); 425 icph_writel(0x00, &dp6c_ptr->u.ic.S_Info[1]); 426 icph_writel(0x01, &dp6c_ptr->u.ic.S_Info[2]); 427 icph_writel(0x00, &dp6c_ptr->u.ic.S_Info[3]); 428 icph_writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx); 429 430 outb(1,PTR2USHORT(&ha->plx->ldoor_reg)); 431 432 retries = INIT_RETRIES; 433 icph_delay(20); 434 while (icph_readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) { 435 if (--retries == 0) { 436 printk("initialization error\n"); 437 icph_munmap(ha->brd); 438 return 0; 439 } 440 icph_delay(1); 441 } 442 icph_writeb(0, &dp6c_ptr->u.ic.S_Status); 443 #endif 444 445 icp->icp_ic_all_size = ICP_PCINEW_SZ; 446 447 icp->icp_copy_cmd = icp_pcinew_copy_cmd; 448 icp->icp_get_status = icp_pcinew_get_status; 449 icp->icp_intr = icp_pcinew_intr; 450 icp->icp_release_event = icp_pcinew_release_event; 451 icp->icp_set_sema0 = icp_pcinew_set_sema0; 452 icp->icp_test_busy = icp_pcinew_test_busy; 453 454 break; 455 456 case ICP_MPR: 457 bus_space_write_4(dpmemt, dpmemh, ICP_MPR_IC, ICP_MPR_MAGIC); 458 if (bus_space_read_4(dpmemt, dpmemh, ICP_MPR_IC) != 459 ICP_MPR_MAGIC) { 460 aprint_error( 461 "cannot access DPMEM at 0x%lx (shadowed?)\n", 462 (u_long)dpmembase); 463 goto bail_out; 464 } 465 466 /* 467 * XXX Here the Linux driver has a weird remapping logic I 468 * don't understand. My controller does not need it, and I 469 * cannot see what purpose it serves, therefore I did not 470 * do anything similar. 471 */ 472 473 bus_space_set_region_4(dpmemt, dpmemh, ICP_I960_SZ, 0, 474 ICP_DPR_IF_SZ >> 2); 475 476 /* Disable everything. */ 477 bus_space_write_1(dpmemt, dpmemh, ICP_EDOOR_EN, 478 bus_space_read_1(dpmemt, dpmemh, ICP_EDOOR_EN) | 4); 479 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_EDOOR, 0xff); 480 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_STATUS, 481 0); 482 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_CMD_INDEX, 483 0); 484 485 bus_space_write_4(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_INFO, 486 htole32(dpmembase)); 487 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_CMD_INDX, 488 0xff); 489 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_LDOOR, 1); 490 491 DELAY(20); 492 retries = 1000000; 493 while (bus_space_read_1(dpmemt, dpmemh, 494 ICP_MPR_IC + ICP_S_STATUS) != 0xff) { 495 if (--retries == 0) { 496 aprint_error("DEINIT failed\n"); 497 goto bail_out; 498 } 499 DELAY(1); 500 } 501 502 protocol = (u_int8_t)bus_space_read_4(dpmemt, dpmemh, 503 ICP_MPR_IC + ICP_S_INFO); 504 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_STATUS, 505 0); 506 if (protocol != ICP_PROTOCOL_VERSION) { 507 aprint_error("unsupported protocol %d\n", protocol); 508 goto bail_out; 509 } 510 511 /* special commnd to controller BIOS */ 512 bus_space_write_4(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_INFO, 0); 513 bus_space_write_4(dpmemt, dpmemh, 514 ICP_MPR_IC + ICP_S_INFO + sizeof(u_int32_t), 0); 515 bus_space_write_4(dpmemt, dpmemh, 516 ICP_MPR_IC + ICP_S_INFO + 2 * sizeof(u_int32_t), 1); 517 bus_space_write_4(dpmemt, dpmemh, 518 ICP_MPR_IC + ICP_S_INFO + 3 * sizeof(u_int32_t), 0); 519 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_CMD_INDX, 520 0xfe); 521 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_LDOOR, 1); 522 523 DELAY(20); 524 retries = 1000000; 525 while (bus_space_read_1(dpmemt, dpmemh, 526 ICP_MPR_IC + ICP_S_STATUS) != 0xfe) { 527 if (--retries == 0) { 528 aprint_error("initialization error\n"); 529 goto bail_out; 530 } 531 DELAY(1); 532 } 533 534 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_STATUS, 535 0); 536 537 icp->icp_copy_cmd = icp_mpr_copy_cmd; 538 icp->icp_get_status = icp_mpr_get_status; 539 icp->icp_intr = icp_mpr_intr; 540 icp->icp_release_event = icp_mpr_release_event; 541 icp->icp_set_sema0 = icp_mpr_set_sema0; 542 icp->icp_test_busy = icp_mpr_test_busy; 543 break; 544 } 545 546 if (pci_intr_map(pa, &ih)) { 547 aprint_error("couldn't map interrupt\n"); 548 goto bail_out; 549 } 550 intrstr = pci_intr_string(pa->pa_pc, ih); 551 icp->icp_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, icp_intr, icp); 552 if (icp->icp_ih == NULL) { 553 aprint_error("couldn't establish interrupt"); 554 if (intrstr != NULL) 555 aprint_error(" at %s", intrstr); 556 aprint_error("\n"); 557 goto bail_out; 558 } 559 status |= INTR_ESTABLISHED; 560 561 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) 562 aprint_normal("Intel Storage RAID controller\n"); 563 else 564 aprint_normal("ICP-Vortex RAID controller\n"); 565 566 icp->icp_pci_bus = pa->pa_bus; 567 icp->icp_pci_device = pa->pa_device; 568 icp->icp_pci_device_id = PCI_PRODUCT(pa->pa_id); 569 icp->icp_pci_subdevice_id = pci_conf_read(pa->pa_pc, pa->pa_tag, 570 PCI_SUBSYS_ID_REG); 571 572 if (icp_init(icp, intrstr)) 573 goto bail_out; 574 575 icp_pci_enable_intr(icp); 576 return; 577 578 bail_out: 579 if ((status & DPMEM_MAPPED) != 0) 580 bus_space_unmap(dpmemt, dpmemh, dpmemsize); 581 if ((status & IOMEM_MAPPED) != 0) 582 bus_space_unmap(iomemt, iomemh, iomembase); 583 if ((status & IO_MAPPED) != 0) 584 bus_space_unmap(iot, ioh, iosize); 585 if ((status & INTR_ESTABLISHED) != 0) 586 pci_intr_disestablish(pa->pa_pc, icp->icp_ih); 587 } 588 589 /* 590 * Enable interrupts. 591 */ 592 void 593 icp_pci_enable_intr(struct icp_softc *icp) 594 { 595 596 switch (ICP_CLASS(icp)) { 597 case ICP_PCI: 598 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_IRQDEL, 599 1); 600 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, 601 ICP_CMD_INDEX, 0); 602 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_IRQEN, 603 1); 604 break; 605 606 case ICP_PCINEW: 607 bus_space_write_1(icp->icp_iot, icp->icp_ioh, ICP_EDOOR_REG, 608 0xff); 609 bus_space_write_1(icp->icp_iot, icp->icp_ioh, ICP_CONTROL1, 3); 610 break; 611 612 case ICP_MPR: 613 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, 614 ICP_MPR_EDOOR, 0xff); 615 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_EDOOR_EN, 616 bus_space_read_1(icp->icp_dpmemt, icp->icp_dpmemh, 617 ICP_EDOOR_EN) & ~4); 618 break; 619 } 620 } 621 622 /* 623 * "Old" PCI controller-specific functions. 624 */ 625 626 void 627 icp_pci_copy_cmd(struct icp_softc *icp, struct icp_ccb *ccb) 628 { 629 630 /* XXX Not yet implemented */ 631 } 632 633 u_int8_t 634 icp_pci_get_status(struct icp_softc *icp) 635 { 636 637 /* XXX Not yet implemented */ 638 return (0); 639 } 640 641 void 642 icp_pci_intr(struct icp_softc *icp, struct icp_intr_ctx *ctx) 643 { 644 645 /* XXX Not yet implemented */ 646 } 647 648 void 649 icp_pci_release_event(struct icp_softc *icp, 650 struct icp_ccb *ccb) 651 { 652 653 /* XXX Not yet implemented */ 654 } 655 656 void 657 icp_pci_set_sema0(struct icp_softc *icp) 658 { 659 660 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_SEMA0, 1); 661 } 662 663 int 664 icp_pci_test_busy(struct icp_softc *icp) 665 { 666 667 /* XXX Not yet implemented */ 668 return (0); 669 } 670 671 /* 672 * "New" PCI controller-specific functions. 673 */ 674 675 void 676 icp_pcinew_copy_cmd(struct icp_softc *icp, 677 struct icp_ccb *ccb) 678 { 679 680 /* XXX Not yet implemented */ 681 } 682 683 u_int8_t 684 icp_pcinew_get_status(struct icp_softc *icp) 685 { 686 687 /* XXX Not yet implemented */ 688 return (0); 689 } 690 691 void 692 icp_pcinew_intr(struct icp_softc *icp, 693 struct icp_intr_ctx *ctx) 694 { 695 696 /* XXX Not yet implemented */ 697 } 698 699 void 700 icp_pcinew_release_event(struct icp_softc *icp, 701 struct icp_ccb *ccb) 702 { 703 704 /* XXX Not yet implemented */ 705 } 706 707 void 708 icp_pcinew_set_sema0(struct icp_softc *icp) 709 { 710 711 bus_space_write_1(icp->icp_iot, icp->icp_ioh, ICP_SEMA0_REG, 1); 712 } 713 714 int 715 icp_pcinew_test_busy(struct icp_softc *icp) 716 { 717 718 /* XXX Not yet implemented */ 719 return (0); 720 } 721 722 /* 723 * MPR PCI controller-specific functions 724 */ 725 726 void 727 icp_mpr_copy_cmd(struct icp_softc *icp, struct icp_ccb *ic) 728 { 729 730 bus_space_write_2(icp->icp_dpmemt, icp->icp_dpmemh, 731 ICP_MPR_IC + ICP_COMM_QUEUE + 0 * ICP_COMM_Q_SZ + ICP_OFFSET, 732 ICP_DPR_CMD); 733 bus_space_write_2(icp->icp_dpmemt, icp->icp_dpmemh, 734 ICP_MPR_IC + ICP_COMM_QUEUE + 0 * ICP_COMM_Q_SZ + ICP_SERV_ID, 735 ic->ic_service); 736 bus_space_write_region_4(icp->icp_dpmemt, icp->icp_dpmemh, 737 ICP_MPR_IC + ICP_DPR_CMD, (u_int32_t *)&ic->ic_cmd, 738 ic->ic_cmdlen >> 2); 739 } 740 741 u_int8_t 742 icp_mpr_get_status(struct icp_softc *icp) 743 { 744 745 return (bus_space_read_1(icp->icp_dpmemt, icp->icp_dpmemh, 746 ICP_MPR_EDOOR)); 747 } 748 749 void 750 icp_mpr_intr(struct icp_softc *icp, struct icp_intr_ctx *ctx) 751 { 752 753 if ((ctx->istatus & 0x80) != 0) { /* error flag */ 754 ctx->istatus &= ~0x80; 755 ctx->cmd_status = bus_space_read_2(icp->icp_dpmemt, 756 icp->icp_dpmemh, ICP_MPR_STATUS); 757 } else 758 ctx->cmd_status = ICP_S_OK; 759 760 ctx->service = bus_space_read_2(icp->icp_dpmemt, icp->icp_dpmemh, 761 ICP_MPR_SERVICE); 762 ctx->info = bus_space_read_4(icp->icp_dpmemt, icp->icp_dpmemh, 763 ICP_MPR_INFO); 764 ctx->info2 = bus_space_read_4(icp->icp_dpmemt, icp->icp_dpmemh, 765 ICP_MPR_INFO + sizeof(u_int32_t)); 766 767 if (ctx->istatus == ICP_ASYNCINDEX) { 768 if (ctx->service != ICP_SCREENSERVICE && 769 (icp->icp_fw_vers & 0xff) >= 0x1a) { 770 int i; 771 772 icp->icp_evt.severity = 773 bus_space_read_1(icp->icp_dpmemt, 774 icp->icp_dpmemh, ICP_SEVERITY); 775 for (i = 0; 776 i < sizeof(icp->icp_evt.event_string); i++) { 777 icp->icp_evt.event_string[i] = 778 bus_space_read_1(icp->icp_dpmemt, 779 icp->icp_dpmemh, ICP_EVT_BUF + i); 780 if (icp->icp_evt.event_string[i] == '\0') 781 break; 782 } 783 } 784 } 785 786 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_MPR_EDOOR, 787 0xff); 788 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_MPR_SEMA1, 0); 789 } 790 791 void 792 icp_mpr_release_event(struct icp_softc *icp, struct icp_ccb *ic) 793 { 794 795 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_MPR_LDOOR, 1); 796 } 797 798 void 799 icp_mpr_set_sema0(struct icp_softc *icp) 800 { 801 802 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_MPR_SEMA0, 1); 803 } 804 805 int 806 icp_mpr_test_busy(struct icp_softc *icp) 807 { 808 809 return (bus_space_read_1(icp->icp_dpmemt, icp->icp_dpmemh, 810 ICP_MPR_SEMA0) & 1); 811 } 812
Indexes created Mon Sep 29 21:09:56 GMT 2025