icp_pci.c revision 1.4
1 /* $NetBSD: icp_pci.c,v 1.4 2002/09/30 20:37:25 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1999, 2000 Niklas Hallqvist. All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Niklas Hallqvist. 53 * 4. The name of the author may not be used to endorse or promote products 54 * derived from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 57 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 58 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 59 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 60 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 61 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 62 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 63 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 64 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 65 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 66 * 67 * from OpenBSD: icp_pci.c,v 1.11 2001/06/12 15:40:30 niklas Exp 68 */ 69 70 /* 71 * This driver would not have written if it was not for the hardware donations 72 * from both ICP-Vortex and ko.neT. I want to thank them for their support. 73 * 74 * Re-worked for NetBSD by Andrew Doran. Test hardware kindly supplied by 75 * Intel. 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: icp_pci.c,v 1.4 2002/09/30 20:37:25 thorpej Exp $"); 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/device.h> 84 #include <sys/kernel.h> 85 #include <sys/queue.h> 86 #include <sys/buf.h> 87 #include <sys/endian.h> 88 #include <sys/conf.h> 89 90 #include <uvm/uvm_extern.h> 91 92 #include <machine/bus.h> 93 94 #include <dev/pci/pcireg.h> 95 #include <dev/pci/pcivar.h> 96 #include <dev/pci/pcidevs.h> 97 98 #include <dev/ic/icpreg.h> 99 #include <dev/ic/icpvar.h> 100 101 /* Product numbers for Fibre-Channel are greater than or equal to 0x200 */ 102 #define ICP_PCI_PRODUCT_FC 0x200 103 104 /* Mapping registers for various areas */ 105 #define ICP_PCI_DPMEM 0x10 106 #define ICP_PCINEW_IOMEM 0x10 107 #define ICP_PCINEW_IO 0x14 108 #define ICP_PCINEW_DPMEM 0x18 109 110 /* PCI SRAM structure */ 111 #define ICP_MAGIC 0x00 /* u_int32_t, controller ID from BIOS */ 112 #define ICP_NEED_DEINIT 0x04 /* u_int16_t, switch between BIOS/driver */ 113 #define ICP_SWITCH_SUPPORT 0x06 /* u_int8_t, see ICP_NEED_DEINIT */ 114 #define ICP_OS_USED 0x10 /* u_int8_t [16], OS code per service */ 115 #define ICP_FW_MAGIC 0x3c /* u_int8_t, controller ID from firmware */ 116 #define ICP_SRAM_SZ 0x40 117 118 /* DPRAM PCI controllers */ 119 #define ICP_DPR_IF 0x00 /* interface area */ 120 #define ICP_6SR (0xff0 - ICP_SRAM_SZ) 121 #define ICP_SEMA1 0xff1 /* volatile u_int8_t, command semaphore */ 122 #define ICP_IRQEN 0xff5 /* u_int8_t, board interrupts enable */ 123 #define ICP_EVENT 0xff8 /* u_int8_t, release event */ 124 #define ICP_IRQDEL 0xffc /* u_int8_t, acknowledge board interrupt */ 125 #define ICP_DPRAM_SZ 0x1000 126 127 /* PLX register structure (new PCI controllers) */ 128 #define ICP_CFG_REG 0x00 /* u_int8_t, DPRAM cfg. (2: < 1MB, 0: any) */ 129 #define ICP_SEMA0_REG 0x40 /* volatile u_int8_t, command semaphore */ 130 #define ICP_SEMA1_REG 0x41 /* volatile u_int8_t, status semaphore */ 131 #define ICP_PLX_STATUS 0x44 /* volatile u_int16_t, command status */ 132 #define ICP_PLX_SERVICE 0x46 /* u_int16_t, service */ 133 #define ICP_PLX_INFO 0x48 /* u_int32_t [2], additional info */ 134 #define ICP_LDOOR_REG 0x60 /* u_int8_t, PCI to local doorbell */ 135 #define ICP_EDOOR_REG 0x64 /* volatile u_int8_t, local to PCI doorbell */ 136 #define ICP_CONTROL0 0x68 /* u_int8_t, control0 register (unused) */ 137 #define ICP_CONTROL1 0x69 /* u_int8_t, board interrupts enable */ 138 #define ICP_PLX_SZ 0x80 139 140 /* DPRAM new PCI controllers */ 141 #define ICP_IC 0x00 /* interface */ 142 #define ICP_PCINEW_6SR (0x4000 - ICP_SRAM_SZ) 143 /* SRAM structure */ 144 #define ICP_PCINEW_SZ 0x4000 145 146 /* i960 register structure (PCI MPR controllers) */ 147 #define ICP_MPR_SEMA0 0x10 /* volatile u_int8_t, command semaphore */ 148 #define ICP_MPR_SEMA1 0x12 /* volatile u_int8_t, status semaphore */ 149 #define ICP_MPR_STATUS 0x14 /* volatile u_int16_t, command status */ 150 #define ICP_MPR_SERVICE 0x16 /* u_int16_t, service */ 151 #define ICP_MPR_INFO 0x18 /* u_int32_t [2], additional info */ 152 #define ICP_MPR_LDOOR 0x20 /* u_int8_t, PCI to local doorbell */ 153 #define ICP_MPR_EDOOR 0x2c /* volatile u_int8_t, locl to PCI doorbell */ 154 #define ICP_EDOOR_EN 0x34 /* u_int8_t, board interrupts enable */ 155 #define ICP_I960_SZ 0x1000 156 157 /* DPRAM PCI MPR controllers */ 158 #define ICP_I960R 0x00 /* 4KB i960 registers */ 159 #define ICP_MPR_IC ICP_I960_SZ 160 /* interface area */ 161 #define ICP_MPR_6SR (ICP_I960_SZ + 0x3000 - ICP_SRAM_SZ) 162 /* SRAM structure */ 163 #define ICP_MPR_SZ 0x4000 164 165 int icp_pci_match(struct device *, struct cfdata *, void *); 166 void icp_pci_attach(struct device *, struct device *, void *); 167 void icp_pci_enable_intr(struct icp_softc *); 168 int icp_pci_find_class(struct pci_attach_args *); 169 170 void icp_pci_copy_cmd(struct icp_softc *, struct icp_ccb *); 171 u_int8_t icp_pci_get_status(struct icp_softc *); 172 void icp_pci_intr(struct icp_softc *, struct icp_intr_ctx *); 173 void icp_pci_release_event(struct icp_softc *, struct icp_ccb *); 174 void icp_pci_set_sema0(struct icp_softc *); 175 int icp_pci_test_busy(struct icp_softc *); 176 177 void icp_pcinew_copy_cmd(struct icp_softc *, struct icp_ccb *); 178 u_int8_t icp_pcinew_get_status(struct icp_softc *); 179 void icp_pcinew_intr(struct icp_softc *, struct icp_intr_ctx *); 180 void icp_pcinew_release_event(struct icp_softc *, struct icp_ccb *); 181 void icp_pcinew_set_sema0(struct icp_softc *); 182 int icp_pcinew_test_busy(struct icp_softc *); 183 184 void icp_mpr_copy_cmd(struct icp_softc *, struct icp_ccb *); 185 u_int8_t icp_mpr_get_status(struct icp_softc *); 186 void icp_mpr_intr(struct icp_softc *, struct icp_intr_ctx *); 187 void icp_mpr_release_event(struct icp_softc *, struct icp_ccb *); 188 void icp_mpr_set_sema0(struct icp_softc *); 189 int icp_mpr_test_busy(struct icp_softc *); 190 191 CFATTACH_DECL(icp_pci, sizeof(struct icp_softc), 192 icp_pci_match, icp_pci_attach, NULL, NULL) 193 194 struct icp_pci_ident { 195 u_short gpi_vendor; 196 u_short gpi_product; 197 u_short gpi_class; 198 } const icp_pci_ident[] = { 199 { PCI_VENDOR_VORTEX, PCI_PRODUCT_VORTEX_GDT_60x0, ICP_PCI }, 200 { PCI_VENDOR_VORTEX, PCI_PRODUCT_VORTEX_GDT_6000B, ICP_PCI }, 201 202 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GDT_RAID1, ICP_MPR }, 203 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GDT_RAID2, ICP_MPR }, 204 }; 205 206 int 207 icp_pci_find_class(struct pci_attach_args *pa) 208 { 209 const struct icp_pci_ident *gpi, *maxgpi; 210 211 gpi = icp_pci_ident; 212 maxgpi = gpi + sizeof(icp_pci_ident) / sizeof(icp_pci_ident[0]); 213 214 for (; gpi < maxgpi; gpi++) 215 if (PCI_VENDOR(pa->pa_id) == gpi->gpi_vendor && 216 PCI_PRODUCT(pa->pa_id) == gpi->gpi_product) 217 return (gpi->gpi_class); 218 219 /* 220 * ICP-Vortex only make RAID controllers, so we employ a heuristic 221 * to match unlisted boards. 222 */ 223 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VORTEX) 224 return (PCI_PRODUCT(pa->pa_id) < 0x100 ? ICP_PCINEW : ICP_MPR); 225 226 return (-1); 227 } 228 229 int 230 icp_pci_match(struct device *parent, struct cfdata *match, void *aux) 231 { 232 struct pci_attach_args *pa; 233 234 pa = aux; 235 236 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 237 return (0); 238 239 return (icp_pci_find_class(pa) != -1); 240 } 241 242 void 243 icp_pci_attach(struct device *parent, struct device *self, void *aux) 244 { 245 struct pci_attach_args *pa; 246 struct icp_softc *icp; 247 bus_space_tag_t dpmemt, iomemt, iot; 248 bus_space_handle_t dpmemh, iomemh, ioh; 249 bus_addr_t dpmembase, iomembase, iobase; 250 bus_size_t dpmemsize, iomemsize, iosize; 251 u_int32_t status; 252 #define DPMEM_MAPPED 1 253 #define IOMEM_MAPPED 2 254 #define IO_MAPPED 4 255 #define INTR_ESTABLISHED 8 256 int retries; 257 u_int8_t protocol; 258 pci_intr_handle_t ih; 259 const char *intrstr; 260 261 pa = aux; 262 status = 0; 263 icp = (struct icp_softc *)self; 264 icp->icp_class = icp_pci_find_class(pa); 265 266 printf(": "); 267 268 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VORTEX && 269 PCI_PRODUCT(pa->pa_id) >= ICP_PCI_PRODUCT_FC) 270 icp->icp_class |= ICP_FC; 271 272 if (pci_mapreg_map(pa, 273 ICP_CLASS(icp) == ICP_PCINEW ? ICP_PCINEW_DPMEM : ICP_PCI_DPMEM, 274 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, &dpmemt, 275 &dpmemh, &dpmembase, &dpmemsize)) { 276 if (pci_mapreg_map(pa, 277 ICP_CLASS(icp) == ICP_PCINEW ? ICP_PCINEW_DPMEM : 278 ICP_PCI_DPMEM, 279 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M, 0, 280 &dpmemt, &dpmemh, &dpmembase, &dpmemsize)) { 281 printf("cannot map DPMEM\n"); 282 goto bail_out; 283 } 284 } 285 status |= DPMEM_MAPPED; 286 icp->icp_dpmemt = dpmemt; 287 icp->icp_dpmemh = dpmemh; 288 icp->icp_dpmembase = dpmembase; 289 icp->icp_dmat = pa->pa_dmat; 290 291 /* 292 * The ICP_PCINEW series also has two other regions to map. 293 */ 294 if (ICP_CLASS(icp) == ICP_PCINEW) { 295 if (pci_mapreg_map(pa, ICP_PCINEW_IOMEM, PCI_MAPREG_TYPE_MEM, 296 0, &iomemt, &iomemh, &iomembase, &iomemsize)) { 297 printf("cannot map memory mapped I/O ports\n"); 298 goto bail_out; 299 } 300 status |= IOMEM_MAPPED; 301 302 if (pci_mapreg_map(pa, ICP_PCINEW_IO, PCI_MAPREG_TYPE_IO, 0, 303 &iot, &ioh, &iobase, &iosize)) { 304 printf("cannot map I/O ports\n"); 305 goto bail_out; 306 } 307 status |= IO_MAPPED; 308 icp->icp_iot = iot; 309 icp->icp_ioh = ioh; 310 icp->icp_iobase = iobase; 311 } 312 313 switch (ICP_CLASS(icp)) { 314 case ICP_PCI: 315 bus_space_set_region_4(dpmemt, dpmemh, 0, 0, 316 ICP_DPR_IF_SZ >> 2); 317 if (bus_space_read_1(dpmemt, dpmemh, 0) != 0) { 318 printf("cannot write to DPMEM\n"); 319 goto bail_out; 320 } 321 322 #if 0 323 /* disable board interrupts, deinit services */ 324 icph_writeb(0xff, &dp6_ptr->io.irqdel); 325 icph_writeb(0x00, &dp6_ptr->io.irqen);; 326 icph_writeb(0x00, &dp6_ptr->u.ic.S_Status); 327 icph_writeb(0x00, &dp6_ptr->u.ic.Cmd_Index); 328 329 icph_writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]); 330 icph_writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx); 331 icph_writeb(0, &dp6_ptr->io.event); 332 retries = INIT_RETRIES; 333 icph_delay(20); 334 while (icph_readb(&dp6_ptr->u.ic.S_Status) != 0xff) { 335 if (--retries == 0) { 336 printk("initialization error (DEINIT failed)\n"); 337 icph_munmap(ha->brd); 338 return 0; 339 } 340 icph_delay(1); 341 } 342 prot_ver = (unchar)icph_readl(&dp6_ptr->u.ic.S_Info[0]); 343 icph_writeb(0, &dp6_ptr->u.ic.S_Status); 344 icph_writeb(0xff, &dp6_ptr->io.irqdel); 345 if (prot_ver != PROTOCOL_VERSION) { 346 printk("illegal protocol version\n"); 347 icph_munmap(ha->brd); 348 return 0; 349 } 350 351 ha->type = ICP_PCI; 352 ha->ic_all_size = sizeof(dp6_ptr->u); 353 354 /* special command to controller BIOS */ 355 icph_writel(0x00, &dp6_ptr->u.ic.S_Info[0]); 356 icph_writel(0x00, &dp6_ptr->u.ic.S_Info[1]); 357 icph_writel(0x01, &dp6_ptr->u.ic.S_Info[2]); 358 icph_writel(0x00, &dp6_ptr->u.ic.S_Info[3]); 359 icph_writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx); 360 icph_writeb(0, &dp6_ptr->io.event); 361 retries = INIT_RETRIES; 362 icph_delay(20); 363 while (icph_readb(&dp6_ptr->u.ic.S_Status) != 0xfe) { 364 if (--retries == 0) { 365 printk("initialization error\n"); 366 icph_munmap(ha->brd); 367 return 0; 368 } 369 icph_delay(1); 370 } 371 icph_writeb(0, &dp6_ptr->u.ic.S_Status); 372 icph_writeb(0xff, &dp6_ptr->io.irqdel); 373 #endif 374 375 icp->icp_ic_all_size = ICP_DPRAM_SZ; 376 377 icp->icp_copy_cmd = icp_pci_copy_cmd; 378 icp->icp_get_status = icp_pci_get_status; 379 icp->icp_intr = icp_pci_intr; 380 icp->icp_release_event = icp_pci_release_event; 381 icp->icp_set_sema0 = icp_pci_set_sema0; 382 icp->icp_test_busy = icp_pci_test_busy; 383 384 break; 385 386 case ICP_PCINEW: 387 bus_space_set_region_4(dpmemt, dpmemh, 0, 0, 388 ICP_DPR_IF_SZ >> 2); 389 if (bus_space_read_1(dpmemt, dpmemh, 0) != 0) { 390 printf("cannot write to DPMEM\n"); 391 goto bail_out; 392 } 393 394 #if 0 395 /* disable board interrupts, deinit services */ 396 outb(0x00,PTR2USHORT(&ha->plx->control1)); 397 outb(0xff,PTR2USHORT(&ha->plx->edoor_reg)); 398 399 icph_writeb(0x00, &dp6c_ptr->u.ic.S_Status); 400 icph_writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index); 401 402 icph_writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]); 403 icph_writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx); 404 405 outb(1,PTR2USHORT(&ha->plx->ldoor_reg)); 406 407 retries = INIT_RETRIES; 408 icph_delay(20); 409 while (icph_readb(&dp6c_ptr->u.ic.S_Status) != 0xff) { 410 if (--retries == 0) { 411 printk("initialization error (DEINIT failed)\n"); 412 icph_munmap(ha->brd); 413 return 0; 414 } 415 icph_delay(1); 416 } 417 prot_ver = (unchar)icph_readl(&dp6c_ptr->u.ic.S_Info[0]); 418 icph_writeb(0, &dp6c_ptr->u.ic.Status); 419 if (prot_ver != PROTOCOL_VERSION) { 420 printk("illegal protocol version\n"); 421 icph_munmap(ha->brd); 422 return 0; 423 } 424 425 ha->type = ICP_PCINEW; 426 ha->ic_all_size = sizeof(dp6c_ptr->u); 427 428 /* special command to controller BIOS */ 429 icph_writel(0x00, &dp6c_ptr->u.ic.S_Info[0]); 430 icph_writel(0x00, &dp6c_ptr->u.ic.S_Info[1]); 431 icph_writel(0x01, &dp6c_ptr->u.ic.S_Info[2]); 432 icph_writel(0x00, &dp6c_ptr->u.ic.S_Info[3]); 433 icph_writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx); 434 435 outb(1,PTR2USHORT(&ha->plx->ldoor_reg)); 436 437 retries = INIT_RETRIES; 438 icph_delay(20); 439 while (icph_readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) { 440 if (--retries == 0) { 441 printk("initialization error\n"); 442 icph_munmap(ha->brd); 443 return 0; 444 } 445 icph_delay(1); 446 } 447 icph_writeb(0, &dp6c_ptr->u.ic.S_Status); 448 #endif 449 450 icp->icp_ic_all_size = ICP_PCINEW_SZ; 451 452 icp->icp_copy_cmd = icp_pcinew_copy_cmd; 453 icp->icp_get_status = icp_pcinew_get_status; 454 icp->icp_intr = icp_pcinew_intr; 455 icp->icp_release_event = icp_pcinew_release_event; 456 icp->icp_set_sema0 = icp_pcinew_set_sema0; 457 icp->icp_test_busy = icp_pcinew_test_busy; 458 459 break; 460 461 case ICP_MPR: 462 bus_space_write_4(dpmemt, dpmemh, ICP_MPR_IC, ICP_MPR_MAGIC); 463 if (bus_space_read_4(dpmemt, dpmemh, ICP_MPR_IC) != 464 ICP_MPR_MAGIC) { 465 printf("cannot access DPMEM at 0x%lx (shadowed?)\n", 466 (u_long)dpmembase); 467 goto bail_out; 468 } 469 470 /* 471 * XXX Here the Linux driver has a weird remapping logic I 472 * don't understand. My controller does not need it, and I 473 * cannot see what purpose it serves, therefore I did not 474 * do anything similar. 475 */ 476 477 bus_space_set_region_4(dpmemt, dpmemh, ICP_I960_SZ, 0, 478 ICP_DPR_IF_SZ >> 2); 479 480 /* Disable everything. */ 481 bus_space_write_1(dpmemt, dpmemh, ICP_EDOOR_EN, 482 bus_space_read_1(dpmemt, dpmemh, ICP_EDOOR_EN) | 4); 483 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_EDOOR, 0xff); 484 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_STATUS, 485 0); 486 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_CMD_INDEX, 487 0); 488 489 bus_space_write_4(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_INFO, 490 htole32(dpmembase)); 491 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_CMD_INDX, 492 0xff); 493 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_LDOOR, 1); 494 495 DELAY(20); 496 retries = 1000000; 497 while (bus_space_read_1(dpmemt, dpmemh, 498 ICP_MPR_IC + ICP_S_STATUS) != 0xff) { 499 if (--retries == 0) { 500 printf("DEINIT failed\n"); 501 goto bail_out; 502 } 503 DELAY(1); 504 } 505 506 protocol = (u_int8_t)bus_space_read_4(dpmemt, dpmemh, 507 ICP_MPR_IC + ICP_S_INFO); 508 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_STATUS, 509 0); 510 if (protocol != ICP_PROTOCOL_VERSION) { 511 printf("unsupported protocol %d\n", protocol); 512 goto bail_out; 513 } 514 515 /* special commnd to controller BIOS */ 516 bus_space_write_4(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_INFO, 0); 517 bus_space_write_4(dpmemt, dpmemh, 518 ICP_MPR_IC + ICP_S_INFO + sizeof(u_int32_t), 0); 519 bus_space_write_4(dpmemt, dpmemh, 520 ICP_MPR_IC + ICP_S_INFO + 2 * sizeof(u_int32_t), 1); 521 bus_space_write_4(dpmemt, dpmemh, 522 ICP_MPR_IC + ICP_S_INFO + 3 * sizeof(u_int32_t), 0); 523 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_CMD_INDX, 524 0xfe); 525 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_LDOOR, 1); 526 527 DELAY(20); 528 retries = 1000000; 529 while (bus_space_read_1(dpmemt, dpmemh, 530 ICP_MPR_IC + ICP_S_STATUS) != 0xfe) { 531 if (--retries == 0) { 532 printf("initialization error\n"); 533 goto bail_out; 534 } 535 DELAY(1); 536 } 537 538 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_STATUS, 539 0); 540 541 icp->icp_copy_cmd = icp_mpr_copy_cmd; 542 icp->icp_get_status = icp_mpr_get_status; 543 icp->icp_intr = icp_mpr_intr; 544 icp->icp_release_event = icp_mpr_release_event; 545 icp->icp_set_sema0 = icp_mpr_set_sema0; 546 icp->icp_test_busy = icp_mpr_test_busy; 547 break; 548 } 549 550 if (pci_intr_map(pa, &ih)) { 551 printf("couldn't map interrupt\n"); 552 goto bail_out; 553 } 554 intrstr = pci_intr_string(pa->pa_pc, ih); 555 icp->icp_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, icp_intr, icp); 556 if (icp->icp_ih == NULL) { 557 printf("couldn't establish interrupt"); 558 if (intrstr != NULL) 559 printf(" at %s", intrstr); 560 printf("\n"); 561 goto bail_out; 562 } 563 status |= INTR_ESTABLISHED; 564 565 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) 566 printf("Intel Storage RAID controller\n"); 567 else 568 printf("ICP-Vortex RAID controller\n"); 569 570 if (icp_init(icp, intrstr)) 571 goto bail_out; 572 573 icp_pci_enable_intr(icp); 574 return; 575 576 bail_out: 577 if ((status & DPMEM_MAPPED) != 0) 578 bus_space_unmap(dpmemt, dpmemh, dpmemsize); 579 if ((status & IOMEM_MAPPED) != 0) 580 bus_space_unmap(iomemt, iomemh, iomembase); 581 if ((status & IO_MAPPED) != 0) 582 bus_space_unmap(iot, ioh, iosize); 583 if ((status & INTR_ESTABLISHED) != 0) 584 pci_intr_disestablish(pa->pa_pc, icp->icp_ih); 585 } 586 587 /* 588 * Enable interrupts. 589 */ 590 void 591 icp_pci_enable_intr(struct icp_softc *icp) 592 { 593 594 switch (ICP_CLASS(icp)) { 595 case ICP_PCI: 596 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_IRQDEL, 597 1); 598 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, 599 ICP_CMD_INDEX, 0); 600 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_IRQEN, 601 1); 602 break; 603 604 case ICP_PCINEW: 605 bus_space_write_1(icp->icp_iot, icp->icp_ioh, ICP_EDOOR_REG, 606 0xff); 607 bus_space_write_1(icp->icp_iot, icp->icp_ioh, ICP_CONTROL1, 3); 608 break; 609 610 case ICP_MPR: 611 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, 612 ICP_MPR_EDOOR, 0xff); 613 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_EDOOR_EN, 614 bus_space_read_1(icp->icp_dpmemt, icp->icp_dpmemh, 615 ICP_EDOOR_EN) & ~4); 616 break; 617 } 618 } 619 620 /* 621 * "Old" PCI controller-specific functions. 622 */ 623 624 void 625 icp_pci_copy_cmd(struct icp_softc *icp, struct icp_ccb *ccb) 626 { 627 628 /* XXX Not yet implemented */ 629 } 630 631 u_int8_t 632 icp_pci_get_status(struct icp_softc *icp) 633 { 634 635 /* XXX Not yet implemented */ 636 return (0); 637 } 638 639 void 640 icp_pci_intr(struct icp_softc *icp, struct icp_intr_ctx *ctx) 641 { 642 643 /* XXX Not yet implemented */ 644 } 645 646 void 647 icp_pci_release_event(struct icp_softc *icp, struct icp_ccb *ccb) 648 { 649 650 /* XXX Not yet implemented */ 651 } 652 653 void 654 icp_pci_set_sema0(struct icp_softc *icp) 655 { 656 657 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_SEMA0, 1); 658 } 659 660 int 661 icp_pci_test_busy(struct icp_softc *icp) 662 { 663 664 /* XXX Not yet implemented */ 665 return (0); 666 } 667 668 /* 669 * "New" PCI controller-specific functions. 670 */ 671 672 void 673 icp_pcinew_copy_cmd(struct icp_softc *icp, struct icp_ccb *ccb) 674 { 675 676 /* XXX Not yet implemented */ 677 } 678 679 u_int8_t 680 icp_pcinew_get_status(struct icp_softc *icp) 681 { 682 683 /* XXX Not yet implemented */ 684 return (0); 685 } 686 687 void 688 icp_pcinew_intr(struct icp_softc *icp, struct icp_intr_ctx *ctx) 689 { 690 691 /* XXX Not yet implemented */ 692 } 693 694 void 695 icp_pcinew_release_event(struct icp_softc *icp, struct icp_ccb *ccb) 696 { 697 698 /* XXX Not yet implemented */ 699 } 700 701 void 702 icp_pcinew_set_sema0(struct icp_softc *icp) 703 { 704 705 bus_space_write_1(icp->icp_iot, icp->icp_ioh, ICP_SEMA0_REG, 1); 706 } 707 708 int 709 icp_pcinew_test_busy(struct icp_softc *icp) 710 { 711 712 /* XXX Not yet implemented */ 713 return (0); 714 } 715 716 /* 717 * MPR PCI controller-specific functions 718 */ 719 720 void 721 icp_mpr_copy_cmd(struct icp_softc *icp, struct icp_ccb *ic) 722 { 723 724 bus_space_write_2(icp->icp_dpmemt, icp->icp_dpmemh, 725 ICP_MPR_IC + ICP_COMM_QUEUE + 0 * ICP_COMM_Q_SZ + ICP_OFFSET, 726 ICP_DPR_CMD); 727 bus_space_write_2(icp->icp_dpmemt, icp->icp_dpmemh, 728 ICP_MPR_IC + ICP_COMM_QUEUE + 0 * ICP_COMM_Q_SZ + ICP_SERV_ID, 729 ic->ic_service); 730 bus_space_write_region_4(icp->icp_dpmemt, icp->icp_dpmemh, 731 ICP_MPR_IC + ICP_DPR_CMD, (u_int32_t *)&ic->ic_cmd, 732 ic->ic_cmdlen >> 2); 733 } 734 735 u_int8_t 736 icp_mpr_get_status(struct icp_softc *icp) 737 { 738 739 return (bus_space_read_1(icp->icp_dpmemt, icp->icp_dpmemh, 740 ICP_MPR_EDOOR)); 741 } 742 743 void 744 icp_mpr_intr(struct icp_softc *icp, struct icp_intr_ctx *ctx) 745 { 746 747 if ((ctx->istatus & 0x80) != 0) { /* error flag */ 748 ctx->istatus &= ~0x80; 749 ctx->cmd_status = bus_space_read_2(icp->icp_dpmemt, 750 icp->icp_dpmemh, ICP_MPR_STATUS); 751 } else 752 ctx->cmd_status = ICP_S_OK; 753 754 ctx->service = bus_space_read_2(icp->icp_dpmemt, icp->icp_dpmemh, 755 ICP_MPR_SERVICE); 756 ctx->info = bus_space_read_4(icp->icp_dpmemt, icp->icp_dpmemh, 757 ICP_MPR_INFO); 758 ctx->info2 = bus_space_read_4(icp->icp_dpmemt, icp->icp_dpmemh, 759 ICP_MPR_INFO + sizeof(u_int32_t)); 760 761 /* 762 * XXX Read async event string here. 763 */ 764 765 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_MPR_EDOOR, 766 0xff); 767 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_MPR_SEMA1, 0); 768 } 769 770 void 771 icp_mpr_release_event(struct icp_softc *icp, struct icp_ccb *ic) 772 { 773 774 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_MPR_LDOOR, 1); 775 } 776 777 void 778 icp_mpr_set_sema0(struct icp_softc *icp) 779 { 780 781 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_MPR_SEMA0, 1); 782 } 783 784 int 785 icp_mpr_test_busy(struct icp_softc *icp) 786 { 787 788 return (bus_space_read_1(icp->icp_dpmemt, icp->icp_dpmemh, 789 ICP_MPR_SEMA0) & 1); 790 } 791
Indexes created Tue Sep 30 10:09:55 GMT 2025