icp_pci.c revision 1.7
1 /* $NetBSD: icp_pci.c,v 1.7 2003/01/31 00:07:42 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1999, 2000 Niklas Hallqvist. All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Niklas Hallqvist. 53 * 4. The name of the author may not be used to endorse or promote products 54 * derived from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 57 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 58 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 59 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 60 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 61 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 62 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 63 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 64 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 65 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 66 * 67 * from OpenBSD: icp_pci.c,v 1.11 2001/06/12 15:40:30 niklas Exp 68 */ 69 70 /* 71 * This driver would not have written if it was not for the hardware donations 72 * from both ICP-Vortex and ko.neT. I want to thank them for their support. 73 * 74 * Re-worked for NetBSD by Andrew Doran. Test hardware kindly supplied by 75 * Intel. 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: icp_pci.c,v 1.7 2003/01/31 00:07:42 thorpej Exp $"); 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/device.h> 84 #include <sys/kernel.h> 85 #include <sys/queue.h> 86 #include <sys/buf.h> 87 #include <sys/endian.h> 88 #include <sys/conf.h> 89 90 #include <uvm/uvm_extern.h> 91 92 #include <machine/bus.h> 93 94 #include <dev/pci/pcireg.h> 95 #include <dev/pci/pcivar.h> 96 #include <dev/pci/pcidevs.h> 97 98 #include <dev/ic/icpreg.h> 99 #include <dev/ic/icpvar.h> 100 101 /* Product numbers for Fibre-Channel are greater than or equal to 0x200 */ 102 #define ICP_PCI_PRODUCT_FC 0x200 103 104 /* Mapping registers for various areas */ 105 #define ICP_PCI_DPMEM 0x10 106 #define ICP_PCINEW_IOMEM 0x10 107 #define ICP_PCINEW_IO 0x14 108 #define ICP_PCINEW_DPMEM 0x18 109 110 /* PCI SRAM structure */ 111 #define ICP_MAGIC 0x00 /* u_int32_t, controller ID from BIOS */ 112 #define ICP_NEED_DEINIT 0x04 /* u_int16_t, switch between BIOS/driver */ 113 #define ICP_SWITCH_SUPPORT 0x06 /* u_int8_t, see ICP_NEED_DEINIT */ 114 #define ICP_OS_USED 0x10 /* u_int8_t [16], OS code per service */ 115 #define ICP_FW_MAGIC 0x3c /* u_int8_t, controller ID from firmware */ 116 #define ICP_SRAM_SZ 0x40 117 118 /* DPRAM PCI controllers */ 119 #define ICP_DPR_IF 0x00 /* interface area */ 120 #define ICP_6SR (0xff0 - ICP_SRAM_SZ) 121 #define ICP_SEMA1 0xff1 /* volatile u_int8_t, command semaphore */ 122 #define ICP_IRQEN 0xff5 /* u_int8_t, board interrupts enable */ 123 #define ICP_EVENT 0xff8 /* u_int8_t, release event */ 124 #define ICP_IRQDEL 0xffc /* u_int8_t, acknowledge board interrupt */ 125 #define ICP_DPRAM_SZ 0x1000 126 127 /* PLX register structure (new PCI controllers) */ 128 #define ICP_CFG_REG 0x00 /* u_int8_t, DPRAM cfg. (2: < 1MB, 0: any) */ 129 #define ICP_SEMA0_REG 0x40 /* volatile u_int8_t, command semaphore */ 130 #define ICP_SEMA1_REG 0x41 /* volatile u_int8_t, status semaphore */ 131 #define ICP_PLX_STATUS 0x44 /* volatile u_int16_t, command status */ 132 #define ICP_PLX_SERVICE 0x46 /* u_int16_t, service */ 133 #define ICP_PLX_INFO 0x48 /* u_int32_t [2], additional info */ 134 #define ICP_LDOOR_REG 0x60 /* u_int8_t, PCI to local doorbell */ 135 #define ICP_EDOOR_REG 0x64 /* volatile u_int8_t, local to PCI doorbell */ 136 #define ICP_CONTROL0 0x68 /* u_int8_t, control0 register (unused) */ 137 #define ICP_CONTROL1 0x69 /* u_int8_t, board interrupts enable */ 138 #define ICP_PLX_SZ 0x80 139 140 /* DPRAM new PCI controllers */ 141 #define ICP_IC 0x00 /* interface */ 142 #define ICP_PCINEW_6SR (0x4000 - ICP_SRAM_SZ) 143 /* SRAM structure */ 144 #define ICP_PCINEW_SZ 0x4000 145 146 /* i960 register structure (PCI MPR controllers) */ 147 #define ICP_MPR_SEMA0 0x10 /* volatile u_int8_t, command semaphore */ 148 #define ICP_MPR_SEMA1 0x12 /* volatile u_int8_t, status semaphore */ 149 #define ICP_MPR_STATUS 0x14 /* volatile u_int16_t, command status */ 150 #define ICP_MPR_SERVICE 0x16 /* u_int16_t, service */ 151 #define ICP_MPR_INFO 0x18 /* u_int32_t [2], additional info */ 152 #define ICP_MPR_LDOOR 0x20 /* u_int8_t, PCI to local doorbell */ 153 #define ICP_MPR_EDOOR 0x2c /* volatile u_int8_t, locl to PCI doorbell */ 154 #define ICP_EDOOR_EN 0x34 /* u_int8_t, board interrupts enable */ 155 #define ICP_I960_SZ 0x1000 156 157 /* DPRAM PCI MPR controllers */ 158 #define ICP_I960R 0x00 /* 4KB i960 registers */ 159 #define ICP_MPR_IC ICP_I960_SZ 160 /* interface area */ 161 #define ICP_MPR_6SR (ICP_I960_SZ + 0x3000 - ICP_SRAM_SZ) 162 /* SRAM structure */ 163 #define ICP_MPR_SZ 0x4000 164 165 int icp_pci_match(struct device *, struct cfdata *, void *); 166 void icp_pci_attach(struct device *, struct device *, void *); 167 void icp_pci_enable_intr(struct icp_softc *); 168 int icp_pci_find_class(struct pci_attach_args *); 169 170 void icp_pci_copy_cmd(struct icp_softc *, struct icp_ccb *); 171 u_int8_t icp_pci_get_status(struct icp_softc *); 172 void icp_pci_intr(struct icp_softc *, struct icp_intr_ctx *); 173 void icp_pci_release_event(struct icp_softc *, struct icp_ccb *); 174 void icp_pci_set_sema0(struct icp_softc *); 175 int icp_pci_test_busy(struct icp_softc *); 176 177 void icp_pcinew_copy_cmd(struct icp_softc *, struct icp_ccb *); 178 u_int8_t icp_pcinew_get_status(struct icp_softc *); 179 void icp_pcinew_intr(struct icp_softc *, struct icp_intr_ctx *); 180 void icp_pcinew_release_event(struct icp_softc *, struct icp_ccb *); 181 void icp_pcinew_set_sema0(struct icp_softc *); 182 int icp_pcinew_test_busy(struct icp_softc *); 183 184 void icp_mpr_copy_cmd(struct icp_softc *, struct icp_ccb *); 185 u_int8_t icp_mpr_get_status(struct icp_softc *); 186 void icp_mpr_intr(struct icp_softc *, struct icp_intr_ctx *); 187 void icp_mpr_release_event(struct icp_softc *, struct icp_ccb *); 188 void icp_mpr_set_sema0(struct icp_softc *); 189 int icp_mpr_test_busy(struct icp_softc *); 190 191 CFATTACH_DECL(icp_pci, sizeof(struct icp_softc), 192 icp_pci_match, icp_pci_attach, NULL, NULL); 193 194 struct icp_pci_ident { 195 u_short gpi_vendor; 196 u_short gpi_product; 197 u_short gpi_class; 198 } const icp_pci_ident[] = { 199 { PCI_VENDOR_VORTEX, PCI_PRODUCT_VORTEX_GDT_60x0, ICP_PCI }, 200 { PCI_VENDOR_VORTEX, PCI_PRODUCT_VORTEX_GDT_6000B, ICP_PCI }, 201 202 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GDT_RAID1, ICP_MPR }, 203 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GDT_RAID2, ICP_MPR }, 204 }; 205 206 int 207 icp_pci_find_class(struct pci_attach_args *pa) 208 { 209 const struct icp_pci_ident *gpi, *maxgpi; 210 211 gpi = icp_pci_ident; 212 maxgpi = gpi + sizeof(icp_pci_ident) / sizeof(icp_pci_ident[0]); 213 214 for (; gpi < maxgpi; gpi++) 215 if (PCI_VENDOR(pa->pa_id) == gpi->gpi_vendor && 216 PCI_PRODUCT(pa->pa_id) == gpi->gpi_product) 217 return (gpi->gpi_class); 218 219 /* 220 * ICP-Vortex only make RAID controllers, so we employ a heuristic 221 * to match unlisted boards. 222 */ 223 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VORTEX) 224 return (PCI_PRODUCT(pa->pa_id) < 0x100 ? ICP_PCINEW : ICP_MPR); 225 226 return (-1); 227 } 228 229 int 230 icp_pci_match(struct device *parent, struct cfdata *match, void *aux) 231 { 232 struct pci_attach_args *pa; 233 234 pa = aux; 235 236 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 237 return (0); 238 239 return (icp_pci_find_class(pa) != -1); 240 } 241 242 void 243 icp_pci_attach(struct device *parent, struct device *self, void *aux) 244 { 245 struct pci_attach_args *pa; 246 struct icp_softc *icp; 247 bus_space_tag_t dpmemt, iomemt, iot; 248 bus_space_handle_t dpmemh, iomemh, ioh; 249 bus_addr_t dpmembase, iomembase, iobase; 250 bus_size_t dpmemsize, iomemsize, iosize; 251 u_int32_t status; 252 #define DPMEM_MAPPED 1 253 #define IOMEM_MAPPED 2 254 #define IO_MAPPED 4 255 #define INTR_ESTABLISHED 8 256 int retries; 257 u_int8_t protocol; 258 pci_intr_handle_t ih; 259 const char *intrstr; 260 261 pa = aux; 262 status = 0; 263 icp = (struct icp_softc *)self; 264 icp->icp_class = icp_pci_find_class(pa); 265 266 aprint_naive(": RAID controller\n"); 267 aprint_normal(": "); 268 269 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VORTEX && 270 PCI_PRODUCT(pa->pa_id) >= ICP_PCI_PRODUCT_FC) 271 icp->icp_class |= ICP_FC; 272 273 if (pci_mapreg_map(pa, 274 ICP_CLASS(icp) == ICP_PCINEW ? ICP_PCINEW_DPMEM : ICP_PCI_DPMEM, 275 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, &dpmemt, 276 &dpmemh, &dpmembase, &dpmemsize)) { 277 if (pci_mapreg_map(pa, 278 ICP_CLASS(icp) == ICP_PCINEW ? ICP_PCINEW_DPMEM : 279 ICP_PCI_DPMEM, 280 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M, 0, 281 &dpmemt, &dpmemh, &dpmembase, &dpmemsize)) { 282 aprint_error("cannot map DPMEM\n"); 283 goto bail_out; 284 } 285 } 286 status |= DPMEM_MAPPED; 287 icp->icp_dpmemt = dpmemt; 288 icp->icp_dpmemh = dpmemh; 289 icp->icp_dpmembase = dpmembase; 290 icp->icp_dmat = pa->pa_dmat; 291 292 /* 293 * The ICP_PCINEW series also has two other regions to map. 294 */ 295 if (ICP_CLASS(icp) == ICP_PCINEW) { 296 if (pci_mapreg_map(pa, ICP_PCINEW_IOMEM, PCI_MAPREG_TYPE_MEM, 297 0, &iomemt, &iomemh, &iomembase, &iomemsize)) { 298 aprint_error("cannot map memory mapped I/O ports\n"); 299 goto bail_out; 300 } 301 status |= IOMEM_MAPPED; 302 303 if (pci_mapreg_map(pa, ICP_PCINEW_IO, PCI_MAPREG_TYPE_IO, 0, 304 &iot, &ioh, &iobase, &iosize)) { 305 aprint_error("cannot map I/O ports\n"); 306 goto bail_out; 307 } 308 status |= IO_MAPPED; 309 icp->icp_iot = iot; 310 icp->icp_ioh = ioh; 311 icp->icp_iobase = iobase; 312 } 313 314 switch (ICP_CLASS(icp)) { 315 case ICP_PCI: 316 bus_space_set_region_4(dpmemt, dpmemh, 0, 0, 317 ICP_DPR_IF_SZ >> 2); 318 if (bus_space_read_1(dpmemt, dpmemh, 0) != 0) { 319 aprint_error("cannot write to DPMEM\n"); 320 goto bail_out; 321 } 322 323 #if 0 324 /* disable board interrupts, deinit services */ 325 icph_writeb(0xff, &dp6_ptr->io.irqdel); 326 icph_writeb(0x00, &dp6_ptr->io.irqen); 327 icph_writeb(0x00, &dp6_ptr->u.ic.S_Status); 328 icph_writeb(0x00, &dp6_ptr->u.ic.Cmd_Index); 329 330 icph_writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]); 331 icph_writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx); 332 icph_writeb(0, &dp6_ptr->io.event); 333 retries = INIT_RETRIES; 334 icph_delay(20); 335 while (icph_readb(&dp6_ptr->u.ic.S_Status) != 0xff) { 336 if (--retries == 0) { 337 printk("initialization error (DEINIT failed)\n"); 338 icph_munmap(ha->brd); 339 return 0; 340 } 341 icph_delay(1); 342 } 343 prot_ver = (unchar)icph_readl(&dp6_ptr->u.ic.S_Info[0]); 344 icph_writeb(0, &dp6_ptr->u.ic.S_Status); 345 icph_writeb(0xff, &dp6_ptr->io.irqdel); 346 if (prot_ver != PROTOCOL_VERSION) { 347 printk("illegal protocol version\n"); 348 icph_munmap(ha->brd); 349 return 0; 350 } 351 352 ha->type = ICP_PCI; 353 ha->ic_all_size = sizeof(dp6_ptr->u); 354 355 /* special command to controller BIOS */ 356 icph_writel(0x00, &dp6_ptr->u.ic.S_Info[0]); 357 icph_writel(0x00, &dp6_ptr->u.ic.S_Info[1]); 358 icph_writel(0x01, &dp6_ptr->u.ic.S_Info[2]); 359 icph_writel(0x00, &dp6_ptr->u.ic.S_Info[3]); 360 icph_writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx); 361 icph_writeb(0, &dp6_ptr->io.event); 362 retries = INIT_RETRIES; 363 icph_delay(20); 364 while (icph_readb(&dp6_ptr->u.ic.S_Status) != 0xfe) { 365 if (--retries == 0) { 366 printk("initialization error\n"); 367 icph_munmap(ha->brd); 368 return 0; 369 } 370 icph_delay(1); 371 } 372 icph_writeb(0, &dp6_ptr->u.ic.S_Status); 373 icph_writeb(0xff, &dp6_ptr->io.irqdel); 374 #endif 375 376 icp->icp_ic_all_size = ICP_DPRAM_SZ; 377 378 icp->icp_copy_cmd = icp_pci_copy_cmd; 379 icp->icp_get_status = icp_pci_get_status; 380 icp->icp_intr = icp_pci_intr; 381 icp->icp_release_event = icp_pci_release_event; 382 icp->icp_set_sema0 = icp_pci_set_sema0; 383 icp->icp_test_busy = icp_pci_test_busy; 384 385 break; 386 387 case ICP_PCINEW: 388 bus_space_set_region_4(dpmemt, dpmemh, 0, 0, 389 ICP_DPR_IF_SZ >> 2); 390 if (bus_space_read_1(dpmemt, dpmemh, 0) != 0) { 391 aprint_error("cannot write to DPMEM\n"); 392 goto bail_out; 393 } 394 395 #if 0 396 /* disable board interrupts, deinit services */ 397 outb(0x00,PTR2USHORT(&ha->plx->control1)); 398 outb(0xff,PTR2USHORT(&ha->plx->edoor_reg)); 399 400 icph_writeb(0x00, &dp6c_ptr->u.ic.S_Status); 401 icph_writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index); 402 403 icph_writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]); 404 icph_writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx); 405 406 outb(1,PTR2USHORT(&ha->plx->ldoor_reg)); 407 408 retries = INIT_RETRIES; 409 icph_delay(20); 410 while (icph_readb(&dp6c_ptr->u.ic.S_Status) != 0xff) { 411 if (--retries == 0) { 412 printk("initialization error (DEINIT failed)\n"); 413 icph_munmap(ha->brd); 414 return 0; 415 } 416 icph_delay(1); 417 } 418 prot_ver = (unchar)icph_readl(&dp6c_ptr->u.ic.S_Info[0]); 419 icph_writeb(0, &dp6c_ptr->u.ic.Status); 420 if (prot_ver != PROTOCOL_VERSION) { 421 printk("illegal protocol version\n"); 422 icph_munmap(ha->brd); 423 return 0; 424 } 425 426 ha->type = ICP_PCINEW; 427 ha->ic_all_size = sizeof(dp6c_ptr->u); 428 429 /* special command to controller BIOS */ 430 icph_writel(0x00, &dp6c_ptr->u.ic.S_Info[0]); 431 icph_writel(0x00, &dp6c_ptr->u.ic.S_Info[1]); 432 icph_writel(0x01, &dp6c_ptr->u.ic.S_Info[2]); 433 icph_writel(0x00, &dp6c_ptr->u.ic.S_Info[3]); 434 icph_writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx); 435 436 outb(1,PTR2USHORT(&ha->plx->ldoor_reg)); 437 438 retries = INIT_RETRIES; 439 icph_delay(20); 440 while (icph_readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) { 441 if (--retries == 0) { 442 printk("initialization error\n"); 443 icph_munmap(ha->brd); 444 return 0; 445 } 446 icph_delay(1); 447 } 448 icph_writeb(0, &dp6c_ptr->u.ic.S_Status); 449 #endif 450 451 icp->icp_ic_all_size = ICP_PCINEW_SZ; 452 453 icp->icp_copy_cmd = icp_pcinew_copy_cmd; 454 icp->icp_get_status = icp_pcinew_get_status; 455 icp->icp_intr = icp_pcinew_intr; 456 icp->icp_release_event = icp_pcinew_release_event; 457 icp->icp_set_sema0 = icp_pcinew_set_sema0; 458 icp->icp_test_busy = icp_pcinew_test_busy; 459 460 break; 461 462 case ICP_MPR: 463 bus_space_write_4(dpmemt, dpmemh, ICP_MPR_IC, ICP_MPR_MAGIC); 464 if (bus_space_read_4(dpmemt, dpmemh, ICP_MPR_IC) != 465 ICP_MPR_MAGIC) { 466 aprint_error( 467 "cannot access DPMEM at 0x%lx (shadowed?)\n", 468 (u_long)dpmembase); 469 goto bail_out; 470 } 471 472 /* 473 * XXX Here the Linux driver has a weird remapping logic I 474 * don't understand. My controller does not need it, and I 475 * cannot see what purpose it serves, therefore I did not 476 * do anything similar. 477 */ 478 479 bus_space_set_region_4(dpmemt, dpmemh, ICP_I960_SZ, 0, 480 ICP_DPR_IF_SZ >> 2); 481 482 /* Disable everything. */ 483 bus_space_write_1(dpmemt, dpmemh, ICP_EDOOR_EN, 484 bus_space_read_1(dpmemt, dpmemh, ICP_EDOOR_EN) | 4); 485 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_EDOOR, 0xff); 486 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_STATUS, 487 0); 488 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_CMD_INDEX, 489 0); 490 491 bus_space_write_4(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_INFO, 492 htole32(dpmembase)); 493 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_CMD_INDX, 494 0xff); 495 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_LDOOR, 1); 496 497 DELAY(20); 498 retries = 1000000; 499 while (bus_space_read_1(dpmemt, dpmemh, 500 ICP_MPR_IC + ICP_S_STATUS) != 0xff) { 501 if (--retries == 0) { 502 aprint_error("DEINIT failed\n"); 503 goto bail_out; 504 } 505 DELAY(1); 506 } 507 508 protocol = (u_int8_t)bus_space_read_4(dpmemt, dpmemh, 509 ICP_MPR_IC + ICP_S_INFO); 510 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_STATUS, 511 0); 512 if (protocol != ICP_PROTOCOL_VERSION) { 513 aprint_error("unsupported protocol %d\n", protocol); 514 goto bail_out; 515 } 516 517 /* special commnd to controller BIOS */ 518 bus_space_write_4(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_INFO, 0); 519 bus_space_write_4(dpmemt, dpmemh, 520 ICP_MPR_IC + ICP_S_INFO + sizeof(u_int32_t), 0); 521 bus_space_write_4(dpmemt, dpmemh, 522 ICP_MPR_IC + ICP_S_INFO + 2 * sizeof(u_int32_t), 1); 523 bus_space_write_4(dpmemt, dpmemh, 524 ICP_MPR_IC + ICP_S_INFO + 3 * sizeof(u_int32_t), 0); 525 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_CMD_INDX, 526 0xfe); 527 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_LDOOR, 1); 528 529 DELAY(20); 530 retries = 1000000; 531 while (bus_space_read_1(dpmemt, dpmemh, 532 ICP_MPR_IC + ICP_S_STATUS) != 0xfe) { 533 if (--retries == 0) { 534 aprint_error("initialization error\n"); 535 goto bail_out; 536 } 537 DELAY(1); 538 } 539 540 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_STATUS, 541 0); 542 543 icp->icp_copy_cmd = icp_mpr_copy_cmd; 544 icp->icp_get_status = icp_mpr_get_status; 545 icp->icp_intr = icp_mpr_intr; 546 icp->icp_release_event = icp_mpr_release_event; 547 icp->icp_set_sema0 = icp_mpr_set_sema0; 548 icp->icp_test_busy = icp_mpr_test_busy; 549 break; 550 } 551 552 if (pci_intr_map(pa, &ih)) { 553 aprint_error("couldn't map interrupt\n"); 554 goto bail_out; 555 } 556 intrstr = pci_intr_string(pa->pa_pc, ih); 557 icp->icp_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, icp_intr, icp); 558 if (icp->icp_ih == NULL) { 559 aprint_error("couldn't establish interrupt"); 560 if (intrstr != NULL) 561 aprint_normal(" at %s", intrstr); 562 aprint_normal("\n"); 563 goto bail_out; 564 } 565 status |= INTR_ESTABLISHED; 566 567 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) 568 aprint_normal("Intel Storage RAID controller\n"); 569 else 570 aprint_normal("ICP-Vortex RAID controller\n"); 571 572 if (icp_init(icp, intrstr)) 573 goto bail_out; 574 575 icp_pci_enable_intr(icp); 576 return; 577 578 bail_out: 579 if ((status & DPMEM_MAPPED) != 0) 580 bus_space_unmap(dpmemt, dpmemh, dpmemsize); 581 if ((status & IOMEM_MAPPED) != 0) 582 bus_space_unmap(iomemt, iomemh, iomembase); 583 if ((status & IO_MAPPED) != 0) 584 bus_space_unmap(iot, ioh, iosize); 585 if ((status & INTR_ESTABLISHED) != 0) 586 pci_intr_disestablish(pa->pa_pc, icp->icp_ih); 587 } 588 589 /* 590 * Enable interrupts. 591 */ 592 void 593 icp_pci_enable_intr(struct icp_softc *icp) 594 { 595 596 switch (ICP_CLASS(icp)) { 597 case ICP_PCI: 598 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_IRQDEL, 599 1); 600 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, 601 ICP_CMD_INDEX, 0); 602 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_IRQEN, 603 1); 604 break; 605 606 case ICP_PCINEW: 607 bus_space_write_1(icp->icp_iot, icp->icp_ioh, ICP_EDOOR_REG, 608 0xff); 609 bus_space_write_1(icp->icp_iot, icp->icp_ioh, ICP_CONTROL1, 3); 610 break; 611 612 case ICP_MPR: 613 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, 614 ICP_MPR_EDOOR, 0xff); 615 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_EDOOR_EN, 616 bus_space_read_1(icp->icp_dpmemt, icp->icp_dpmemh, 617 ICP_EDOOR_EN) & ~4); 618 break; 619 } 620 } 621 622 /* 623 * "Old" PCI controller-specific functions. 624 */ 625 626 void 627 icp_pci_copy_cmd(struct icp_softc *icp, struct icp_ccb *ccb) 628 { 629 630 /* XXX Not yet implemented */ 631 } 632 633 u_int8_t 634 icp_pci_get_status(struct icp_softc *icp) 635 { 636 637 /* XXX Not yet implemented */ 638 return (0); 639 } 640 641 void 642 icp_pci_intr(struct icp_softc *icp, struct icp_intr_ctx *ctx) 643 { 644 645 /* XXX Not yet implemented */ 646 } 647 648 void 649 icp_pci_release_event(struct icp_softc *icp, struct icp_ccb *ccb) 650 { 651 652 /* XXX Not yet implemented */ 653 } 654 655 void 656 icp_pci_set_sema0(struct icp_softc *icp) 657 { 658 659 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_SEMA0, 1); 660 } 661 662 int 663 icp_pci_test_busy(struct icp_softc *icp) 664 { 665 666 /* XXX Not yet implemented */ 667 return (0); 668 } 669 670 /* 671 * "New" PCI controller-specific functions. 672 */ 673 674 void 675 icp_pcinew_copy_cmd(struct icp_softc *icp, struct icp_ccb *ccb) 676 { 677 678 /* XXX Not yet implemented */ 679 } 680 681 u_int8_t 682 icp_pcinew_get_status(struct icp_softc *icp) 683 { 684 685 /* XXX Not yet implemented */ 686 return (0); 687 } 688 689 void 690 icp_pcinew_intr(struct icp_softc *icp, struct icp_intr_ctx *ctx) 691 { 692 693 /* XXX Not yet implemented */ 694 } 695 696 void 697 icp_pcinew_release_event(struct icp_softc *icp, struct icp_ccb *ccb) 698 { 699 700 /* XXX Not yet implemented */ 701 } 702 703 void 704 icp_pcinew_set_sema0(struct icp_softc *icp) 705 { 706 707 bus_space_write_1(icp->icp_iot, icp->icp_ioh, ICP_SEMA0_REG, 1); 708 } 709 710 int 711 icp_pcinew_test_busy(struct icp_softc *icp) 712 { 713 714 /* XXX Not yet implemented */ 715 return (0); 716 } 717 718 /* 719 * MPR PCI controller-specific functions 720 */ 721 722 void 723 icp_mpr_copy_cmd(struct icp_softc *icp, struct icp_ccb *ic) 724 { 725 726 bus_space_write_2(icp->icp_dpmemt, icp->icp_dpmemh, 727 ICP_MPR_IC + ICP_COMM_QUEUE + 0 * ICP_COMM_Q_SZ + ICP_OFFSET, 728 ICP_DPR_CMD); 729 bus_space_write_2(icp->icp_dpmemt, icp->icp_dpmemh, 730 ICP_MPR_IC + ICP_COMM_QUEUE + 0 * ICP_COMM_Q_SZ + ICP_SERV_ID, 731 ic->ic_service); 732 bus_space_write_region_4(icp->icp_dpmemt, icp->icp_dpmemh, 733 ICP_MPR_IC + ICP_DPR_CMD, (u_int32_t *)&ic->ic_cmd, 734 ic->ic_cmdlen >> 2); 735 } 736 737 u_int8_t 738 icp_mpr_get_status(struct icp_softc *icp) 739 { 740 741 return (bus_space_read_1(icp->icp_dpmemt, icp->icp_dpmemh, 742 ICP_MPR_EDOOR)); 743 } 744 745 void 746 icp_mpr_intr(struct icp_softc *icp, struct icp_intr_ctx *ctx) 747 { 748 749 if ((ctx->istatus & 0x80) != 0) { /* error flag */ 750 ctx->istatus &= ~0x80; 751 ctx->cmd_status = bus_space_read_2(icp->icp_dpmemt, 752 icp->icp_dpmemh, ICP_MPR_STATUS); 753 } else 754 ctx->cmd_status = ICP_S_OK; 755 756 ctx->service = bus_space_read_2(icp->icp_dpmemt, icp->icp_dpmemh, 757 ICP_MPR_SERVICE); 758 ctx->info = bus_space_read_4(icp->icp_dpmemt, icp->icp_dpmemh, 759 ICP_MPR_INFO); 760 ctx->info2 = bus_space_read_4(icp->icp_dpmemt, icp->icp_dpmemh, 761 ICP_MPR_INFO + sizeof(u_int32_t)); 762 763 /* 764 * XXX Read async event string here. 765 */ 766 767 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_MPR_EDOOR, 768 0xff); 769 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_MPR_SEMA1, 0); 770 } 771 772 void 773 icp_mpr_release_event(struct icp_softc *icp, struct icp_ccb *ic) 774 { 775 776 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_MPR_LDOOR, 1); 777 } 778 779 void 780 icp_mpr_set_sema0(struct icp_softc *icp) 781 { 782 783 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_MPR_SEMA0, 1); 784 } 785 786 int 787 icp_mpr_test_busy(struct icp_softc *icp) 788 { 789 790 return (bus_space_read_1(icp->icp_dpmemt, icp->icp_dpmemh, 791 ICP_MPR_SEMA0) & 1); 792 } 793
Indexes created Mon Sep 29 21:09:56 GMT 2025