if_age.c revision 1.28.4.5
1 1.28.4.5 yamt /* $NetBSD: if_age.c,v 1.28.4.5 2010/03/11 15:03:44 yamt Exp $ */ 2 1.28.4.2 yamt /* $OpenBSD: if_age.c,v 1.1 2009/01/16 05:00:34 kevlo Exp $ */ 3 1.28.4.2 yamt 4 1.28.4.2 yamt /*- 5 1.28.4.2 yamt * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org> 6 1.28.4.2 yamt * All rights reserved. 7 1.28.4.2 yamt * 8 1.28.4.2 yamt * Redistribution and use in source and binary forms, with or without 9 1.28.4.2 yamt * modification, are permitted provided that the following conditions 10 1.28.4.2 yamt * are met: 11 1.28.4.2 yamt * 1. Redistributions of source code must retain the above copyright 12 1.28.4.2 yamt * notice unmodified, this list of conditions, and the following 13 1.28.4.2 yamt * disclaimer. 14 1.28.4.2 yamt * 2. Redistributions in binary form must reproduce the above copyright 15 1.28.4.2 yamt * notice, this list of conditions and the following disclaimer in the 16 1.28.4.2 yamt * documentation and/or other materials provided with the distribution. 17 1.28.4.2 yamt * 18 1.28.4.2 yamt * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 1.28.4.2 yamt * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 1.28.4.2 yamt * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 1.28.4.2 yamt * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 1.28.4.2 yamt * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 1.28.4.2 yamt * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 1.28.4.2 yamt * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 1.28.4.2 yamt * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 1.28.4.2 yamt * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 1.28.4.2 yamt * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 1.28.4.2 yamt * SUCH DAMAGE. 29 1.28.4.2 yamt */ 30 1.28.4.2 yamt 31 1.28.4.2 yamt /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 32 1.28.4.2 yamt 33 1.28.4.2 yamt #include <sys/cdefs.h> 34 1.28.4.5 yamt __KERNEL_RCSID(0, "$NetBSD: if_age.c,v 1.28.4.5 2010/03/11 15:03:44 yamt Exp $"); 35 1.28.4.2 yamt 36 1.28.4.2 yamt #include "vlan.h" 37 1.28.4.2 yamt 38 1.28.4.2 yamt #include <sys/param.h> 39 1.28.4.2 yamt #include <sys/proc.h> 40 1.28.4.2 yamt #include <sys/endian.h> 41 1.28.4.2 yamt #include <sys/systm.h> 42 1.28.4.2 yamt #include <sys/types.h> 43 1.28.4.2 yamt #include <sys/sockio.h> 44 1.28.4.2 yamt #include <sys/mbuf.h> 45 1.28.4.2 yamt #include <sys/queue.h> 46 1.28.4.2 yamt #include <sys/kernel.h> 47 1.28.4.2 yamt #include <sys/device.h> 48 1.28.4.2 yamt #include <sys/callout.h> 49 1.28.4.2 yamt #include <sys/socket.h> 50 1.28.4.2 yamt 51 1.28.4.2 yamt #include <net/if.h> 52 1.28.4.2 yamt #include <net/if_dl.h> 53 1.28.4.2 yamt #include <net/if_media.h> 54 1.28.4.2 yamt #include <net/if_ether.h> 55 1.28.4.2 yamt 56 1.28.4.2 yamt #ifdef INET 57 1.28.4.2 yamt #include <netinet/in.h> 58 1.28.4.2 yamt #include <netinet/in_systm.h> 59 1.28.4.2 yamt #include <netinet/in_var.h> 60 1.28.4.2 yamt #include <netinet/ip.h> 61 1.28.4.2 yamt #endif 62 1.28.4.2 yamt 63 1.28.4.2 yamt #include <net/if_types.h> 64 1.28.4.2 yamt #include <net/if_vlanvar.h> 65 1.28.4.2 yamt 66 1.28.4.2 yamt #include <net/bpf.h> 67 1.28.4.2 yamt 68 1.28.4.2 yamt #include <sys/rnd.h> 69 1.28.4.2 yamt 70 1.28.4.2 yamt #include <dev/mii/mii.h> 71 1.28.4.2 yamt #include <dev/mii/miivar.h> 72 1.28.4.2 yamt 73 1.28.4.2 yamt #include <dev/pci/pcireg.h> 74 1.28.4.2 yamt #include <dev/pci/pcivar.h> 75 1.28.4.2 yamt #include <dev/pci/pcidevs.h> 76 1.28.4.2 yamt 77 1.28.4.2 yamt #include <dev/pci/if_agereg.h> 78 1.28.4.2 yamt 79 1.28.4.2 yamt static int age_match(device_t, cfdata_t, void *); 80 1.28.4.2 yamt static void age_attach(device_t, device_t, void *); 81 1.28.4.2 yamt static int age_detach(device_t, int); 82 1.28.4.2 yamt 83 1.28.4.5 yamt static bool age_resume(device_t, const pmf_qual_t *); 84 1.28.4.2 yamt 85 1.28.4.2 yamt static int age_miibus_readreg(device_t, int, int); 86 1.28.4.2 yamt static void age_miibus_writereg(device_t, int, int, int); 87 1.28.4.2 yamt static void age_miibus_statchg(device_t); 88 1.28.4.2 yamt 89 1.28.4.2 yamt static int age_init(struct ifnet *); 90 1.28.4.2 yamt static int age_ioctl(struct ifnet *, u_long, void *); 91 1.28.4.2 yamt static void age_start(struct ifnet *); 92 1.28.4.2 yamt static void age_watchdog(struct ifnet *); 93 1.28.4.2 yamt static void age_mediastatus(struct ifnet *, struct ifmediareq *); 94 1.28.4.2 yamt static int age_mediachange(struct ifnet *); 95 1.28.4.2 yamt 96 1.28.4.2 yamt static int age_intr(void *); 97 1.28.4.2 yamt static int age_dma_alloc(struct age_softc *); 98 1.28.4.2 yamt static void age_dma_free(struct age_softc *); 99 1.28.4.2 yamt static void age_get_macaddr(struct age_softc *, uint8_t[]); 100 1.28.4.2 yamt static void age_phy_reset(struct age_softc *); 101 1.28.4.2 yamt 102 1.28.4.2 yamt static int age_encap(struct age_softc *, struct mbuf **); 103 1.28.4.2 yamt static void age_init_tx_ring(struct age_softc *); 104 1.28.4.2 yamt static int age_init_rx_ring(struct age_softc *); 105 1.28.4.2 yamt static void age_init_rr_ring(struct age_softc *); 106 1.28.4.2 yamt static void age_init_cmb_block(struct age_softc *); 107 1.28.4.2 yamt static void age_init_smb_block(struct age_softc *); 108 1.28.4.2 yamt static int age_newbuf(struct age_softc *, struct age_rxdesc *, int); 109 1.28.4.2 yamt static void age_mac_config(struct age_softc *); 110 1.28.4.2 yamt static void age_txintr(struct age_softc *, int); 111 1.28.4.2 yamt static void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 112 1.28.4.2 yamt static void age_rxintr(struct age_softc *, int); 113 1.28.4.2 yamt static void age_tick(void *); 114 1.28.4.2 yamt static void age_reset(struct age_softc *); 115 1.28.4.2 yamt static void age_stop(struct ifnet *, int); 116 1.28.4.2 yamt static void age_stats_update(struct age_softc *); 117 1.28.4.2 yamt static void age_stop_txmac(struct age_softc *); 118 1.28.4.2 yamt static void age_stop_rxmac(struct age_softc *); 119 1.28.4.2 yamt static void age_rxvlan(struct age_softc *sc); 120 1.28.4.2 yamt static void age_rxfilter(struct age_softc *); 121 1.28.4.2 yamt 122 1.28.4.2 yamt CFATTACH_DECL_NEW(age, sizeof(struct age_softc), 123 1.28.4.2 yamt age_match, age_attach, age_detach, NULL); 124 1.28.4.2 yamt 125 1.28.4.2 yamt int agedebug = 0; 126 1.28.4.2 yamt #define DPRINTF(x) do { if (agedebug) printf x; } while (0) 127 1.28.4.2 yamt 128 1.28.4.2 yamt #define ETHER_ALIGN 2 129 1.28.4.2 yamt #define AGE_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 130 1.28.4.2 yamt 131 1.28.4.2 yamt static int 132 1.28.4.2 yamt age_match(device_t dev, cfdata_t match, void *aux) 133 1.28.4.2 yamt { 134 1.28.4.2 yamt struct pci_attach_args *pa = aux; 135 1.28.4.2 yamt 136 1.28.4.2 yamt return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && 137 1.28.4.2 yamt PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_GIGA); 138 1.28.4.2 yamt } 139 1.28.4.2 yamt 140 1.28.4.2 yamt static void 141 1.28.4.2 yamt age_attach(device_t parent, device_t self, void *aux) 142 1.28.4.2 yamt { 143 1.28.4.2 yamt struct age_softc *sc = device_private(self); 144 1.28.4.2 yamt struct pci_attach_args *pa = aux; 145 1.28.4.2 yamt pci_intr_handle_t ih; 146 1.28.4.2 yamt const char *intrstr; 147 1.28.4.2 yamt struct ifnet *ifp = &sc->sc_ec.ec_if; 148 1.28.4.2 yamt pcireg_t memtype; 149 1.28.4.2 yamt int error = 0; 150 1.28.4.2 yamt 151 1.28.4.2 yamt aprint_naive("\n"); 152 1.28.4.2 yamt aprint_normal(": Attansic/Atheros L1 Gigabit Ethernet\n"); 153 1.28.4.2 yamt 154 1.28.4.2 yamt sc->sc_dev = self; 155 1.28.4.2 yamt sc->sc_dmat = pa->pa_dmat; 156 1.28.4.2 yamt sc->sc_pct = pa->pa_pc; 157 1.28.4.2 yamt sc->sc_pcitag = pa->pa_tag; 158 1.28.4.2 yamt 159 1.28.4.2 yamt /* 160 1.28.4.2 yamt * Allocate IO memory 161 1.28.4.2 yamt */ 162 1.28.4.2 yamt memtype = pci_mapreg_type(sc->sc_pct, sc->sc_pcitag, AGE_PCIR_BAR); 163 1.28.4.2 yamt switch (memtype) { 164 1.28.4.2 yamt case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 165 1.28.4.2 yamt case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 166 1.28.4.2 yamt case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 167 1.28.4.2 yamt break; 168 1.28.4.2 yamt default: 169 1.28.4.2 yamt aprint_error_dev(self, "invalid base address register\n"); 170 1.28.4.2 yamt break; 171 1.28.4.2 yamt } 172 1.28.4.2 yamt 173 1.28.4.2 yamt if (pci_mapreg_map(pa, AGE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 174 1.28.4.2 yamt &sc->sc_mem_bh, NULL, &sc->sc_mem_size) != 0) { 175 1.28.4.2 yamt aprint_error_dev(self, "could not map mem space\n"); 176 1.28.4.2 yamt return; 177 1.28.4.2 yamt } 178 1.28.4.2 yamt 179 1.28.4.2 yamt if (pci_intr_map(pa, &ih) != 0) { 180 1.28.4.2 yamt aprint_error_dev(self, "could not map interrupt\n"); 181 1.28.4.2 yamt goto fail; 182 1.28.4.2 yamt } 183 1.28.4.2 yamt 184 1.28.4.2 yamt /* 185 1.28.4.2 yamt * Allocate IRQ 186 1.28.4.2 yamt */ 187 1.28.4.2 yamt intrstr = pci_intr_string(sc->sc_pct, ih); 188 1.28.4.2 yamt sc->sc_irq_handle = pci_intr_establish(sc->sc_pct, ih, IPL_NET, 189 1.28.4.2 yamt age_intr, sc); 190 1.28.4.2 yamt if (sc->sc_irq_handle == NULL) { 191 1.28.4.2 yamt aprint_error_dev(self, "could not establish interrupt"); 192 1.28.4.2 yamt if (intrstr != NULL) 193 1.28.4.2 yamt aprint_error(" at %s", intrstr); 194 1.28.4.2 yamt aprint_error("\n"); 195 1.28.4.2 yamt goto fail; 196 1.28.4.2 yamt } 197 1.28.4.2 yamt aprint_normal_dev(self, "%s\n", intrstr); 198 1.28.4.2 yamt 199 1.28.4.2 yamt /* Set PHY address. */ 200 1.28.4.2 yamt sc->age_phyaddr = AGE_PHY_ADDR; 201 1.28.4.2 yamt 202 1.28.4.2 yamt /* Reset PHY. */ 203 1.28.4.2 yamt age_phy_reset(sc); 204 1.28.4.2 yamt 205 1.28.4.2 yamt /* Reset the ethernet controller. */ 206 1.28.4.2 yamt age_reset(sc); 207 1.28.4.2 yamt 208 1.28.4.2 yamt /* Get PCI and chip id/revision. */ 209 1.28.4.2 yamt sc->age_rev = PCI_REVISION(pa->pa_class); 210 1.28.4.2 yamt sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 211 1.28.4.2 yamt MASTER_CHIP_REV_SHIFT; 212 1.28.4.2 yamt 213 1.28.4.2 yamt aprint_debug_dev(self, "PCI device revision : 0x%04x\n", sc->age_rev); 214 1.28.4.2 yamt aprint_debug_dev(self, "Chip id/revision : 0x%04x\n", sc->age_chip_rev); 215 1.28.4.2 yamt 216 1.28.4.2 yamt if (agedebug) { 217 1.28.4.2 yamt aprint_debug_dev(self, "%d Tx FIFO, %d Rx FIFO\n", 218 1.28.4.2 yamt CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 219 1.28.4.2 yamt CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 220 1.28.4.2 yamt } 221 1.28.4.2 yamt 222 1.28.4.2 yamt /* Set max allowable DMA size. */ 223 1.28.4.2 yamt sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 224 1.28.4.2 yamt sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 225 1.28.4.2 yamt 226 1.28.4.2 yamt /* Allocate DMA stuffs */ 227 1.28.4.2 yamt error = age_dma_alloc(sc); 228 1.28.4.2 yamt if (error) 229 1.28.4.2 yamt goto fail; 230 1.28.4.2 yamt 231 1.28.4.2 yamt callout_init(&sc->sc_tick_ch, 0); 232 1.28.4.2 yamt callout_setfunc(&sc->sc_tick_ch, age_tick, sc); 233 1.28.4.2 yamt 234 1.28.4.2 yamt /* Load station address. */ 235 1.28.4.2 yamt age_get_macaddr(sc, sc->sc_enaddr); 236 1.28.4.2 yamt 237 1.28.4.2 yamt aprint_normal_dev(self, "Ethernet address %s\n", 238 1.28.4.2 yamt ether_sprintf(sc->sc_enaddr)); 239 1.28.4.2 yamt 240 1.28.4.2 yamt ifp->if_softc = sc; 241 1.28.4.2 yamt ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 242 1.28.4.2 yamt ifp->if_init = age_init; 243 1.28.4.2 yamt ifp->if_ioctl = age_ioctl; 244 1.28.4.2 yamt ifp->if_start = age_start; 245 1.28.4.2 yamt ifp->if_stop = age_stop; 246 1.28.4.2 yamt ifp->if_watchdog = age_watchdog; 247 1.28.4.2 yamt ifp->if_baudrate = IF_Gbps(1); 248 1.28.4.2 yamt IFQ_SET_MAXLEN(&ifp->if_snd, AGE_TX_RING_CNT - 1); 249 1.28.4.2 yamt IFQ_SET_READY(&ifp->if_snd); 250 1.28.4.2 yamt strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 251 1.28.4.2 yamt 252 1.28.4.2 yamt sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 253 1.28.4.2 yamt 254 1.28.4.3 yamt ifp->if_capabilities |= IFCAP_CSUM_IPv4_Rx | 255 1.28.4.3 yamt IFCAP_CSUM_TCPv4_Rx | 256 1.28.4.3 yamt IFCAP_CSUM_UDPv4_Rx; 257 1.28.4.2 yamt #ifdef AGE_CHECKSUM 258 1.28.4.3 yamt ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | 259 1.28.4.3 yamt IFCAP_CSUM_TCPv4_Tx | 260 1.28.4.3 yamt IFCAP_CSUM_UDPv4_Tx; 261 1.28.4.2 yamt #endif 262 1.28.4.2 yamt 263 1.28.4.2 yamt #if NVLAN > 0 264 1.28.4.2 yamt sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 265 1.28.4.2 yamt #endif 266 1.28.4.2 yamt 267 1.28.4.2 yamt /* Set up MII bus. */ 268 1.28.4.2 yamt sc->sc_miibus.mii_ifp = ifp; 269 1.28.4.2 yamt sc->sc_miibus.mii_readreg = age_miibus_readreg; 270 1.28.4.2 yamt sc->sc_miibus.mii_writereg = age_miibus_writereg; 271 1.28.4.2 yamt sc->sc_miibus.mii_statchg = age_miibus_statchg; 272 1.28.4.2 yamt 273 1.28.4.2 yamt sc->sc_ec.ec_mii = &sc->sc_miibus; 274 1.28.4.2 yamt ifmedia_init(&sc->sc_miibus.mii_media, 0, age_mediachange, 275 1.28.4.2 yamt age_mediastatus); 276 1.28.4.2 yamt mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 277 1.28.4.3 yamt MII_OFFSET_ANY, MIIF_DOPAUSE); 278 1.28.4.2 yamt 279 1.28.4.2 yamt if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 280 1.28.4.2 yamt aprint_error_dev(self, "no PHY found!\n"); 281 1.28.4.2 yamt ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 282 1.28.4.2 yamt 0, NULL); 283 1.28.4.2 yamt ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 284 1.28.4.2 yamt } else 285 1.28.4.2 yamt ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 286 1.28.4.2 yamt 287 1.28.4.2 yamt if_attach(ifp); 288 1.28.4.2 yamt ether_ifattach(ifp, sc->sc_enaddr); 289 1.28.4.2 yamt 290 1.28.4.4 yamt if (pmf_device_register(self, NULL, age_resume)) 291 1.28.4.2 yamt pmf_class_network_register(self, ifp); 292 1.28.4.4 yamt else 293 1.28.4.4 yamt aprint_error_dev(self, "couldn't establish power handler\n"); 294 1.28.4.2 yamt 295 1.28.4.2 yamt return; 296 1.28.4.2 yamt 297 1.28.4.2 yamt fail: 298 1.28.4.2 yamt age_dma_free(sc); 299 1.28.4.2 yamt if (sc->sc_irq_handle != NULL) { 300 1.28.4.2 yamt pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 301 1.28.4.2 yamt sc->sc_irq_handle = NULL; 302 1.28.4.2 yamt } 303 1.28.4.2 yamt if (sc->sc_mem_size) { 304 1.28.4.2 yamt bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 305 1.28.4.2 yamt sc->sc_mem_size = 0; 306 1.28.4.2 yamt } 307 1.28.4.2 yamt } 308 1.28.4.2 yamt 309 1.28.4.2 yamt static int 310 1.28.4.2 yamt age_detach(device_t self, int flags) 311 1.28.4.2 yamt { 312 1.28.4.2 yamt struct age_softc *sc = device_private(self); 313 1.28.4.2 yamt struct ifnet *ifp = &sc->sc_ec.ec_if; 314 1.28.4.2 yamt int s; 315 1.28.4.2 yamt 316 1.28.4.2 yamt pmf_device_deregister(self); 317 1.28.4.2 yamt s = splnet(); 318 1.28.4.2 yamt age_stop(ifp, 0); 319 1.28.4.2 yamt splx(s); 320 1.28.4.2 yamt 321 1.28.4.2 yamt mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 322 1.28.4.2 yamt 323 1.28.4.2 yamt /* Delete all remaining media. */ 324 1.28.4.2 yamt ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 325 1.28.4.2 yamt 326 1.28.4.2 yamt ether_ifdetach(ifp); 327 1.28.4.2 yamt if_detach(ifp); 328 1.28.4.2 yamt age_dma_free(sc); 329 1.28.4.2 yamt 330 1.28.4.2 yamt if (sc->sc_irq_handle != NULL) { 331 1.28.4.2 yamt pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 332 1.28.4.2 yamt sc->sc_irq_handle = NULL; 333 1.28.4.2 yamt } 334 1.28.4.2 yamt if (sc->sc_mem_size) { 335 1.28.4.2 yamt bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 336 1.28.4.2 yamt sc->sc_mem_size = 0; 337 1.28.4.2 yamt } 338 1.28.4.2 yamt return 0; 339 1.28.4.2 yamt } 340 1.28.4.2 yamt 341 1.28.4.2 yamt /* 342 1.28.4.2 yamt * Read a PHY register on the MII of the L1. 343 1.28.4.2 yamt */ 344 1.28.4.2 yamt static int 345 1.28.4.2 yamt age_miibus_readreg(device_t dev, int phy, int reg) 346 1.28.4.2 yamt { 347 1.28.4.2 yamt struct age_softc *sc = device_private(dev); 348 1.28.4.2 yamt uint32_t v; 349 1.28.4.2 yamt int i; 350 1.28.4.2 yamt 351 1.28.4.2 yamt if (phy != sc->age_phyaddr) 352 1.28.4.2 yamt return 0; 353 1.28.4.2 yamt 354 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 355 1.28.4.2 yamt MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 356 1.28.4.2 yamt for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 357 1.28.4.2 yamt DELAY(1); 358 1.28.4.2 yamt v = CSR_READ_4(sc, AGE_MDIO); 359 1.28.4.2 yamt if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 360 1.28.4.2 yamt break; 361 1.28.4.2 yamt } 362 1.28.4.2 yamt 363 1.28.4.2 yamt if (i == 0) { 364 1.28.4.2 yamt printf("%s: phy read timeout: phy %d, reg %d\n", 365 1.28.4.2 yamt device_xname(sc->sc_dev), phy, reg); 366 1.28.4.2 yamt return 0; 367 1.28.4.2 yamt } 368 1.28.4.2 yamt 369 1.28.4.2 yamt return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 370 1.28.4.2 yamt } 371 1.28.4.2 yamt 372 1.28.4.2 yamt /* 373 1.28.4.2 yamt * Write a PHY register on the MII of the L1. 374 1.28.4.2 yamt */ 375 1.28.4.2 yamt static void 376 1.28.4.2 yamt age_miibus_writereg(device_t dev, int phy, int reg, int val) 377 1.28.4.2 yamt { 378 1.28.4.2 yamt struct age_softc *sc = device_private(dev); 379 1.28.4.2 yamt uint32_t v; 380 1.28.4.2 yamt int i; 381 1.28.4.2 yamt 382 1.28.4.2 yamt if (phy != sc->age_phyaddr) 383 1.28.4.2 yamt return; 384 1.28.4.2 yamt 385 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 386 1.28.4.2 yamt (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 387 1.28.4.2 yamt MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 388 1.28.4.2 yamt 389 1.28.4.2 yamt for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 390 1.28.4.2 yamt DELAY(1); 391 1.28.4.2 yamt v = CSR_READ_4(sc, AGE_MDIO); 392 1.28.4.2 yamt if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 393 1.28.4.2 yamt break; 394 1.28.4.2 yamt } 395 1.28.4.2 yamt 396 1.28.4.2 yamt if (i == 0) { 397 1.28.4.2 yamt printf("%s: phy write timeout: phy %d, reg %d\n", 398 1.28.4.2 yamt device_xname(sc->sc_dev), phy, reg); 399 1.28.4.2 yamt } 400 1.28.4.2 yamt } 401 1.28.4.2 yamt 402 1.28.4.2 yamt /* 403 1.28.4.2 yamt * Callback from MII layer when media changes. 404 1.28.4.2 yamt */ 405 1.28.4.2 yamt static void 406 1.28.4.2 yamt age_miibus_statchg(device_t dev) 407 1.28.4.2 yamt { 408 1.28.4.2 yamt struct age_softc *sc = device_private(dev); 409 1.28.4.2 yamt struct ifnet *ifp = &sc->sc_ec.ec_if; 410 1.28.4.2 yamt struct mii_data *mii; 411 1.28.4.2 yamt 412 1.28.4.2 yamt if ((ifp->if_flags & IFF_RUNNING) == 0) 413 1.28.4.2 yamt return; 414 1.28.4.2 yamt 415 1.28.4.2 yamt mii = &sc->sc_miibus; 416 1.28.4.2 yamt 417 1.28.4.2 yamt sc->age_flags &= ~AGE_FLAG_LINK; 418 1.28.4.2 yamt if ((mii->mii_media_status & IFM_AVALID) != 0) { 419 1.28.4.2 yamt switch (IFM_SUBTYPE(mii->mii_media_active)) { 420 1.28.4.2 yamt case IFM_10_T: 421 1.28.4.2 yamt case IFM_100_TX: 422 1.28.4.2 yamt case IFM_1000_T: 423 1.28.4.2 yamt sc->age_flags |= AGE_FLAG_LINK; 424 1.28.4.2 yamt break; 425 1.28.4.2 yamt default: 426 1.28.4.2 yamt break; 427 1.28.4.2 yamt } 428 1.28.4.2 yamt } 429 1.28.4.2 yamt 430 1.28.4.2 yamt /* Stop Rx/Tx MACs. */ 431 1.28.4.2 yamt age_stop_rxmac(sc); 432 1.28.4.2 yamt age_stop_txmac(sc); 433 1.28.4.2 yamt 434 1.28.4.2 yamt /* Program MACs with resolved speed/duplex/flow-control. */ 435 1.28.4.2 yamt if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 436 1.28.4.2 yamt uint32_t reg; 437 1.28.4.2 yamt 438 1.28.4.2 yamt age_mac_config(sc); 439 1.28.4.2 yamt reg = CSR_READ_4(sc, AGE_MAC_CFG); 440 1.28.4.2 yamt /* Restart DMA engine and Tx/Rx MAC. */ 441 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 442 1.28.4.2 yamt DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 443 1.28.4.2 yamt reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 444 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 445 1.28.4.2 yamt } 446 1.28.4.2 yamt } 447 1.28.4.2 yamt 448 1.28.4.2 yamt /* 449 1.28.4.2 yamt * Get the current interface media status. 450 1.28.4.2 yamt */ 451 1.28.4.2 yamt static void 452 1.28.4.2 yamt age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 453 1.28.4.2 yamt { 454 1.28.4.2 yamt struct age_softc *sc = ifp->if_softc; 455 1.28.4.2 yamt struct mii_data *mii = &sc->sc_miibus; 456 1.28.4.2 yamt 457 1.28.4.2 yamt mii_pollstat(mii); 458 1.28.4.2 yamt ifmr->ifm_status = mii->mii_media_status; 459 1.28.4.2 yamt ifmr->ifm_active = mii->mii_media_active; 460 1.28.4.2 yamt } 461 1.28.4.2 yamt 462 1.28.4.2 yamt /* 463 1.28.4.2 yamt * Set hardware to newly-selected media. 464 1.28.4.2 yamt */ 465 1.28.4.2 yamt static int 466 1.28.4.2 yamt age_mediachange(struct ifnet *ifp) 467 1.28.4.2 yamt { 468 1.28.4.2 yamt struct age_softc *sc = ifp->if_softc; 469 1.28.4.2 yamt struct mii_data *mii = &sc->sc_miibus; 470 1.28.4.2 yamt int error; 471 1.28.4.2 yamt 472 1.28.4.2 yamt if (mii->mii_instance != 0) { 473 1.28.4.2 yamt struct mii_softc *miisc; 474 1.28.4.2 yamt 475 1.28.4.2 yamt LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 476 1.28.4.2 yamt mii_phy_reset(miisc); 477 1.28.4.2 yamt } 478 1.28.4.2 yamt error = mii_mediachg(mii); 479 1.28.4.2 yamt 480 1.28.4.2 yamt return error; 481 1.28.4.2 yamt } 482 1.28.4.2 yamt 483 1.28.4.2 yamt static int 484 1.28.4.2 yamt age_intr(void *arg) 485 1.28.4.2 yamt { 486 1.28.4.2 yamt struct age_softc *sc = arg; 487 1.28.4.2 yamt struct ifnet *ifp = &sc->sc_ec.ec_if; 488 1.28.4.2 yamt struct cmb *cmb; 489 1.28.4.2 yamt uint32_t status; 490 1.28.4.2 yamt 491 1.28.4.2 yamt status = CSR_READ_4(sc, AGE_INTR_STATUS); 492 1.28.4.2 yamt if (status == 0 || (status & AGE_INTRS) == 0) 493 1.28.4.2 yamt return 0; 494 1.28.4.2 yamt 495 1.28.4.2 yamt cmb = sc->age_rdata.age_cmb_block; 496 1.28.4.2 yamt if (cmb == NULL) { 497 1.28.4.2 yamt /* Happens when bringing up the interface 498 1.28.4.2 yamt * w/o having a carrier. Ack. the interrupt. 499 1.28.4.2 yamt */ 500 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_INTR_STATUS, status); 501 1.28.4.2 yamt return 0; 502 1.28.4.2 yamt } 503 1.28.4.2 yamt 504 1.28.4.2 yamt /* Disable interrupts. */ 505 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 506 1.28.4.2 yamt 507 1.28.4.2 yamt bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 508 1.28.4.2 yamt sc->age_cdata.age_cmb_block_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 509 1.28.4.2 yamt status = le32toh(cmb->intr_status); 510 1.28.4.2 yamt if ((status & AGE_INTRS) == 0) 511 1.28.4.2 yamt goto back; 512 1.28.4.2 yamt 513 1.28.4.2 yamt sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 514 1.28.4.2 yamt TPD_CONS_SHIFT; 515 1.28.4.2 yamt sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 516 1.28.4.2 yamt RRD_PROD_SHIFT; 517 1.28.4.2 yamt 518 1.28.4.2 yamt /* Let hardware know CMB was served. */ 519 1.28.4.2 yamt cmb->intr_status = 0; 520 1.28.4.2 yamt bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 521 1.28.4.2 yamt sc->age_cdata.age_cmb_block_map->dm_mapsize, 522 1.28.4.2 yamt BUS_DMASYNC_PREWRITE); 523 1.28.4.2 yamt 524 1.28.4.2 yamt if (ifp->if_flags & IFF_RUNNING) { 525 1.28.4.2 yamt if (status & INTR_CMB_RX) 526 1.28.4.2 yamt age_rxintr(sc, sc->age_rr_prod); 527 1.28.4.2 yamt 528 1.28.4.2 yamt if (status & INTR_CMB_TX) 529 1.28.4.2 yamt age_txintr(sc, sc->age_tpd_cons); 530 1.28.4.2 yamt 531 1.28.4.2 yamt if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 532 1.28.4.2 yamt if (status & INTR_DMA_RD_TO_RST) 533 1.28.4.2 yamt printf("%s: DMA read error! -- resetting\n", 534 1.28.4.2 yamt device_xname(sc->sc_dev)); 535 1.28.4.2 yamt if (status & INTR_DMA_WR_TO_RST) 536 1.28.4.2 yamt printf("%s: DMA write error! -- resetting\n", 537 1.28.4.2 yamt device_xname(sc->sc_dev)); 538 1.28.4.2 yamt age_init(ifp); 539 1.28.4.2 yamt } 540 1.28.4.2 yamt 541 1.28.4.2 yamt if (!IFQ_IS_EMPTY(&ifp->if_snd)) 542 1.28.4.2 yamt age_start(ifp); 543 1.28.4.2 yamt 544 1.28.4.2 yamt if (status & INTR_SMB) 545 1.28.4.2 yamt age_stats_update(sc); 546 1.28.4.2 yamt } 547 1.28.4.2 yamt 548 1.28.4.2 yamt /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 549 1.28.4.2 yamt bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 550 1.28.4.2 yamt sc->age_cdata.age_cmb_block_map->dm_mapsize, 551 1.28.4.2 yamt BUS_DMASYNC_POSTREAD); 552 1.28.4.2 yamt 553 1.28.4.2 yamt back: 554 1.28.4.2 yamt /* Re-enable interrupts. */ 555 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 556 1.28.4.2 yamt 557 1.28.4.2 yamt return 1; 558 1.28.4.2 yamt } 559 1.28.4.2 yamt 560 1.28.4.2 yamt static void 561 1.28.4.2 yamt age_get_macaddr(struct age_softc *sc, uint8_t eaddr[]) 562 1.28.4.2 yamt { 563 1.28.4.3 yamt uint32_t ea[2], reg; 564 1.28.4.3 yamt int i, vpdc; 565 1.28.4.2 yamt 566 1.28.4.2 yamt reg = CSR_READ_4(sc, AGE_SPI_CTRL); 567 1.28.4.2 yamt if ((reg & SPI_VPD_ENB) != 0) { 568 1.28.4.2 yamt /* Get VPD stored in TWSI EEPROM. */ 569 1.28.4.2 yamt reg &= ~SPI_VPD_ENB; 570 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 571 1.28.4.2 yamt } 572 1.28.4.2 yamt 573 1.28.4.3 yamt if (pci_get_capability(sc->sc_pct, sc->sc_pcitag, 574 1.28.4.3 yamt PCI_CAP_VPD, &vpdc, NULL)) { 575 1.28.4.2 yamt /* 576 1.28.4.3 yamt * PCI VPD capability found, let TWSI reload EEPROM. 577 1.28.4.3 yamt * This will set Ethernet address of controller. 578 1.28.4.2 yamt */ 579 1.28.4.3 yamt CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | 580 1.28.4.3 yamt TWSI_CTRL_SW_LD_START); 581 1.28.4.3 yamt for (i = 100; i > 0; i++) { 582 1.28.4.3 yamt DELAY(1000); 583 1.28.4.3 yamt reg = CSR_READ_4(sc, AGE_TWSI_CTRL); 584 1.28.4.3 yamt if ((reg & TWSI_CTRL_SW_LD_START) == 0) 585 1.28.4.2 yamt break; 586 1.28.4.2 yamt } 587 1.28.4.3 yamt if (i == 0) 588 1.28.4.3 yamt printf("%s: reloading EEPROM timeout!\n", 589 1.28.4.2 yamt device_xname(sc->sc_dev)); 590 1.28.4.2 yamt } else { 591 1.28.4.2 yamt if (agedebug) 592 1.28.4.2 yamt printf("%s: PCI VPD capability not found!\n", 593 1.28.4.2 yamt device_xname(sc->sc_dev)); 594 1.28.4.2 yamt } 595 1.28.4.2 yamt 596 1.28.4.3 yamt ea[0] = CSR_READ_4(sc, AGE_PAR0); 597 1.28.4.3 yamt ea[1] = CSR_READ_4(sc, AGE_PAR1); 598 1.28.4.2 yamt 599 1.28.4.2 yamt eaddr[0] = (ea[1] >> 8) & 0xFF; 600 1.28.4.2 yamt eaddr[1] = (ea[1] >> 0) & 0xFF; 601 1.28.4.2 yamt eaddr[2] = (ea[0] >> 24) & 0xFF; 602 1.28.4.2 yamt eaddr[3] = (ea[0] >> 16) & 0xFF; 603 1.28.4.2 yamt eaddr[4] = (ea[0] >> 8) & 0xFF; 604 1.28.4.2 yamt eaddr[5] = (ea[0] >> 0) & 0xFF; 605 1.28.4.2 yamt } 606 1.28.4.2 yamt 607 1.28.4.2 yamt static void 608 1.28.4.2 yamt age_phy_reset(struct age_softc *sc) 609 1.28.4.2 yamt { 610 1.28.4.3 yamt uint16_t reg, pn; 611 1.28.4.3 yamt int i, linkup; 612 1.28.4.3 yamt 613 1.28.4.2 yamt /* Reset PHY. */ 614 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 615 1.28.4.3 yamt DELAY(2000); 616 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 617 1.28.4.3 yamt DELAY(2000); 618 1.28.4.3 yamt 619 1.28.4.3 yamt #define ATPHY_DBG_ADDR 0x1D 620 1.28.4.3 yamt #define ATPHY_DBG_DATA 0x1E 621 1.28.4.3 yamt #define ATPHY_CDTC 0x16 622 1.28.4.3 yamt #define PHY_CDTC_ENB 0x0001 623 1.28.4.3 yamt #define PHY_CDTC_POFF 8 624 1.28.4.3 yamt #define ATPHY_CDTS 0x1C 625 1.28.4.3 yamt #define PHY_CDTS_STAT_OK 0x0000 626 1.28.4.3 yamt #define PHY_CDTS_STAT_SHORT 0x0100 627 1.28.4.3 yamt #define PHY_CDTS_STAT_OPEN 0x0200 628 1.28.4.3 yamt #define PHY_CDTS_STAT_INVAL 0x0300 629 1.28.4.3 yamt #define PHY_CDTS_STAT_MASK 0x0300 630 1.28.4.3 yamt 631 1.28.4.3 yamt /* Check power saving mode. Magic from Linux. */ 632 1.28.4.3 yamt age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET); 633 1.28.4.3 yamt for (linkup = 0, pn = 0; pn < 4; pn++) { 634 1.28.4.3 yamt age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, ATPHY_CDTC, 635 1.28.4.3 yamt (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB); 636 1.28.4.3 yamt for (i = 200; i > 0; i--) { 637 1.28.4.3 yamt DELAY(1000); 638 1.28.4.3 yamt reg = age_miibus_readreg(sc->sc_dev, sc->age_phyaddr, 639 1.28.4.3 yamt ATPHY_CDTC); 640 1.28.4.3 yamt if ((reg & PHY_CDTC_ENB) == 0) 641 1.28.4.3 yamt break; 642 1.28.4.3 yamt } 643 1.28.4.3 yamt DELAY(1000); 644 1.28.4.3 yamt reg = age_miibus_readreg(sc->sc_dev, sc->age_phyaddr, 645 1.28.4.3 yamt ATPHY_CDTS); 646 1.28.4.3 yamt if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) { 647 1.28.4.3 yamt linkup++; 648 1.28.4.3 yamt break; 649 1.28.4.3 yamt } 650 1.28.4.3 yamt } 651 1.28.4.3 yamt age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, MII_BMCR, 652 1.28.4.3 yamt BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 653 1.28.4.3 yamt if (linkup == 0) { 654 1.28.4.3 yamt age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, 655 1.28.4.3 yamt ATPHY_DBG_ADDR, 0); 656 1.28.4.3 yamt age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, 657 1.28.4.3 yamt ATPHY_DBG_DATA, 0x124E); 658 1.28.4.3 yamt age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, 659 1.28.4.3 yamt ATPHY_DBG_ADDR, 1); 660 1.28.4.3 yamt reg = age_miibus_readreg(sc->sc_dev, sc->age_phyaddr, 661 1.28.4.3 yamt ATPHY_DBG_DATA); 662 1.28.4.3 yamt age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, 663 1.28.4.3 yamt ATPHY_DBG_DATA, reg | 0x03); 664 1.28.4.3 yamt /* XXX */ 665 1.28.4.3 yamt DELAY(1500 * 1000); 666 1.28.4.3 yamt age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, 667 1.28.4.3 yamt ATPHY_DBG_ADDR, 0); 668 1.28.4.3 yamt age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, 669 1.28.4.3 yamt ATPHY_DBG_DATA, 0x024E); 670 1.28.4.3 yamt } 671 1.28.4.3 yamt 672 1.28.4.3 yamt #undef ATPHY_DBG_ADDR 673 1.28.4.3 yamt #undef ATPHY_DBG_DATA 674 1.28.4.3 yamt #undef ATPHY_CDTC 675 1.28.4.3 yamt #undef PHY_CDTC_ENB 676 1.28.4.3 yamt #undef PHY_CDTC_POFF 677 1.28.4.3 yamt #undef ATPHY_CDTS 678 1.28.4.3 yamt #undef PHY_CDTS_STAT_OK 679 1.28.4.3 yamt #undef PHY_CDTS_STAT_SHORT 680 1.28.4.3 yamt #undef PHY_CDTS_STAT_OPEN 681 1.28.4.3 yamt #undef PHY_CDTS_STAT_INVAL 682 1.28.4.3 yamt #undef PHY_CDTS_STAT_MASK 683 1.28.4.2 yamt } 684 1.28.4.2 yamt 685 1.28.4.2 yamt static int 686 1.28.4.2 yamt age_dma_alloc(struct age_softc *sc) 687 1.28.4.2 yamt { 688 1.28.4.2 yamt struct age_txdesc *txd; 689 1.28.4.2 yamt struct age_rxdesc *rxd; 690 1.28.4.2 yamt int nsegs, error, i; 691 1.28.4.2 yamt 692 1.28.4.2 yamt /* 693 1.28.4.2 yamt * Create DMA stuffs for TX ring 694 1.28.4.2 yamt */ 695 1.28.4.2 yamt error = bus_dmamap_create(sc->sc_dmat, AGE_TX_RING_SZ, 1, 696 1.28.4.2 yamt AGE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_tx_ring_map); 697 1.28.4.2 yamt if (error) { 698 1.28.4.2 yamt sc->age_cdata.age_tx_ring_map = NULL; 699 1.28.4.2 yamt return ENOBUFS; 700 1.28.4.2 yamt } 701 1.28.4.2 yamt 702 1.28.4.2 yamt /* Allocate DMA'able memory for TX ring */ 703 1.28.4.2 yamt error = bus_dmamem_alloc(sc->sc_dmat, AGE_TX_RING_SZ, 704 1.28.4.2 yamt ETHER_ALIGN, 0, &sc->age_rdata.age_tx_ring_seg, 1, 705 1.28.4.2 yamt &nsegs, BUS_DMA_WAITOK); 706 1.28.4.2 yamt if (error) { 707 1.28.4.2 yamt printf("%s: could not allocate DMA'able memory for Tx ring, " 708 1.28.4.2 yamt "error = %i\n", device_xname(sc->sc_dev), error); 709 1.28.4.2 yamt return error; 710 1.28.4.2 yamt } 711 1.28.4.2 yamt 712 1.28.4.2 yamt error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_tx_ring_seg, 713 1.28.4.2 yamt nsegs, AGE_TX_RING_SZ, (void **)&sc->age_rdata.age_tx_ring, 714 1.28.4.2 yamt BUS_DMA_NOWAIT); 715 1.28.4.2 yamt if (error) 716 1.28.4.2 yamt return ENOBUFS; 717 1.28.4.2 yamt 718 1.28.4.2 yamt memset(sc->age_rdata.age_tx_ring, 0, AGE_TX_RING_SZ); 719 1.28.4.2 yamt 720 1.28.4.2 yamt /* Load the DMA map for Tx ring. */ 721 1.28.4.2 yamt error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 722 1.28.4.2 yamt sc->age_rdata.age_tx_ring, AGE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 723 1.28.4.2 yamt if (error) { 724 1.28.4.2 yamt printf("%s: could not load DMA'able memory for Tx ring, " 725 1.28.4.2 yamt "error = %i\n", device_xname(sc->sc_dev), error); 726 1.28.4.2 yamt bus_dmamem_free(sc->sc_dmat, 727 1.28.4.2 yamt &sc->age_rdata.age_tx_ring_seg, 1); 728 1.28.4.2 yamt return error; 729 1.28.4.2 yamt } 730 1.28.4.2 yamt 731 1.28.4.2 yamt sc->age_rdata.age_tx_ring_paddr = 732 1.28.4.2 yamt sc->age_cdata.age_tx_ring_map->dm_segs[0].ds_addr; 733 1.28.4.2 yamt 734 1.28.4.2 yamt /* 735 1.28.4.2 yamt * Create DMA stuffs for RX ring 736 1.28.4.2 yamt */ 737 1.28.4.2 yamt error = bus_dmamap_create(sc->sc_dmat, AGE_RX_RING_SZ, 1, 738 1.28.4.2 yamt AGE_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_ring_map); 739 1.28.4.2 yamt if (error) { 740 1.28.4.2 yamt sc->age_cdata.age_rx_ring_map = NULL; 741 1.28.4.2 yamt return ENOBUFS; 742 1.28.4.2 yamt } 743 1.28.4.2 yamt 744 1.28.4.2 yamt /* Allocate DMA'able memory for RX ring */ 745 1.28.4.2 yamt error = bus_dmamem_alloc(sc->sc_dmat, AGE_RX_RING_SZ, 746 1.28.4.2 yamt ETHER_ALIGN, 0, &sc->age_rdata.age_rx_ring_seg, 1, 747 1.28.4.2 yamt &nsegs, BUS_DMA_WAITOK); 748 1.28.4.2 yamt if (error) { 749 1.28.4.2 yamt printf("%s: could not allocate DMA'able memory for Rx ring, " 750 1.28.4.2 yamt "error = %i.\n", device_xname(sc->sc_dev), error); 751 1.28.4.2 yamt return error; 752 1.28.4.2 yamt } 753 1.28.4.2 yamt 754 1.28.4.2 yamt error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rx_ring_seg, 755 1.28.4.2 yamt nsegs, AGE_RX_RING_SZ, (void **)&sc->age_rdata.age_rx_ring, 756 1.28.4.2 yamt BUS_DMA_NOWAIT); 757 1.28.4.2 yamt if (error) 758 1.28.4.2 yamt return ENOBUFS; 759 1.28.4.2 yamt 760 1.28.4.2 yamt memset(sc->age_rdata.age_rx_ring, 0, AGE_RX_RING_SZ); 761 1.28.4.2 yamt 762 1.28.4.2 yamt /* Load the DMA map for Rx ring. */ 763 1.28.4.2 yamt error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 764 1.28.4.2 yamt sc->age_rdata.age_rx_ring, AGE_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 765 1.28.4.2 yamt if (error) { 766 1.28.4.2 yamt printf("%s: could not load DMA'able memory for Rx ring, " 767 1.28.4.2 yamt "error = %i.\n", device_xname(sc->sc_dev), error); 768 1.28.4.2 yamt bus_dmamem_free(sc->sc_dmat, 769 1.28.4.2 yamt &sc->age_rdata.age_rx_ring_seg, 1); 770 1.28.4.2 yamt return error; 771 1.28.4.2 yamt } 772 1.28.4.2 yamt 773 1.28.4.2 yamt sc->age_rdata.age_rx_ring_paddr = 774 1.28.4.2 yamt sc->age_cdata.age_rx_ring_map->dm_segs[0].ds_addr; 775 1.28.4.2 yamt 776 1.28.4.2 yamt /* 777 1.28.4.2 yamt * Create DMA stuffs for RX return ring 778 1.28.4.2 yamt */ 779 1.28.4.2 yamt error = bus_dmamap_create(sc->sc_dmat, AGE_RR_RING_SZ, 1, 780 1.28.4.2 yamt AGE_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rr_ring_map); 781 1.28.4.2 yamt if (error) { 782 1.28.4.2 yamt sc->age_cdata.age_rr_ring_map = NULL; 783 1.28.4.2 yamt return ENOBUFS; 784 1.28.4.2 yamt } 785 1.28.4.2 yamt 786 1.28.4.2 yamt /* Allocate DMA'able memory for RX return ring */ 787 1.28.4.2 yamt error = bus_dmamem_alloc(sc->sc_dmat, AGE_RR_RING_SZ, 788 1.28.4.2 yamt ETHER_ALIGN, 0, &sc->age_rdata.age_rr_ring_seg, 1, 789 1.28.4.2 yamt &nsegs, BUS_DMA_WAITOK); 790 1.28.4.2 yamt if (error) { 791 1.28.4.2 yamt printf("%s: could not allocate DMA'able memory for Rx " 792 1.28.4.2 yamt "return ring, error = %i.\n", 793 1.28.4.2 yamt device_xname(sc->sc_dev), error); 794 1.28.4.2 yamt return error; 795 1.28.4.2 yamt } 796 1.28.4.2 yamt 797 1.28.4.2 yamt error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rr_ring_seg, 798 1.28.4.2 yamt nsegs, AGE_RR_RING_SZ, (void **)&sc->age_rdata.age_rr_ring, 799 1.28.4.2 yamt BUS_DMA_NOWAIT); 800 1.28.4.2 yamt if (error) 801 1.28.4.2 yamt return ENOBUFS; 802 1.28.4.2 yamt 803 1.28.4.2 yamt memset(sc->age_rdata.age_rr_ring, 0, AGE_RR_RING_SZ); 804 1.28.4.2 yamt 805 1.28.4.2 yamt /* Load the DMA map for Rx return ring. */ 806 1.28.4.2 yamt error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 807 1.28.4.2 yamt sc->age_rdata.age_rr_ring, AGE_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 808 1.28.4.2 yamt if (error) { 809 1.28.4.2 yamt printf("%s: could not load DMA'able memory for Rx return ring, " 810 1.28.4.2 yamt "error = %i\n", device_xname(sc->sc_dev), error); 811 1.28.4.2 yamt bus_dmamem_free(sc->sc_dmat, 812 1.28.4.2 yamt &sc->age_rdata.age_rr_ring_seg, 1); 813 1.28.4.2 yamt return error; 814 1.28.4.2 yamt } 815 1.28.4.2 yamt 816 1.28.4.2 yamt sc->age_rdata.age_rr_ring_paddr = 817 1.28.4.2 yamt sc->age_cdata.age_rr_ring_map->dm_segs[0].ds_addr; 818 1.28.4.2 yamt 819 1.28.4.2 yamt /* 820 1.28.4.2 yamt * Create DMA stuffs for CMB block 821 1.28.4.2 yamt */ 822 1.28.4.2 yamt error = bus_dmamap_create(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 1, 823 1.28.4.2 yamt AGE_CMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 824 1.28.4.2 yamt &sc->age_cdata.age_cmb_block_map); 825 1.28.4.2 yamt if (error) { 826 1.28.4.2 yamt sc->age_cdata.age_cmb_block_map = NULL; 827 1.28.4.2 yamt return ENOBUFS; 828 1.28.4.2 yamt } 829 1.28.4.2 yamt 830 1.28.4.2 yamt /* Allocate DMA'able memory for CMB block */ 831 1.28.4.2 yamt error = bus_dmamem_alloc(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 832 1.28.4.2 yamt ETHER_ALIGN, 0, &sc->age_rdata.age_cmb_block_seg, 1, 833 1.28.4.2 yamt &nsegs, BUS_DMA_WAITOK); 834 1.28.4.2 yamt if (error) { 835 1.28.4.2 yamt printf("%s: could not allocate DMA'able memory for " 836 1.28.4.2 yamt "CMB block, error = %i\n", device_xname(sc->sc_dev), error); 837 1.28.4.2 yamt return error; 838 1.28.4.2 yamt } 839 1.28.4.2 yamt 840 1.28.4.2 yamt error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_cmb_block_seg, 841 1.28.4.2 yamt nsegs, AGE_CMB_BLOCK_SZ, (void **)&sc->age_rdata.age_cmb_block, 842 1.28.4.2 yamt BUS_DMA_NOWAIT); 843 1.28.4.2 yamt if (error) 844 1.28.4.2 yamt return ENOBUFS; 845 1.28.4.2 yamt 846 1.28.4.2 yamt memset(sc->age_rdata.age_cmb_block, 0, AGE_CMB_BLOCK_SZ); 847 1.28.4.2 yamt 848 1.28.4.2 yamt /* Load the DMA map for CMB block. */ 849 1.28.4.2 yamt error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 850 1.28.4.2 yamt sc->age_rdata.age_cmb_block, AGE_CMB_BLOCK_SZ, NULL, 851 1.28.4.2 yamt BUS_DMA_WAITOK); 852 1.28.4.2 yamt if (error) { 853 1.28.4.2 yamt printf("%s: could not load DMA'able memory for CMB block, " 854 1.28.4.2 yamt "error = %i\n", device_xname(sc->sc_dev), error); 855 1.28.4.2 yamt bus_dmamem_free(sc->sc_dmat, 856 1.28.4.2 yamt &sc->age_rdata.age_cmb_block_seg, 1); 857 1.28.4.2 yamt return error; 858 1.28.4.2 yamt } 859 1.28.4.2 yamt 860 1.28.4.2 yamt sc->age_rdata.age_cmb_block_paddr = 861 1.28.4.2 yamt sc->age_cdata.age_cmb_block_map->dm_segs[0].ds_addr; 862 1.28.4.2 yamt 863 1.28.4.2 yamt /* 864 1.28.4.2 yamt * Create DMA stuffs for SMB block 865 1.28.4.2 yamt */ 866 1.28.4.2 yamt error = bus_dmamap_create(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 1, 867 1.28.4.2 yamt AGE_SMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 868 1.28.4.2 yamt &sc->age_cdata.age_smb_block_map); 869 1.28.4.2 yamt if (error) { 870 1.28.4.2 yamt sc->age_cdata.age_smb_block_map = NULL; 871 1.28.4.2 yamt return ENOBUFS; 872 1.28.4.2 yamt } 873 1.28.4.2 yamt 874 1.28.4.2 yamt /* Allocate DMA'able memory for SMB block */ 875 1.28.4.2 yamt error = bus_dmamem_alloc(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 876 1.28.4.2 yamt ETHER_ALIGN, 0, &sc->age_rdata.age_smb_block_seg, 1, 877 1.28.4.2 yamt &nsegs, BUS_DMA_WAITOK); 878 1.28.4.2 yamt if (error) { 879 1.28.4.2 yamt printf("%s: could not allocate DMA'able memory for " 880 1.28.4.2 yamt "SMB block, error = %i\n", device_xname(sc->sc_dev), error); 881 1.28.4.2 yamt return error; 882 1.28.4.2 yamt } 883 1.28.4.2 yamt 884 1.28.4.2 yamt error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_smb_block_seg, 885 1.28.4.2 yamt nsegs, AGE_SMB_BLOCK_SZ, (void **)&sc->age_rdata.age_smb_block, 886 1.28.4.2 yamt BUS_DMA_NOWAIT); 887 1.28.4.2 yamt if (error) 888 1.28.4.2 yamt return ENOBUFS; 889 1.28.4.2 yamt 890 1.28.4.2 yamt memset(sc->age_rdata.age_smb_block, 0, AGE_SMB_BLOCK_SZ); 891 1.28.4.2 yamt 892 1.28.4.2 yamt /* Load the DMA map for SMB block */ 893 1.28.4.2 yamt error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 894 1.28.4.2 yamt sc->age_rdata.age_smb_block, AGE_SMB_BLOCK_SZ, NULL, 895 1.28.4.2 yamt BUS_DMA_WAITOK); 896 1.28.4.2 yamt if (error) { 897 1.28.4.2 yamt printf("%s: could not load DMA'able memory for SMB block, " 898 1.28.4.2 yamt "error = %i\n", device_xname(sc->sc_dev), error); 899 1.28.4.2 yamt bus_dmamem_free(sc->sc_dmat, 900 1.28.4.2 yamt &sc->age_rdata.age_smb_block_seg, 1); 901 1.28.4.2 yamt return error; 902 1.28.4.2 yamt } 903 1.28.4.2 yamt 904 1.28.4.2 yamt sc->age_rdata.age_smb_block_paddr = 905 1.28.4.2 yamt sc->age_cdata.age_smb_block_map->dm_segs[0].ds_addr; 906 1.28.4.2 yamt 907 1.28.4.2 yamt /* Create DMA maps for Tx buffers. */ 908 1.28.4.2 yamt for (i = 0; i < AGE_TX_RING_CNT; i++) { 909 1.28.4.2 yamt txd = &sc->age_cdata.age_txdesc[i]; 910 1.28.4.2 yamt txd->tx_m = NULL; 911 1.28.4.2 yamt txd->tx_dmamap = NULL; 912 1.28.4.2 yamt error = bus_dmamap_create(sc->sc_dmat, AGE_TSO_MAXSIZE, 913 1.28.4.2 yamt AGE_MAXTXSEGS, AGE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 914 1.28.4.2 yamt &txd->tx_dmamap); 915 1.28.4.2 yamt if (error) { 916 1.28.4.2 yamt txd->tx_dmamap = NULL; 917 1.28.4.2 yamt printf("%s: could not create Tx dmamap, error = %i.\n", 918 1.28.4.2 yamt device_xname(sc->sc_dev), error); 919 1.28.4.2 yamt return error; 920 1.28.4.2 yamt } 921 1.28.4.2 yamt } 922 1.28.4.2 yamt 923 1.28.4.2 yamt /* Create DMA maps for Rx buffers. */ 924 1.28.4.2 yamt error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 925 1.28.4.2 yamt BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_sparemap); 926 1.28.4.2 yamt if (error) { 927 1.28.4.2 yamt sc->age_cdata.age_rx_sparemap = NULL; 928 1.28.4.2 yamt printf("%s: could not create spare Rx dmamap, error = %i.\n", 929 1.28.4.2 yamt device_xname(sc->sc_dev), error); 930 1.28.4.2 yamt return error; 931 1.28.4.2 yamt } 932 1.28.4.2 yamt for (i = 0; i < AGE_RX_RING_CNT; i++) { 933 1.28.4.2 yamt rxd = &sc->age_cdata.age_rxdesc[i]; 934 1.28.4.2 yamt rxd->rx_m = NULL; 935 1.28.4.2 yamt rxd->rx_dmamap = NULL; 936 1.28.4.2 yamt error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 937 1.28.4.2 yamt MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 938 1.28.4.2 yamt if (error) { 939 1.28.4.2 yamt rxd->rx_dmamap = NULL; 940 1.28.4.2 yamt printf("%s: could not create Rx dmamap, error = %i.\n", 941 1.28.4.2 yamt device_xname(sc->sc_dev), error); 942 1.28.4.2 yamt return error; 943 1.28.4.2 yamt } 944 1.28.4.2 yamt } 945 1.28.4.2 yamt 946 1.28.4.2 yamt return 0; 947 1.28.4.2 yamt } 948 1.28.4.2 yamt 949 1.28.4.2 yamt static void 950 1.28.4.2 yamt age_dma_free(struct age_softc *sc) 951 1.28.4.2 yamt { 952 1.28.4.2 yamt struct age_txdesc *txd; 953 1.28.4.2 yamt struct age_rxdesc *rxd; 954 1.28.4.2 yamt int i; 955 1.28.4.2 yamt 956 1.28.4.2 yamt /* Tx buffers */ 957 1.28.4.2 yamt for (i = 0; i < AGE_TX_RING_CNT; i++) { 958 1.28.4.2 yamt txd = &sc->age_cdata.age_txdesc[i]; 959 1.28.4.2 yamt if (txd->tx_dmamap != NULL) { 960 1.28.4.2 yamt bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 961 1.28.4.2 yamt txd->tx_dmamap = NULL; 962 1.28.4.2 yamt } 963 1.28.4.2 yamt } 964 1.28.4.2 yamt /* Rx buffers */ 965 1.28.4.2 yamt for (i = 0; i < AGE_RX_RING_CNT; i++) { 966 1.28.4.2 yamt rxd = &sc->age_cdata.age_rxdesc[i]; 967 1.28.4.2 yamt if (rxd->rx_dmamap != NULL) { 968 1.28.4.2 yamt bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 969 1.28.4.2 yamt rxd->rx_dmamap = NULL; 970 1.28.4.2 yamt } 971 1.28.4.2 yamt } 972 1.28.4.2 yamt if (sc->age_cdata.age_rx_sparemap != NULL) { 973 1.28.4.2 yamt bus_dmamap_destroy(sc->sc_dmat, sc->age_cdata.age_rx_sparemap); 974 1.28.4.2 yamt sc->age_cdata.age_rx_sparemap = NULL; 975 1.28.4.2 yamt } 976 1.28.4.2 yamt 977 1.28.4.2 yamt /* Tx ring. */ 978 1.28.4.2 yamt if (sc->age_cdata.age_tx_ring_map != NULL) 979 1.28.4.2 yamt bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_tx_ring_map); 980 1.28.4.2 yamt if (sc->age_cdata.age_tx_ring_map != NULL && 981 1.28.4.2 yamt sc->age_rdata.age_tx_ring != NULL) 982 1.28.4.2 yamt bus_dmamem_free(sc->sc_dmat, 983 1.28.4.2 yamt &sc->age_rdata.age_tx_ring_seg, 1); 984 1.28.4.2 yamt sc->age_rdata.age_tx_ring = NULL; 985 1.28.4.2 yamt sc->age_cdata.age_tx_ring_map = NULL; 986 1.28.4.2 yamt 987 1.28.4.2 yamt /* Rx ring. */ 988 1.28.4.2 yamt if (sc->age_cdata.age_rx_ring_map != NULL) 989 1.28.4.2 yamt bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rx_ring_map); 990 1.28.4.2 yamt if (sc->age_cdata.age_rx_ring_map != NULL && 991 1.28.4.2 yamt sc->age_rdata.age_rx_ring != NULL) 992 1.28.4.2 yamt bus_dmamem_free(sc->sc_dmat, 993 1.28.4.2 yamt &sc->age_rdata.age_rx_ring_seg, 1); 994 1.28.4.2 yamt sc->age_rdata.age_rx_ring = NULL; 995 1.28.4.2 yamt sc->age_cdata.age_rx_ring_map = NULL; 996 1.28.4.2 yamt 997 1.28.4.2 yamt /* Rx return ring. */ 998 1.28.4.2 yamt if (sc->age_cdata.age_rr_ring_map != NULL) 999 1.28.4.2 yamt bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rr_ring_map); 1000 1.28.4.2 yamt if (sc->age_cdata.age_rr_ring_map != NULL && 1001 1.28.4.2 yamt sc->age_rdata.age_rr_ring != NULL) 1002 1.28.4.2 yamt bus_dmamem_free(sc->sc_dmat, 1003 1.28.4.2 yamt &sc->age_rdata.age_rr_ring_seg, 1); 1004 1.28.4.2 yamt sc->age_rdata.age_rr_ring = NULL; 1005 1.28.4.2 yamt sc->age_cdata.age_rr_ring_map = NULL; 1006 1.28.4.2 yamt 1007 1.28.4.2 yamt /* CMB block */ 1008 1.28.4.2 yamt if (sc->age_cdata.age_cmb_block_map != NULL) 1009 1.28.4.2 yamt bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_cmb_block_map); 1010 1.28.4.2 yamt if (sc->age_cdata.age_cmb_block_map != NULL && 1011 1.28.4.2 yamt sc->age_rdata.age_cmb_block != NULL) 1012 1.28.4.2 yamt bus_dmamem_free(sc->sc_dmat, 1013 1.28.4.2 yamt &sc->age_rdata.age_cmb_block_seg, 1); 1014 1.28.4.2 yamt sc->age_rdata.age_cmb_block = NULL; 1015 1.28.4.2 yamt sc->age_cdata.age_cmb_block_map = NULL; 1016 1.28.4.2 yamt 1017 1.28.4.2 yamt /* SMB block */ 1018 1.28.4.2 yamt if (sc->age_cdata.age_smb_block_map != NULL) 1019 1.28.4.2 yamt bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_smb_block_map); 1020 1.28.4.2 yamt if (sc->age_cdata.age_smb_block_map != NULL && 1021 1.28.4.2 yamt sc->age_rdata.age_smb_block != NULL) 1022 1.28.4.2 yamt bus_dmamem_free(sc->sc_dmat, 1023 1.28.4.2 yamt &sc->age_rdata.age_smb_block_seg, 1); 1024 1.28.4.2 yamt sc->age_rdata.age_smb_block = NULL; 1025 1.28.4.2 yamt sc->age_cdata.age_smb_block_map = NULL; 1026 1.28.4.2 yamt } 1027 1.28.4.2 yamt 1028 1.28.4.2 yamt static void 1029 1.28.4.2 yamt age_start(struct ifnet *ifp) 1030 1.28.4.2 yamt { 1031 1.28.4.2 yamt struct age_softc *sc = ifp->if_softc; 1032 1.28.4.2 yamt struct mbuf *m_head; 1033 1.28.4.2 yamt int enq; 1034 1.28.4.2 yamt 1035 1.28.4.2 yamt if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1036 1.28.4.2 yamt return; 1037 1.28.4.2 yamt 1038 1.28.4.2 yamt enq = 0; 1039 1.28.4.2 yamt for (;;) { 1040 1.28.4.2 yamt IFQ_DEQUEUE(&ifp->if_snd, m_head); 1041 1.28.4.2 yamt if (m_head == NULL) 1042 1.28.4.2 yamt break; 1043 1.28.4.2 yamt 1044 1.28.4.2 yamt /* 1045 1.28.4.2 yamt * Pack the data into the transmit ring. If we 1046 1.28.4.2 yamt * don't have room, set the OACTIVE flag and wait 1047 1.28.4.2 yamt * for the NIC to drain the ring. 1048 1.28.4.2 yamt */ 1049 1.28.4.2 yamt if (age_encap(sc, &m_head)) { 1050 1.28.4.2 yamt if (m_head == NULL) 1051 1.28.4.2 yamt break; 1052 1.28.4.5 yamt IF_PREPEND(&ifp->if_snd, m_head); 1053 1.28.4.2 yamt ifp->if_flags |= IFF_OACTIVE; 1054 1.28.4.2 yamt break; 1055 1.28.4.2 yamt } 1056 1.28.4.2 yamt enq = 1; 1057 1.28.4.2 yamt 1058 1.28.4.2 yamt /* 1059 1.28.4.2 yamt * If there's a BPF listener, bounce a copy of this frame 1060 1.28.4.2 yamt * to him. 1061 1.28.4.2 yamt */ 1062 1.28.4.2 yamt if (ifp->if_bpf != NULL) 1063 1.28.4.5 yamt bpf_ops->bpf_mtap(ifp->if_bpf, m_head); 1064 1.28.4.2 yamt } 1065 1.28.4.2 yamt 1066 1.28.4.2 yamt if (enq) { 1067 1.28.4.2 yamt /* Update mbox. */ 1068 1.28.4.2 yamt AGE_COMMIT_MBOX(sc); 1069 1.28.4.2 yamt /* Set a timeout in case the chip goes out to lunch. */ 1070 1.28.4.2 yamt ifp->if_timer = AGE_TX_TIMEOUT; 1071 1.28.4.2 yamt } 1072 1.28.4.2 yamt } 1073 1.28.4.2 yamt 1074 1.28.4.2 yamt static void 1075 1.28.4.2 yamt age_watchdog(struct ifnet *ifp) 1076 1.28.4.2 yamt { 1077 1.28.4.2 yamt struct age_softc *sc = ifp->if_softc; 1078 1.28.4.2 yamt 1079 1.28.4.2 yamt if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1080 1.28.4.2 yamt printf("%s: watchdog timeout (missed link)\n", 1081 1.28.4.2 yamt device_xname(sc->sc_dev)); 1082 1.28.4.2 yamt ifp->if_oerrors++; 1083 1.28.4.2 yamt age_init(ifp); 1084 1.28.4.2 yamt return; 1085 1.28.4.2 yamt } 1086 1.28.4.2 yamt 1087 1.28.4.2 yamt if (sc->age_cdata.age_tx_cnt == 0) { 1088 1.28.4.2 yamt printf("%s: watchdog timeout (missed Tx interrupts) " 1089 1.28.4.2 yamt "-- recovering\n", device_xname(sc->sc_dev)); 1090 1.28.4.2 yamt if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1091 1.28.4.2 yamt age_start(ifp); 1092 1.28.4.2 yamt return; 1093 1.28.4.2 yamt } 1094 1.28.4.2 yamt 1095 1.28.4.2 yamt printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1096 1.28.4.2 yamt ifp->if_oerrors++; 1097 1.28.4.2 yamt age_init(ifp); 1098 1.28.4.2 yamt 1099 1.28.4.2 yamt if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1100 1.28.4.2 yamt age_start(ifp); 1101 1.28.4.2 yamt } 1102 1.28.4.2 yamt 1103 1.28.4.2 yamt static int 1104 1.28.4.2 yamt age_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1105 1.28.4.2 yamt { 1106 1.28.4.2 yamt struct age_softc *sc = ifp->if_softc; 1107 1.28.4.2 yamt int s, error; 1108 1.28.4.2 yamt 1109 1.28.4.2 yamt s = splnet(); 1110 1.28.4.2 yamt 1111 1.28.4.2 yamt error = ether_ioctl(ifp, cmd, data); 1112 1.28.4.2 yamt if (error == ENETRESET) { 1113 1.28.4.2 yamt if (ifp->if_flags & IFF_RUNNING) 1114 1.28.4.2 yamt age_rxfilter(sc); 1115 1.28.4.2 yamt error = 0; 1116 1.28.4.2 yamt } 1117 1.28.4.2 yamt 1118 1.28.4.2 yamt splx(s); 1119 1.28.4.2 yamt return error; 1120 1.28.4.2 yamt } 1121 1.28.4.2 yamt 1122 1.28.4.2 yamt static void 1123 1.28.4.2 yamt age_mac_config(struct age_softc *sc) 1124 1.28.4.2 yamt { 1125 1.28.4.2 yamt struct mii_data *mii; 1126 1.28.4.2 yamt uint32_t reg; 1127 1.28.4.2 yamt 1128 1.28.4.2 yamt mii = &sc->sc_miibus; 1129 1.28.4.2 yamt 1130 1.28.4.2 yamt reg = CSR_READ_4(sc, AGE_MAC_CFG); 1131 1.28.4.2 yamt reg &= ~MAC_CFG_FULL_DUPLEX; 1132 1.28.4.2 yamt reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1133 1.28.4.2 yamt reg &= ~MAC_CFG_SPEED_MASK; 1134 1.28.4.2 yamt 1135 1.28.4.2 yamt /* Reprogram MAC with resolved speed/duplex. */ 1136 1.28.4.2 yamt switch (IFM_SUBTYPE(mii->mii_media_active)) { 1137 1.28.4.2 yamt case IFM_10_T: 1138 1.28.4.2 yamt case IFM_100_TX: 1139 1.28.4.2 yamt reg |= MAC_CFG_SPEED_10_100; 1140 1.28.4.2 yamt break; 1141 1.28.4.2 yamt case IFM_1000_T: 1142 1.28.4.2 yamt reg |= MAC_CFG_SPEED_1000; 1143 1.28.4.2 yamt break; 1144 1.28.4.2 yamt } 1145 1.28.4.2 yamt if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1146 1.28.4.2 yamt reg |= MAC_CFG_FULL_DUPLEX; 1147 1.28.4.2 yamt if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1148 1.28.4.2 yamt reg |= MAC_CFG_TX_FC; 1149 1.28.4.2 yamt if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1150 1.28.4.2 yamt reg |= MAC_CFG_RX_FC; 1151 1.28.4.2 yamt } 1152 1.28.4.2 yamt 1153 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1154 1.28.4.2 yamt } 1155 1.28.4.2 yamt 1156 1.28.4.2 yamt static bool 1157 1.28.4.5 yamt age_resume(device_t dv, const pmf_qual_t *qual) 1158 1.28.4.2 yamt { 1159 1.28.4.2 yamt struct age_softc *sc = device_private(dv); 1160 1.28.4.2 yamt uint16_t cmd; 1161 1.28.4.2 yamt 1162 1.28.4.2 yamt /* 1163 1.28.4.2 yamt * Clear INTx emulation disable for hardware that 1164 1.28.4.2 yamt * is set in resume event. From Linux. 1165 1.28.4.2 yamt */ 1166 1.28.4.2 yamt cmd = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 1167 1.28.4.2 yamt if ((cmd & PCI_COMMAND_INTERRUPT_DISABLE) != 0) { 1168 1.28.4.2 yamt cmd &= ~PCI_COMMAND_INTERRUPT_DISABLE; 1169 1.28.4.2 yamt pci_conf_write(sc->sc_pct, sc->sc_pcitag, 1170 1.28.4.2 yamt PCI_COMMAND_STATUS_REG, cmd); 1171 1.28.4.2 yamt } 1172 1.28.4.2 yamt 1173 1.28.4.2 yamt return true; 1174 1.28.4.2 yamt } 1175 1.28.4.2 yamt 1176 1.28.4.2 yamt static int 1177 1.28.4.2 yamt age_encap(struct age_softc *sc, struct mbuf **m_head) 1178 1.28.4.2 yamt { 1179 1.28.4.2 yamt struct age_txdesc *txd, *txd_last; 1180 1.28.4.2 yamt struct tx_desc *desc; 1181 1.28.4.2 yamt struct mbuf *m; 1182 1.28.4.2 yamt bus_dmamap_t map; 1183 1.28.4.2 yamt uint32_t cflags, poff, vtag; 1184 1.28.4.2 yamt int error, i, nsegs, prod; 1185 1.28.4.2 yamt #if NVLAN > 0 1186 1.28.4.2 yamt struct m_tag *mtag; 1187 1.28.4.2 yamt #endif 1188 1.28.4.2 yamt 1189 1.28.4.2 yamt m = *m_head; 1190 1.28.4.2 yamt cflags = vtag = 0; 1191 1.28.4.2 yamt poff = 0; 1192 1.28.4.2 yamt 1193 1.28.4.2 yamt prod = sc->age_cdata.age_tx_prod; 1194 1.28.4.2 yamt txd = &sc->age_cdata.age_txdesc[prod]; 1195 1.28.4.2 yamt txd_last = txd; 1196 1.28.4.2 yamt map = txd->tx_dmamap; 1197 1.28.4.2 yamt 1198 1.28.4.2 yamt error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1199 1.28.4.2 yamt 1200 1.28.4.2 yamt if (error == EFBIG) { 1201 1.28.4.2 yamt error = 0; 1202 1.28.4.2 yamt 1203 1.28.4.5 yamt *m_head = m_pullup(*m_head, MHLEN); 1204 1.28.4.5 yamt if (*m_head == NULL) { 1205 1.28.4.2 yamt printf("%s: can't defrag TX mbuf\n", 1206 1.28.4.2 yamt device_xname(sc->sc_dev)); 1207 1.28.4.2 yamt return ENOBUFS; 1208 1.28.4.2 yamt } 1209 1.28.4.2 yamt 1210 1.28.4.2 yamt error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1211 1.28.4.2 yamt BUS_DMA_NOWAIT); 1212 1.28.4.2 yamt 1213 1.28.4.2 yamt if (error != 0) { 1214 1.28.4.2 yamt printf("%s: could not load defragged TX mbuf\n", 1215 1.28.4.2 yamt device_xname(sc->sc_dev)); 1216 1.28.4.2 yamt m_freem(*m_head); 1217 1.28.4.2 yamt *m_head = NULL; 1218 1.28.4.2 yamt return error; 1219 1.28.4.2 yamt } 1220 1.28.4.2 yamt } else if (error) { 1221 1.28.4.2 yamt printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 1222 1.28.4.2 yamt return error; 1223 1.28.4.2 yamt } 1224 1.28.4.2 yamt 1225 1.28.4.2 yamt nsegs = map->dm_nsegs; 1226 1.28.4.2 yamt 1227 1.28.4.2 yamt if (nsegs == 0) { 1228 1.28.4.2 yamt m_freem(*m_head); 1229 1.28.4.2 yamt *m_head = NULL; 1230 1.28.4.2 yamt return EIO; 1231 1.28.4.2 yamt } 1232 1.28.4.2 yamt 1233 1.28.4.2 yamt /* Check descriptor overrun. */ 1234 1.28.4.2 yamt if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1235 1.28.4.2 yamt bus_dmamap_unload(sc->sc_dmat, map); 1236 1.28.4.2 yamt return ENOBUFS; 1237 1.28.4.2 yamt } 1238 1.28.4.2 yamt 1239 1.28.4.2 yamt m = *m_head; 1240 1.28.4.2 yamt /* Configure Tx IP/TCP/UDP checksum offload. */ 1241 1.28.4.2 yamt if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1242 1.28.4.2 yamt cflags |= AGE_TD_CSUM; 1243 1.28.4.2 yamt if ((m->m_pkthdr.csum_flags & M_CSUM_TCPv4) != 0) 1244 1.28.4.2 yamt cflags |= AGE_TD_TCPCSUM; 1245 1.28.4.2 yamt if ((m->m_pkthdr.csum_flags & M_CSUM_UDPv4) != 0) 1246 1.28.4.2 yamt cflags |= AGE_TD_UDPCSUM; 1247 1.28.4.2 yamt /* Set checksum start offset. */ 1248 1.28.4.2 yamt cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1249 1.28.4.2 yamt } 1250 1.28.4.2 yamt 1251 1.28.4.2 yamt #if NVLAN > 0 1252 1.28.4.2 yamt /* Configure VLAN hardware tag insertion. */ 1253 1.28.4.2 yamt if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m))) { 1254 1.28.4.2 yamt vtag = AGE_TX_VLAN_TAG(htons(VLAN_TAG_VALUE(mtag))); 1255 1.28.4.2 yamt vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1256 1.28.4.2 yamt cflags |= AGE_TD_INSERT_VLAN_TAG; 1257 1.28.4.2 yamt } 1258 1.28.4.2 yamt #endif 1259 1.28.4.2 yamt 1260 1.28.4.2 yamt desc = NULL; 1261 1.28.4.2 yamt for (i = 0; i < nsegs; i++) { 1262 1.28.4.2 yamt desc = &sc->age_rdata.age_tx_ring[prod]; 1263 1.28.4.2 yamt desc->addr = htole64(map->dm_segs[i].ds_addr); 1264 1.28.4.2 yamt desc->len = 1265 1.28.4.2 yamt htole32(AGE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 1266 1.28.4.2 yamt desc->flags = htole32(cflags); 1267 1.28.4.2 yamt sc->age_cdata.age_tx_cnt++; 1268 1.28.4.2 yamt AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1269 1.28.4.2 yamt } 1270 1.28.4.2 yamt 1271 1.28.4.2 yamt /* Update producer index. */ 1272 1.28.4.2 yamt sc->age_cdata.age_tx_prod = prod; 1273 1.28.4.2 yamt 1274 1.28.4.2 yamt /* Set EOP on the last descriptor. */ 1275 1.28.4.2 yamt prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1276 1.28.4.2 yamt desc = &sc->age_rdata.age_tx_ring[prod]; 1277 1.28.4.2 yamt desc->flags |= htole32(AGE_TD_EOP); 1278 1.28.4.2 yamt 1279 1.28.4.2 yamt /* Swap dmamap of the first and the last. */ 1280 1.28.4.2 yamt txd = &sc->age_cdata.age_txdesc[prod]; 1281 1.28.4.2 yamt map = txd_last->tx_dmamap; 1282 1.28.4.2 yamt txd_last->tx_dmamap = txd->tx_dmamap; 1283 1.28.4.2 yamt txd->tx_dmamap = map; 1284 1.28.4.2 yamt txd->tx_m = m; 1285 1.28.4.2 yamt 1286 1.28.4.2 yamt /* Sync descriptors. */ 1287 1.28.4.2 yamt bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1288 1.28.4.2 yamt BUS_DMASYNC_PREWRITE); 1289 1.28.4.2 yamt bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1290 1.28.4.2 yamt sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1291 1.28.4.2 yamt 1292 1.28.4.2 yamt return 0; 1293 1.28.4.2 yamt } 1294 1.28.4.2 yamt 1295 1.28.4.2 yamt static void 1296 1.28.4.2 yamt age_txintr(struct age_softc *sc, int tpd_cons) 1297 1.28.4.2 yamt { 1298 1.28.4.2 yamt struct ifnet *ifp = &sc->sc_ec.ec_if; 1299 1.28.4.2 yamt struct age_txdesc *txd; 1300 1.28.4.2 yamt int cons, prog; 1301 1.28.4.2 yamt 1302 1.28.4.2 yamt bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1303 1.28.4.2 yamt sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1304 1.28.4.2 yamt 1305 1.28.4.2 yamt /* 1306 1.28.4.2 yamt * Go through our Tx list and free mbufs for those 1307 1.28.4.2 yamt * frames which have been transmitted. 1308 1.28.4.2 yamt */ 1309 1.28.4.2 yamt cons = sc->age_cdata.age_tx_cons; 1310 1.28.4.2 yamt for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 1311 1.28.4.2 yamt if (sc->age_cdata.age_tx_cnt <= 0) 1312 1.28.4.2 yamt break; 1313 1.28.4.2 yamt prog++; 1314 1.28.4.2 yamt ifp->if_flags &= ~IFF_OACTIVE; 1315 1.28.4.2 yamt sc->age_cdata.age_tx_cnt--; 1316 1.28.4.2 yamt txd = &sc->age_cdata.age_txdesc[cons]; 1317 1.28.4.2 yamt /* 1318 1.28.4.2 yamt * Clear Tx descriptors, it's not required but would 1319 1.28.4.2 yamt * help debugging in case of Tx issues. 1320 1.28.4.2 yamt */ 1321 1.28.4.2 yamt txd->tx_desc->addr = 0; 1322 1.28.4.2 yamt txd->tx_desc->len = 0; 1323 1.28.4.2 yamt txd->tx_desc->flags = 0; 1324 1.28.4.2 yamt 1325 1.28.4.2 yamt if (txd->tx_m == NULL) 1326 1.28.4.2 yamt continue; 1327 1.28.4.2 yamt /* Reclaim transmitted mbufs. */ 1328 1.28.4.2 yamt bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1329 1.28.4.2 yamt m_freem(txd->tx_m); 1330 1.28.4.2 yamt txd->tx_m = NULL; 1331 1.28.4.2 yamt } 1332 1.28.4.2 yamt 1333 1.28.4.2 yamt if (prog > 0) { 1334 1.28.4.2 yamt sc->age_cdata.age_tx_cons = cons; 1335 1.28.4.2 yamt 1336 1.28.4.2 yamt /* 1337 1.28.4.2 yamt * Unarm watchdog timer only when there are no pending 1338 1.28.4.2 yamt * Tx descriptors in queue. 1339 1.28.4.2 yamt */ 1340 1.28.4.2 yamt if (sc->age_cdata.age_tx_cnt == 0) 1341 1.28.4.2 yamt ifp->if_timer = 0; 1342 1.28.4.2 yamt 1343 1.28.4.2 yamt bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1344 1.28.4.2 yamt sc->age_cdata.age_tx_ring_map->dm_mapsize, 1345 1.28.4.2 yamt BUS_DMASYNC_PREWRITE); 1346 1.28.4.2 yamt } 1347 1.28.4.2 yamt } 1348 1.28.4.2 yamt 1349 1.28.4.2 yamt /* Receive a frame. */ 1350 1.28.4.2 yamt static void 1351 1.28.4.2 yamt age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 1352 1.28.4.2 yamt { 1353 1.28.4.2 yamt struct ifnet *ifp = &sc->sc_ec.ec_if; 1354 1.28.4.2 yamt struct age_rxdesc *rxd; 1355 1.28.4.2 yamt struct rx_desc *desc; 1356 1.28.4.2 yamt struct mbuf *mp, *m; 1357 1.28.4.2 yamt uint32_t status, index; 1358 1.28.4.2 yamt int count, nsegs, pktlen; 1359 1.28.4.2 yamt int rx_cons; 1360 1.28.4.2 yamt 1361 1.28.4.2 yamt status = le32toh(rxrd->flags); 1362 1.28.4.2 yamt index = le32toh(rxrd->index); 1363 1.28.4.2 yamt rx_cons = AGE_RX_CONS(index); 1364 1.28.4.2 yamt nsegs = AGE_RX_NSEGS(index); 1365 1.28.4.2 yamt 1366 1.28.4.2 yamt sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 1367 1.28.4.2 yamt if ((status & AGE_RRD_ERROR) != 0 && 1368 1.28.4.2 yamt (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 1369 1.28.4.2 yamt AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) { 1370 1.28.4.2 yamt /* 1371 1.28.4.2 yamt * We want to pass the following frames to upper 1372 1.28.4.2 yamt * layer regardless of error status of Rx return 1373 1.28.4.2 yamt * ring. 1374 1.28.4.2 yamt * 1375 1.28.4.2 yamt * o IP/TCP/UDP checksum is bad. 1376 1.28.4.2 yamt * o frame length and protocol specific length 1377 1.28.4.2 yamt * does not match. 1378 1.28.4.2 yamt */ 1379 1.28.4.2 yamt sc->age_cdata.age_rx_cons += nsegs; 1380 1.28.4.2 yamt sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1381 1.28.4.2 yamt return; 1382 1.28.4.2 yamt } 1383 1.28.4.2 yamt 1384 1.28.4.2 yamt pktlen = 0; 1385 1.28.4.2 yamt for (count = 0; count < nsegs; count++, 1386 1.28.4.2 yamt AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 1387 1.28.4.2 yamt rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 1388 1.28.4.2 yamt mp = rxd->rx_m; 1389 1.28.4.2 yamt desc = rxd->rx_desc; 1390 1.28.4.2 yamt /* Add a new receive buffer to the ring. */ 1391 1.28.4.2 yamt if (age_newbuf(sc, rxd, 0) != 0) { 1392 1.28.4.2 yamt ifp->if_iqdrops++; 1393 1.28.4.2 yamt /* Reuse Rx buffers. */ 1394 1.28.4.2 yamt if (sc->age_cdata.age_rxhead != NULL) { 1395 1.28.4.2 yamt m_freem(sc->age_cdata.age_rxhead); 1396 1.28.4.2 yamt AGE_RXCHAIN_RESET(sc); 1397 1.28.4.2 yamt } 1398 1.28.4.2 yamt break; 1399 1.28.4.2 yamt } 1400 1.28.4.2 yamt 1401 1.28.4.2 yamt /* The length of the first mbuf is computed last. */ 1402 1.28.4.2 yamt if (count != 0) { 1403 1.28.4.2 yamt mp->m_len = AGE_RX_BYTES(le32toh(desc->len)); 1404 1.28.4.2 yamt pktlen += mp->m_len; 1405 1.28.4.2 yamt } 1406 1.28.4.2 yamt 1407 1.28.4.2 yamt /* Chain received mbufs. */ 1408 1.28.4.2 yamt if (sc->age_cdata.age_rxhead == NULL) { 1409 1.28.4.2 yamt sc->age_cdata.age_rxhead = mp; 1410 1.28.4.2 yamt sc->age_cdata.age_rxtail = mp; 1411 1.28.4.2 yamt } else { 1412 1.28.4.2 yamt mp->m_flags &= ~M_PKTHDR; 1413 1.28.4.2 yamt sc->age_cdata.age_rxprev_tail = 1414 1.28.4.2 yamt sc->age_cdata.age_rxtail; 1415 1.28.4.2 yamt sc->age_cdata.age_rxtail->m_next = mp; 1416 1.28.4.2 yamt sc->age_cdata.age_rxtail = mp; 1417 1.28.4.2 yamt } 1418 1.28.4.2 yamt 1419 1.28.4.2 yamt if (count == nsegs - 1) { 1420 1.28.4.2 yamt /* 1421 1.28.4.2 yamt * It seems that L1 controller has no way 1422 1.28.4.2 yamt * to tell hardware to strip CRC bytes. 1423 1.28.4.2 yamt */ 1424 1.28.4.2 yamt sc->age_cdata.age_rxlen -= ETHER_CRC_LEN; 1425 1.28.4.2 yamt if (nsegs > 1) { 1426 1.28.4.2 yamt /* Remove the CRC bytes in chained mbufs. */ 1427 1.28.4.2 yamt pktlen -= ETHER_CRC_LEN; 1428 1.28.4.2 yamt if (mp->m_len <= ETHER_CRC_LEN) { 1429 1.28.4.2 yamt sc->age_cdata.age_rxtail = 1430 1.28.4.2 yamt sc->age_cdata.age_rxprev_tail; 1431 1.28.4.2 yamt sc->age_cdata.age_rxtail->m_len -= 1432 1.28.4.2 yamt (ETHER_CRC_LEN - mp->m_len); 1433 1.28.4.2 yamt sc->age_cdata.age_rxtail->m_next = NULL; 1434 1.28.4.2 yamt m_freem(mp); 1435 1.28.4.2 yamt } else { 1436 1.28.4.2 yamt mp->m_len -= ETHER_CRC_LEN; 1437 1.28.4.2 yamt } 1438 1.28.4.2 yamt } 1439 1.28.4.2 yamt 1440 1.28.4.2 yamt m = sc->age_cdata.age_rxhead; 1441 1.28.4.2 yamt m->m_flags |= M_PKTHDR; 1442 1.28.4.2 yamt m->m_pkthdr.rcvif = ifp; 1443 1.28.4.2 yamt m->m_pkthdr.len = sc->age_cdata.age_rxlen; 1444 1.28.4.2 yamt /* Set the first mbuf length. */ 1445 1.28.4.2 yamt m->m_len = sc->age_cdata.age_rxlen - pktlen; 1446 1.28.4.2 yamt 1447 1.28.4.2 yamt /* 1448 1.28.4.2 yamt * Set checksum information. 1449 1.28.4.2 yamt * It seems that L1 controller can compute partial 1450 1.28.4.2 yamt * checksum. The partial checksum value can be used 1451 1.28.4.2 yamt * to accelerate checksum computation for fragmented 1452 1.28.4.2 yamt * TCP/UDP packets. Upper network stack already 1453 1.28.4.2 yamt * takes advantage of the partial checksum value in 1454 1.28.4.2 yamt * IP reassembly stage. But I'm not sure the 1455 1.28.4.2 yamt * correctness of the partial hardware checksum 1456 1.28.4.2 yamt * assistance due to lack of data sheet. If it is 1457 1.28.4.2 yamt * proven to work on L1 I'll enable it. 1458 1.28.4.2 yamt */ 1459 1.28.4.2 yamt if (status & AGE_RRD_IPV4) { 1460 1.28.4.2 yamt if (status & AGE_RRD_IPCSUM_NOK) 1461 1.28.4.2 yamt m->m_pkthdr.csum_flags |= 1462 1.28.4.2 yamt M_CSUM_IPv4_BAD; 1463 1.28.4.2 yamt if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 1464 1.28.4.2 yamt (status & AGE_RRD_TCP_UDPCSUM_NOK)) { 1465 1.28.4.2 yamt m->m_pkthdr.csum_flags |= 1466 1.28.4.2 yamt M_CSUM_TCP_UDP_BAD; 1467 1.28.4.2 yamt } 1468 1.28.4.2 yamt /* 1469 1.28.4.2 yamt * Don't mark bad checksum for TCP/UDP frames 1470 1.28.4.2 yamt * as fragmented frames may always have set 1471 1.28.4.2 yamt * bad checksummed bit of descriptor status. 1472 1.28.4.2 yamt */ 1473 1.28.4.2 yamt } 1474 1.28.4.2 yamt #if NVLAN > 0 1475 1.28.4.2 yamt /* Check for VLAN tagged frames. */ 1476 1.28.4.2 yamt if (status & AGE_RRD_VLAN) { 1477 1.28.4.2 yamt uint32_t vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 1478 1.28.4.2 yamt VLAN_INPUT_TAG(ifp, m, AGE_RX_VLAN_TAG(vtag), 1479 1.28.4.2 yamt continue); 1480 1.28.4.2 yamt } 1481 1.28.4.2 yamt #endif 1482 1.28.4.2 yamt 1483 1.28.4.2 yamt if (ifp->if_bpf) 1484 1.28.4.5 yamt bpf_ops->bpf_mtap(ifp->if_bpf, m); 1485 1.28.4.2 yamt /* Pass it on. */ 1486 1.28.4.2 yamt ether_input(ifp, m); 1487 1.28.4.2 yamt 1488 1.28.4.2 yamt /* Reset mbuf chains. */ 1489 1.28.4.2 yamt AGE_RXCHAIN_RESET(sc); 1490 1.28.4.2 yamt } 1491 1.28.4.2 yamt } 1492 1.28.4.2 yamt 1493 1.28.4.2 yamt if (count != nsegs) { 1494 1.28.4.2 yamt sc->age_cdata.age_rx_cons += nsegs; 1495 1.28.4.2 yamt sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1496 1.28.4.2 yamt } else 1497 1.28.4.2 yamt sc->age_cdata.age_rx_cons = rx_cons; 1498 1.28.4.2 yamt } 1499 1.28.4.2 yamt 1500 1.28.4.2 yamt static void 1501 1.28.4.2 yamt age_rxintr(struct age_softc *sc, int rr_prod) 1502 1.28.4.2 yamt { 1503 1.28.4.2 yamt struct rx_rdesc *rxrd; 1504 1.28.4.2 yamt int rr_cons, nsegs, pktlen, prog; 1505 1.28.4.2 yamt 1506 1.28.4.2 yamt rr_cons = sc->age_cdata.age_rr_cons; 1507 1.28.4.2 yamt if (rr_cons == rr_prod) 1508 1.28.4.2 yamt return; 1509 1.28.4.2 yamt 1510 1.28.4.2 yamt bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1511 1.28.4.2 yamt sc->age_cdata.age_rr_ring_map->dm_mapsize, 1512 1.28.4.2 yamt BUS_DMASYNC_POSTREAD); 1513 1.28.4.2 yamt 1514 1.28.4.2 yamt for (prog = 0; rr_cons != rr_prod; prog++) { 1515 1.28.4.2 yamt rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 1516 1.28.4.2 yamt nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 1517 1.28.4.2 yamt if (nsegs == 0) 1518 1.28.4.2 yamt break; 1519 1.28.4.2 yamt /* 1520 1.28.4.2 yamt * Check number of segments against received bytes 1521 1.28.4.2 yamt * Non-matching value would indicate that hardware 1522 1.28.4.2 yamt * is still trying to update Rx return descriptors. 1523 1.28.4.2 yamt * I'm not sure whether this check is really needed. 1524 1.28.4.2 yamt */ 1525 1.28.4.2 yamt pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 1526 1.28.4.2 yamt if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) / 1527 1.28.4.2 yamt (MCLBYTES - ETHER_ALIGN))) 1528 1.28.4.2 yamt break; 1529 1.28.4.2 yamt 1530 1.28.4.2 yamt /* Received a frame. */ 1531 1.28.4.2 yamt age_rxeof(sc, rxrd); 1532 1.28.4.2 yamt 1533 1.28.4.2 yamt /* Clear return ring. */ 1534 1.28.4.2 yamt rxrd->index = 0; 1535 1.28.4.2 yamt AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 1536 1.28.4.2 yamt } 1537 1.28.4.2 yamt 1538 1.28.4.2 yamt if (prog > 0) { 1539 1.28.4.2 yamt /* Update the consumer index. */ 1540 1.28.4.2 yamt sc->age_cdata.age_rr_cons = rr_cons; 1541 1.28.4.2 yamt 1542 1.28.4.2 yamt /* Sync descriptors. */ 1543 1.28.4.2 yamt bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1544 1.28.4.2 yamt sc->age_cdata.age_rr_ring_map->dm_mapsize, 1545 1.28.4.2 yamt BUS_DMASYNC_PREWRITE); 1546 1.28.4.2 yamt 1547 1.28.4.2 yamt /* Notify hardware availability of new Rx buffers. */ 1548 1.28.4.2 yamt AGE_COMMIT_MBOX(sc); 1549 1.28.4.2 yamt } 1550 1.28.4.2 yamt } 1551 1.28.4.2 yamt 1552 1.28.4.2 yamt static void 1553 1.28.4.2 yamt age_tick(void *xsc) 1554 1.28.4.2 yamt { 1555 1.28.4.2 yamt struct age_softc *sc = xsc; 1556 1.28.4.2 yamt struct mii_data *mii = &sc->sc_miibus; 1557 1.28.4.2 yamt int s; 1558 1.28.4.2 yamt 1559 1.28.4.2 yamt s = splnet(); 1560 1.28.4.2 yamt mii_tick(mii); 1561 1.28.4.2 yamt splx(s); 1562 1.28.4.2 yamt 1563 1.28.4.2 yamt callout_schedule(&sc->sc_tick_ch, hz); 1564 1.28.4.2 yamt } 1565 1.28.4.2 yamt 1566 1.28.4.2 yamt static void 1567 1.28.4.2 yamt age_reset(struct age_softc *sc) 1568 1.28.4.2 yamt { 1569 1.28.4.2 yamt uint32_t reg; 1570 1.28.4.2 yamt int i; 1571 1.28.4.2 yamt 1572 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 1573 1.28.4.3 yamt CSR_READ_4(sc, AGE_MASTER_CFG); 1574 1.28.4.3 yamt DELAY(1000); 1575 1.28.4.2 yamt for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1576 1.28.4.2 yamt if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1577 1.28.4.2 yamt break; 1578 1.28.4.2 yamt DELAY(10); 1579 1.28.4.2 yamt } 1580 1.28.4.2 yamt 1581 1.28.4.2 yamt if (i == 0) 1582 1.28.4.2 yamt printf("%s: reset timeout(0x%08x)!\n", device_xname(sc->sc_dev), 1583 1.28.4.2 yamt reg); 1584 1.28.4.2 yamt 1585 1.28.4.2 yamt /* Initialize PCIe module. From Linux. */ 1586 1.28.4.2 yamt CSR_WRITE_4(sc, 0x12FC, 0x6500); 1587 1.28.4.2 yamt CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1588 1.28.4.2 yamt } 1589 1.28.4.2 yamt 1590 1.28.4.2 yamt static int 1591 1.28.4.2 yamt age_init(struct ifnet *ifp) 1592 1.28.4.2 yamt { 1593 1.28.4.2 yamt struct age_softc *sc = ifp->if_softc; 1594 1.28.4.2 yamt struct mii_data *mii; 1595 1.28.4.2 yamt uint8_t eaddr[ETHER_ADDR_LEN]; 1596 1.28.4.2 yamt bus_addr_t paddr; 1597 1.28.4.2 yamt uint32_t reg, fsize; 1598 1.28.4.2 yamt uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 1599 1.28.4.2 yamt int error; 1600 1.28.4.2 yamt 1601 1.28.4.2 yamt /* 1602 1.28.4.2 yamt * Cancel any pending I/O. 1603 1.28.4.2 yamt */ 1604 1.28.4.2 yamt age_stop(ifp, 0); 1605 1.28.4.2 yamt 1606 1.28.4.2 yamt /* 1607 1.28.4.2 yamt * Reset the chip to a known state. 1608 1.28.4.2 yamt */ 1609 1.28.4.2 yamt age_reset(sc); 1610 1.28.4.2 yamt 1611 1.28.4.2 yamt /* Initialize descriptors. */ 1612 1.28.4.2 yamt error = age_init_rx_ring(sc); 1613 1.28.4.2 yamt if (error != 0) { 1614 1.28.4.2 yamt printf("%s: no memory for Rx buffers.\n", device_xname(sc->sc_dev)); 1615 1.28.4.2 yamt age_stop(ifp, 0); 1616 1.28.4.2 yamt return error; 1617 1.28.4.2 yamt } 1618 1.28.4.2 yamt age_init_rr_ring(sc); 1619 1.28.4.2 yamt age_init_tx_ring(sc); 1620 1.28.4.2 yamt age_init_cmb_block(sc); 1621 1.28.4.2 yamt age_init_smb_block(sc); 1622 1.28.4.2 yamt 1623 1.28.4.2 yamt /* Reprogram the station address. */ 1624 1.28.4.2 yamt memcpy(eaddr, CLLADDR(ifp->if_sadl), sizeof(eaddr)); 1625 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_PAR0, 1626 1.28.4.2 yamt eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1627 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 1628 1.28.4.2 yamt 1629 1.28.4.2 yamt /* Set descriptor base addresses. */ 1630 1.28.4.2 yamt paddr = sc->age_rdata.age_tx_ring_paddr; 1631 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 1632 1.28.4.2 yamt paddr = sc->age_rdata.age_rx_ring_paddr; 1633 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 1634 1.28.4.2 yamt paddr = sc->age_rdata.age_rr_ring_paddr; 1635 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 1636 1.28.4.2 yamt paddr = sc->age_rdata.age_tx_ring_paddr; 1637 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 1638 1.28.4.2 yamt paddr = sc->age_rdata.age_cmb_block_paddr; 1639 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1640 1.28.4.2 yamt paddr = sc->age_rdata.age_smb_block_paddr; 1641 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1642 1.28.4.2 yamt 1643 1.28.4.2 yamt /* Set Rx/Rx return descriptor counter. */ 1644 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 1645 1.28.4.2 yamt ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 1646 1.28.4.2 yamt DESC_RRD_CNT_MASK) | 1647 1.28.4.2 yamt ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 1648 1.28.4.2 yamt 1649 1.28.4.2 yamt /* Set Tx descriptor counter. */ 1650 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 1651 1.28.4.2 yamt (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 1652 1.28.4.2 yamt 1653 1.28.4.2 yamt /* Tell hardware that we're ready to load descriptors. */ 1654 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 1655 1.28.4.2 yamt 1656 1.28.4.2 yamt /* 1657 1.28.4.2 yamt * Initialize mailbox register. 1658 1.28.4.2 yamt * Updated producer/consumer index information is exchanged 1659 1.28.4.2 yamt * through this mailbox register. However Tx producer and 1660 1.28.4.2 yamt * Rx return consumer/Rx producer are all shared such that 1661 1.28.4.2 yamt * it's hard to separate code path between Tx and Rx without 1662 1.28.4.2 yamt * locking. If L1 hardware have a separate mail box register 1663 1.28.4.2 yamt * for Tx and Rx consumer/producer management we could have 1664 1.28.4.2 yamt * indepent Tx/Rx handler which in turn Rx handler could have 1665 1.28.4.2 yamt * been run without any locking. 1666 1.28.4.2 yamt */ 1667 1.28.4.2 yamt AGE_COMMIT_MBOX(sc); 1668 1.28.4.2 yamt 1669 1.28.4.2 yamt /* Configure IPG/IFG parameters. */ 1670 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 1671 1.28.4.2 yamt ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 1672 1.28.4.2 yamt ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1673 1.28.4.2 yamt ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1674 1.28.4.2 yamt ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 1675 1.28.4.2 yamt 1676 1.28.4.2 yamt /* Set parameters for half-duplex media. */ 1677 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_HDPX_CFG, 1678 1.28.4.2 yamt ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1679 1.28.4.2 yamt HDPX_CFG_LCOL_MASK) | 1680 1.28.4.2 yamt ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1681 1.28.4.2 yamt HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1682 1.28.4.2 yamt ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1683 1.28.4.2 yamt HDPX_CFG_ABEBT_MASK) | 1684 1.28.4.2 yamt ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1685 1.28.4.2 yamt HDPX_CFG_JAMIPG_MASK)); 1686 1.28.4.2 yamt 1687 1.28.4.2 yamt /* Configure interrupt moderation timer. */ 1688 1.28.4.2 yamt sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 1689 1.28.4.2 yamt CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 1690 1.28.4.2 yamt reg = CSR_READ_4(sc, AGE_MASTER_CFG); 1691 1.28.4.2 yamt reg &= ~MASTER_MTIMER_ENB; 1692 1.28.4.2 yamt if (AGE_USECS(sc->age_int_mod) == 0) 1693 1.28.4.2 yamt reg &= ~MASTER_ITIMER_ENB; 1694 1.28.4.2 yamt else 1695 1.28.4.2 yamt reg |= MASTER_ITIMER_ENB; 1696 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 1697 1.28.4.2 yamt if (agedebug) 1698 1.28.4.2 yamt printf("%s: interrupt moderation is %d us.\n", 1699 1.28.4.2 yamt device_xname(sc->sc_dev), sc->age_int_mod); 1700 1.28.4.2 yamt CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 1701 1.28.4.2 yamt 1702 1.28.4.2 yamt /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 1703 1.28.4.2 yamt if (ifp->if_mtu < ETHERMTU) 1704 1.28.4.2 yamt sc->age_max_frame_size = ETHERMTU; 1705 1.28.4.2 yamt else 1706 1.28.4.2 yamt sc->age_max_frame_size = ifp->if_mtu; 1707 1.28.4.2 yamt sc->age_max_frame_size += ETHER_HDR_LEN + 1708 1.28.4.2 yamt sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 1709 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 1710 1.28.4.2 yamt 1711 1.28.4.2 yamt /* Configure jumbo frame. */ 1712 1.28.4.2 yamt fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 1713 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 1714 1.28.4.2 yamt (((fsize / sizeof(uint64_t)) << 1715 1.28.4.2 yamt RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 1716 1.28.4.2 yamt ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 1717 1.28.4.2 yamt RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 1718 1.28.4.2 yamt ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 1719 1.28.4.2 yamt RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 1720 1.28.4.2 yamt 1721 1.28.4.2 yamt /* Configure flow-control parameters. From Linux. */ 1722 1.28.4.2 yamt if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 1723 1.28.4.2 yamt /* 1724 1.28.4.2 yamt * Magic workaround for old-L1. 1725 1.28.4.2 yamt * Don't know which hw revision requires this magic. 1726 1.28.4.2 yamt */ 1727 1.28.4.2 yamt CSR_WRITE_4(sc, 0x12FC, 0x6500); 1728 1.28.4.2 yamt /* 1729 1.28.4.2 yamt * Another magic workaround for flow-control mode 1730 1.28.4.2 yamt * change. From Linux. 1731 1.28.4.2 yamt */ 1732 1.28.4.2 yamt CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1733 1.28.4.2 yamt } 1734 1.28.4.2 yamt /* 1735 1.28.4.2 yamt * TODO 1736 1.28.4.2 yamt * Should understand pause parameter relationships between FIFO 1737 1.28.4.2 yamt * size and number of Rx descriptors and Rx return descriptors. 1738 1.28.4.2 yamt * 1739 1.28.4.2 yamt * Magic parameters came from Linux. 1740 1.28.4.2 yamt */ 1741 1.28.4.2 yamt switch (sc->age_chip_rev) { 1742 1.28.4.2 yamt case 0x8001: 1743 1.28.4.2 yamt case 0x9001: 1744 1.28.4.2 yamt case 0x9002: 1745 1.28.4.2 yamt case 0x9003: 1746 1.28.4.2 yamt rxf_hi = AGE_RX_RING_CNT / 16; 1747 1.28.4.2 yamt rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 1748 1.28.4.2 yamt rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 1749 1.28.4.2 yamt rrd_lo = AGE_RR_RING_CNT / 16; 1750 1.28.4.2 yamt break; 1751 1.28.4.2 yamt default: 1752 1.28.4.2 yamt reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 1753 1.28.4.2 yamt rxf_lo = reg / 16; 1754 1.28.4.2 yamt if (rxf_lo < 192) 1755 1.28.4.2 yamt rxf_lo = 192; 1756 1.28.4.2 yamt rxf_hi = (reg * 7) / 8; 1757 1.28.4.2 yamt if (rxf_hi < rxf_lo) 1758 1.28.4.2 yamt rxf_hi = rxf_lo + 16; 1759 1.28.4.2 yamt reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 1760 1.28.4.2 yamt rrd_lo = reg / 8; 1761 1.28.4.2 yamt rrd_hi = (reg * 7) / 8; 1762 1.28.4.2 yamt if (rrd_lo < 2) 1763 1.28.4.2 yamt rrd_lo = 2; 1764 1.28.4.2 yamt if (rrd_hi < rrd_lo) 1765 1.28.4.2 yamt rrd_hi = rrd_lo + 3; 1766 1.28.4.2 yamt break; 1767 1.28.4.2 yamt } 1768 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 1769 1.28.4.2 yamt ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 1770 1.28.4.2 yamt RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 1771 1.28.4.2 yamt ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 1772 1.28.4.2 yamt RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 1773 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 1774 1.28.4.2 yamt ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 1775 1.28.4.2 yamt RXQ_RRD_PAUSE_THRESH_LO_MASK) | 1776 1.28.4.2 yamt ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 1777 1.28.4.2 yamt RXQ_RRD_PAUSE_THRESH_HI_MASK)); 1778 1.28.4.2 yamt 1779 1.28.4.2 yamt /* Configure RxQ. */ 1780 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_RXQ_CFG, 1781 1.28.4.2 yamt ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 1782 1.28.4.2 yamt RXQ_CFG_RD_BURST_MASK) | 1783 1.28.4.2 yamt ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 1784 1.28.4.2 yamt RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 1785 1.28.4.2 yamt ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 1786 1.28.4.2 yamt RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 1787 1.28.4.2 yamt RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1788 1.28.4.2 yamt 1789 1.28.4.2 yamt /* Configure TxQ. */ 1790 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_TXQ_CFG, 1791 1.28.4.2 yamt ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1792 1.28.4.2 yamt TXQ_CFG_TPD_BURST_MASK) | 1793 1.28.4.2 yamt ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 1794 1.28.4.2 yamt TXQ_CFG_TX_FIFO_BURST_MASK) | 1795 1.28.4.2 yamt ((TXQ_CFG_TPD_FETCH_DEFAULT << 1796 1.28.4.2 yamt TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 1797 1.28.4.2 yamt TXQ_CFG_ENB); 1798 1.28.4.2 yamt 1799 1.28.4.2 yamt /* Configure DMA parameters. */ 1800 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_DMA_CFG, 1801 1.28.4.2 yamt DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 1802 1.28.4.2 yamt sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 1803 1.28.4.2 yamt sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 1804 1.28.4.2 yamt 1805 1.28.4.2 yamt /* Configure CMB DMA write threshold. */ 1806 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 1807 1.28.4.2 yamt ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 1808 1.28.4.2 yamt CMB_WR_THRESH_RRD_MASK) | 1809 1.28.4.2 yamt ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 1810 1.28.4.2 yamt CMB_WR_THRESH_TPD_MASK)); 1811 1.28.4.2 yamt 1812 1.28.4.2 yamt /* Set CMB/SMB timer and enable them. */ 1813 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 1814 1.28.4.2 yamt ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 1815 1.28.4.2 yamt ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 1816 1.28.4.2 yamt 1817 1.28.4.2 yamt /* Request SMB updates for every seconds. */ 1818 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 1819 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 1820 1.28.4.2 yamt 1821 1.28.4.2 yamt /* 1822 1.28.4.2 yamt * Disable all WOL bits as WOL can interfere normal Rx 1823 1.28.4.2 yamt * operation. 1824 1.28.4.2 yamt */ 1825 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1826 1.28.4.2 yamt 1827 1.28.4.2 yamt /* 1828 1.28.4.2 yamt * Configure Tx/Rx MACs. 1829 1.28.4.2 yamt * - Auto-padding for short frames. 1830 1.28.4.2 yamt * - Enable CRC generation. 1831 1.28.4.2 yamt * Start with full-duplex/1000Mbps media. Actual reconfiguration 1832 1.28.4.2 yamt * of MAC is followed after link establishment. 1833 1.28.4.2 yamt */ 1834 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_MAC_CFG, 1835 1.28.4.2 yamt MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 1836 1.28.4.2 yamt MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 1837 1.28.4.2 yamt ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1838 1.28.4.2 yamt MAC_CFG_PREAMBLE_MASK)); 1839 1.28.4.2 yamt 1840 1.28.4.2 yamt /* Set up the receive filter. */ 1841 1.28.4.2 yamt age_rxfilter(sc); 1842 1.28.4.2 yamt age_rxvlan(sc); 1843 1.28.4.2 yamt 1844 1.28.4.2 yamt reg = CSR_READ_4(sc, AGE_MAC_CFG); 1845 1.28.4.2 yamt reg |= MAC_CFG_RXCSUM_ENB; 1846 1.28.4.2 yamt 1847 1.28.4.2 yamt /* Ack all pending interrupts and clear it. */ 1848 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 1849 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 1850 1.28.4.2 yamt 1851 1.28.4.2 yamt /* Finally enable Tx/Rx MAC. */ 1852 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 1853 1.28.4.2 yamt 1854 1.28.4.2 yamt sc->age_flags &= ~AGE_FLAG_LINK; 1855 1.28.4.2 yamt 1856 1.28.4.2 yamt /* Switch to the current media. */ 1857 1.28.4.2 yamt mii = &sc->sc_miibus; 1858 1.28.4.2 yamt mii_mediachg(mii); 1859 1.28.4.2 yamt 1860 1.28.4.2 yamt callout_schedule(&sc->sc_tick_ch, hz); 1861 1.28.4.2 yamt 1862 1.28.4.2 yamt ifp->if_flags |= IFF_RUNNING; 1863 1.28.4.2 yamt ifp->if_flags &= ~IFF_OACTIVE; 1864 1.28.4.2 yamt 1865 1.28.4.2 yamt return 0; 1866 1.28.4.2 yamt } 1867 1.28.4.2 yamt 1868 1.28.4.2 yamt static void 1869 1.28.4.2 yamt age_stop(struct ifnet *ifp, int disable) 1870 1.28.4.2 yamt { 1871 1.28.4.2 yamt struct age_softc *sc = ifp->if_softc; 1872 1.28.4.2 yamt struct age_txdesc *txd; 1873 1.28.4.2 yamt struct age_rxdesc *rxd; 1874 1.28.4.2 yamt uint32_t reg; 1875 1.28.4.2 yamt int i; 1876 1.28.4.2 yamt 1877 1.28.4.2 yamt callout_stop(&sc->sc_tick_ch); 1878 1.28.4.2 yamt 1879 1.28.4.2 yamt /* 1880 1.28.4.2 yamt * Mark the interface down and cancel the watchdog timer. 1881 1.28.4.2 yamt */ 1882 1.28.4.2 yamt ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1883 1.28.4.2 yamt ifp->if_timer = 0; 1884 1.28.4.2 yamt 1885 1.28.4.2 yamt sc->age_flags &= ~AGE_FLAG_LINK; 1886 1.28.4.2 yamt 1887 1.28.4.2 yamt mii_down(&sc->sc_miibus); 1888 1.28.4.2 yamt 1889 1.28.4.2 yamt /* 1890 1.28.4.2 yamt * Disable interrupts. 1891 1.28.4.2 yamt */ 1892 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 1893 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 1894 1.28.4.2 yamt 1895 1.28.4.2 yamt /* Stop CMB/SMB updates. */ 1896 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 1897 1.28.4.2 yamt 1898 1.28.4.2 yamt /* Stop Rx/Tx MAC. */ 1899 1.28.4.2 yamt age_stop_rxmac(sc); 1900 1.28.4.2 yamt age_stop_txmac(sc); 1901 1.28.4.2 yamt 1902 1.28.4.2 yamt /* Stop DMA. */ 1903 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_DMA_CFG, 1904 1.28.4.2 yamt CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 1905 1.28.4.2 yamt 1906 1.28.4.2 yamt /* Stop TxQ/RxQ. */ 1907 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_TXQ_CFG, 1908 1.28.4.2 yamt CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 1909 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_RXQ_CFG, 1910 1.28.4.2 yamt CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 1911 1.28.4.2 yamt for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1912 1.28.4.2 yamt if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1913 1.28.4.2 yamt break; 1914 1.28.4.2 yamt DELAY(10); 1915 1.28.4.2 yamt } 1916 1.28.4.2 yamt if (i == 0) 1917 1.28.4.2 yamt printf("%s: stopping Rx/Tx MACs timed out(0x%08x)!\n", 1918 1.28.4.2 yamt device_xname(sc->sc_dev), reg); 1919 1.28.4.2 yamt 1920 1.28.4.2 yamt /* Reclaim Rx buffers that have been processed. */ 1921 1.28.4.2 yamt if (sc->age_cdata.age_rxhead != NULL) 1922 1.28.4.2 yamt m_freem(sc->age_cdata.age_rxhead); 1923 1.28.4.2 yamt AGE_RXCHAIN_RESET(sc); 1924 1.28.4.2 yamt 1925 1.28.4.2 yamt /* 1926 1.28.4.2 yamt * Free RX and TX mbufs still in the queues. 1927 1.28.4.2 yamt */ 1928 1.28.4.2 yamt for (i = 0; i < AGE_RX_RING_CNT; i++) { 1929 1.28.4.2 yamt rxd = &sc->age_cdata.age_rxdesc[i]; 1930 1.28.4.2 yamt if (rxd->rx_m != NULL) { 1931 1.28.4.2 yamt bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1932 1.28.4.2 yamt m_freem(rxd->rx_m); 1933 1.28.4.2 yamt rxd->rx_m = NULL; 1934 1.28.4.2 yamt } 1935 1.28.4.2 yamt } 1936 1.28.4.2 yamt for (i = 0; i < AGE_TX_RING_CNT; i++) { 1937 1.28.4.2 yamt txd = &sc->age_cdata.age_txdesc[i]; 1938 1.28.4.2 yamt if (txd->tx_m != NULL) { 1939 1.28.4.2 yamt bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1940 1.28.4.2 yamt m_freem(txd->tx_m); 1941 1.28.4.2 yamt txd->tx_m = NULL; 1942 1.28.4.2 yamt } 1943 1.28.4.2 yamt } 1944 1.28.4.2 yamt } 1945 1.28.4.2 yamt 1946 1.28.4.2 yamt static void 1947 1.28.4.2 yamt age_stats_update(struct age_softc *sc) 1948 1.28.4.2 yamt { 1949 1.28.4.2 yamt struct ifnet *ifp = &sc->sc_ec.ec_if; 1950 1.28.4.2 yamt struct age_stats *stat; 1951 1.28.4.2 yamt struct smb *smb; 1952 1.28.4.2 yamt 1953 1.28.4.2 yamt stat = &sc->age_stat; 1954 1.28.4.2 yamt 1955 1.28.4.2 yamt bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 1956 1.28.4.2 yamt sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1957 1.28.4.2 yamt 1958 1.28.4.2 yamt smb = sc->age_rdata.age_smb_block; 1959 1.28.4.2 yamt if (smb->updated == 0) 1960 1.28.4.2 yamt return; 1961 1.28.4.2 yamt 1962 1.28.4.2 yamt /* Rx stats. */ 1963 1.28.4.2 yamt stat->rx_frames += smb->rx_frames; 1964 1.28.4.2 yamt stat->rx_bcast_frames += smb->rx_bcast_frames; 1965 1.28.4.2 yamt stat->rx_mcast_frames += smb->rx_mcast_frames; 1966 1.28.4.2 yamt stat->rx_pause_frames += smb->rx_pause_frames; 1967 1.28.4.2 yamt stat->rx_control_frames += smb->rx_control_frames; 1968 1.28.4.2 yamt stat->rx_crcerrs += smb->rx_crcerrs; 1969 1.28.4.2 yamt stat->rx_lenerrs += smb->rx_lenerrs; 1970 1.28.4.2 yamt stat->rx_bytes += smb->rx_bytes; 1971 1.28.4.2 yamt stat->rx_runts += smb->rx_runts; 1972 1.28.4.2 yamt stat->rx_fragments += smb->rx_fragments; 1973 1.28.4.2 yamt stat->rx_pkts_64 += smb->rx_pkts_64; 1974 1.28.4.2 yamt stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1975 1.28.4.2 yamt stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1976 1.28.4.2 yamt stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1977 1.28.4.2 yamt stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1978 1.28.4.2 yamt stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1979 1.28.4.2 yamt stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1980 1.28.4.2 yamt stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1981 1.28.4.2 yamt stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1982 1.28.4.2 yamt stat->rx_desc_oflows += smb->rx_desc_oflows; 1983 1.28.4.2 yamt stat->rx_alignerrs += smb->rx_alignerrs; 1984 1.28.4.2 yamt stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1985 1.28.4.2 yamt stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1986 1.28.4.2 yamt stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1987 1.28.4.2 yamt 1988 1.28.4.2 yamt /* Tx stats. */ 1989 1.28.4.2 yamt stat->tx_frames += smb->tx_frames; 1990 1.28.4.2 yamt stat->tx_bcast_frames += smb->tx_bcast_frames; 1991 1.28.4.2 yamt stat->tx_mcast_frames += smb->tx_mcast_frames; 1992 1.28.4.2 yamt stat->tx_pause_frames += smb->tx_pause_frames; 1993 1.28.4.2 yamt stat->tx_excess_defer += smb->tx_excess_defer; 1994 1.28.4.2 yamt stat->tx_control_frames += smb->tx_control_frames; 1995 1.28.4.2 yamt stat->tx_deferred += smb->tx_deferred; 1996 1.28.4.2 yamt stat->tx_bytes += smb->tx_bytes; 1997 1.28.4.2 yamt stat->tx_pkts_64 += smb->tx_pkts_64; 1998 1.28.4.2 yamt stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1999 1.28.4.2 yamt stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2000 1.28.4.2 yamt stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2001 1.28.4.2 yamt stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2002 1.28.4.2 yamt stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2003 1.28.4.2 yamt stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2004 1.28.4.2 yamt stat->tx_single_colls += smb->tx_single_colls; 2005 1.28.4.2 yamt stat->tx_multi_colls += smb->tx_multi_colls; 2006 1.28.4.2 yamt stat->tx_late_colls += smb->tx_late_colls; 2007 1.28.4.2 yamt stat->tx_excess_colls += smb->tx_excess_colls; 2008 1.28.4.2 yamt stat->tx_underrun += smb->tx_underrun; 2009 1.28.4.2 yamt stat->tx_desc_underrun += smb->tx_desc_underrun; 2010 1.28.4.2 yamt stat->tx_lenerrs += smb->tx_lenerrs; 2011 1.28.4.2 yamt stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2012 1.28.4.2 yamt stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2013 1.28.4.2 yamt stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2014 1.28.4.2 yamt 2015 1.28.4.2 yamt /* Update counters in ifnet. */ 2016 1.28.4.2 yamt ifp->if_opackets += smb->tx_frames; 2017 1.28.4.2 yamt 2018 1.28.4.2 yamt ifp->if_collisions += smb->tx_single_colls + 2019 1.28.4.2 yamt smb->tx_multi_colls + smb->tx_late_colls + 2020 1.28.4.2 yamt smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 2021 1.28.4.2 yamt 2022 1.28.4.2 yamt ifp->if_oerrors += smb->tx_excess_colls + 2023 1.28.4.2 yamt smb->tx_late_colls + smb->tx_underrun + 2024 1.28.4.2 yamt smb->tx_pkts_truncated; 2025 1.28.4.2 yamt 2026 1.28.4.2 yamt ifp->if_ipackets += smb->rx_frames; 2027 1.28.4.2 yamt 2028 1.28.4.2 yamt ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2029 1.28.4.2 yamt smb->rx_runts + smb->rx_pkts_truncated + 2030 1.28.4.2 yamt smb->rx_fifo_oflows + smb->rx_desc_oflows + 2031 1.28.4.2 yamt smb->rx_alignerrs; 2032 1.28.4.2 yamt 2033 1.28.4.2 yamt /* Update done, clear. */ 2034 1.28.4.2 yamt smb->updated = 0; 2035 1.28.4.2 yamt 2036 1.28.4.2 yamt bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2037 1.28.4.2 yamt sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2038 1.28.4.2 yamt } 2039 1.28.4.2 yamt 2040 1.28.4.2 yamt static void 2041 1.28.4.2 yamt age_stop_txmac(struct age_softc *sc) 2042 1.28.4.2 yamt { 2043 1.28.4.2 yamt uint32_t reg; 2044 1.28.4.2 yamt int i; 2045 1.28.4.2 yamt 2046 1.28.4.2 yamt reg = CSR_READ_4(sc, AGE_MAC_CFG); 2047 1.28.4.2 yamt if ((reg & MAC_CFG_TX_ENB) != 0) { 2048 1.28.4.2 yamt reg &= ~MAC_CFG_TX_ENB; 2049 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2050 1.28.4.2 yamt } 2051 1.28.4.2 yamt /* Stop Tx DMA engine. */ 2052 1.28.4.2 yamt reg = CSR_READ_4(sc, AGE_DMA_CFG); 2053 1.28.4.2 yamt if ((reg & DMA_CFG_RD_ENB) != 0) { 2054 1.28.4.2 yamt reg &= ~DMA_CFG_RD_ENB; 2055 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2056 1.28.4.2 yamt } 2057 1.28.4.2 yamt for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2058 1.28.4.2 yamt if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2059 1.28.4.2 yamt (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2060 1.28.4.2 yamt break; 2061 1.28.4.2 yamt DELAY(10); 2062 1.28.4.2 yamt } 2063 1.28.4.2 yamt if (i == 0) 2064 1.28.4.2 yamt printf("%s: stopping TxMAC timeout!\n", device_xname(sc->sc_dev)); 2065 1.28.4.2 yamt } 2066 1.28.4.2 yamt 2067 1.28.4.2 yamt static void 2068 1.28.4.2 yamt age_stop_rxmac(struct age_softc *sc) 2069 1.28.4.2 yamt { 2070 1.28.4.2 yamt uint32_t reg; 2071 1.28.4.2 yamt int i; 2072 1.28.4.2 yamt 2073 1.28.4.2 yamt reg = CSR_READ_4(sc, AGE_MAC_CFG); 2074 1.28.4.2 yamt if ((reg & MAC_CFG_RX_ENB) != 0) { 2075 1.28.4.2 yamt reg &= ~MAC_CFG_RX_ENB; 2076 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2077 1.28.4.2 yamt } 2078 1.28.4.2 yamt /* Stop Rx DMA engine. */ 2079 1.28.4.2 yamt reg = CSR_READ_4(sc, AGE_DMA_CFG); 2080 1.28.4.2 yamt if ((reg & DMA_CFG_WR_ENB) != 0) { 2081 1.28.4.2 yamt reg &= ~DMA_CFG_WR_ENB; 2082 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2083 1.28.4.2 yamt } 2084 1.28.4.2 yamt for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2085 1.28.4.2 yamt if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2086 1.28.4.2 yamt (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2087 1.28.4.2 yamt break; 2088 1.28.4.2 yamt DELAY(10); 2089 1.28.4.2 yamt } 2090 1.28.4.2 yamt if (i == 0) 2091 1.28.4.2 yamt printf("%s: stopping RxMAC timeout!\n", device_xname(sc->sc_dev)); 2092 1.28.4.2 yamt } 2093 1.28.4.2 yamt 2094 1.28.4.2 yamt static void 2095 1.28.4.2 yamt age_init_tx_ring(struct age_softc *sc) 2096 1.28.4.2 yamt { 2097 1.28.4.2 yamt struct age_ring_data *rd; 2098 1.28.4.2 yamt struct age_txdesc *txd; 2099 1.28.4.2 yamt int i; 2100 1.28.4.2 yamt 2101 1.28.4.2 yamt sc->age_cdata.age_tx_prod = 0; 2102 1.28.4.2 yamt sc->age_cdata.age_tx_cons = 0; 2103 1.28.4.2 yamt sc->age_cdata.age_tx_cnt = 0; 2104 1.28.4.2 yamt 2105 1.28.4.2 yamt rd = &sc->age_rdata; 2106 1.28.4.2 yamt memset(rd->age_tx_ring, 0, AGE_TX_RING_SZ); 2107 1.28.4.2 yamt for (i = 0; i < AGE_TX_RING_CNT; i++) { 2108 1.28.4.2 yamt txd = &sc->age_cdata.age_txdesc[i]; 2109 1.28.4.2 yamt txd->tx_desc = &rd->age_tx_ring[i]; 2110 1.28.4.2 yamt txd->tx_m = NULL; 2111 1.28.4.2 yamt } 2112 1.28.4.2 yamt bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 2113 1.28.4.2 yamt sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2114 1.28.4.2 yamt } 2115 1.28.4.2 yamt 2116 1.28.4.2 yamt static int 2117 1.28.4.2 yamt age_init_rx_ring(struct age_softc *sc) 2118 1.28.4.2 yamt { 2119 1.28.4.2 yamt struct age_ring_data *rd; 2120 1.28.4.2 yamt struct age_rxdesc *rxd; 2121 1.28.4.2 yamt int i; 2122 1.28.4.2 yamt 2123 1.28.4.2 yamt sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 2124 1.28.4.2 yamt rd = &sc->age_rdata; 2125 1.28.4.2 yamt memset(rd->age_rx_ring, 0, AGE_RX_RING_SZ); 2126 1.28.4.2 yamt for (i = 0; i < AGE_RX_RING_CNT; i++) { 2127 1.28.4.2 yamt rxd = &sc->age_cdata.age_rxdesc[i]; 2128 1.28.4.2 yamt rxd->rx_m = NULL; 2129 1.28.4.2 yamt rxd->rx_desc = &rd->age_rx_ring[i]; 2130 1.28.4.2 yamt if (age_newbuf(sc, rxd, 1) != 0) 2131 1.28.4.2 yamt return ENOBUFS; 2132 1.28.4.2 yamt } 2133 1.28.4.2 yamt 2134 1.28.4.2 yamt bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 0, 2135 1.28.4.2 yamt sc->age_cdata.age_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2136 1.28.4.2 yamt 2137 1.28.4.2 yamt return 0; 2138 1.28.4.2 yamt } 2139 1.28.4.2 yamt 2140 1.28.4.2 yamt static void 2141 1.28.4.2 yamt age_init_rr_ring(struct age_softc *sc) 2142 1.28.4.2 yamt { 2143 1.28.4.2 yamt struct age_ring_data *rd; 2144 1.28.4.2 yamt 2145 1.28.4.2 yamt sc->age_cdata.age_rr_cons = 0; 2146 1.28.4.2 yamt AGE_RXCHAIN_RESET(sc); 2147 1.28.4.2 yamt 2148 1.28.4.2 yamt rd = &sc->age_rdata; 2149 1.28.4.2 yamt memset(rd->age_rr_ring, 0, AGE_RR_RING_SZ); 2150 1.28.4.2 yamt bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 2151 1.28.4.2 yamt sc->age_cdata.age_rr_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2152 1.28.4.2 yamt } 2153 1.28.4.2 yamt 2154 1.28.4.2 yamt static void 2155 1.28.4.2 yamt age_init_cmb_block(struct age_softc *sc) 2156 1.28.4.2 yamt { 2157 1.28.4.2 yamt struct age_ring_data *rd; 2158 1.28.4.2 yamt 2159 1.28.4.2 yamt rd = &sc->age_rdata; 2160 1.28.4.2 yamt memset(rd->age_cmb_block, 0, AGE_CMB_BLOCK_SZ); 2161 1.28.4.2 yamt bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 2162 1.28.4.2 yamt sc->age_cdata.age_cmb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2163 1.28.4.2 yamt } 2164 1.28.4.2 yamt 2165 1.28.4.2 yamt static void 2166 1.28.4.2 yamt age_init_smb_block(struct age_softc *sc) 2167 1.28.4.2 yamt { 2168 1.28.4.2 yamt struct age_ring_data *rd; 2169 1.28.4.2 yamt 2170 1.28.4.2 yamt rd = &sc->age_rdata; 2171 1.28.4.2 yamt memset(rd->age_smb_block, 0, AGE_SMB_BLOCK_SZ); 2172 1.28.4.2 yamt bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2173 1.28.4.2 yamt sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2174 1.28.4.2 yamt } 2175 1.28.4.2 yamt 2176 1.28.4.2 yamt static int 2177 1.28.4.2 yamt age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd, int init) 2178 1.28.4.2 yamt { 2179 1.28.4.2 yamt struct rx_desc *desc; 2180 1.28.4.2 yamt struct mbuf *m; 2181 1.28.4.2 yamt bus_dmamap_t map; 2182 1.28.4.2 yamt int error; 2183 1.28.4.2 yamt 2184 1.28.4.2 yamt MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 2185 1.28.4.2 yamt if (m == NULL) 2186 1.28.4.2 yamt return ENOBUFS; 2187 1.28.4.2 yamt MCLGET(m, init ? M_WAITOK : M_DONTWAIT); 2188 1.28.4.2 yamt if (!(m->m_flags & M_EXT)) { 2189 1.28.4.2 yamt m_freem(m); 2190 1.28.4.2 yamt return ENOBUFS; 2191 1.28.4.2 yamt } 2192 1.28.4.2 yamt 2193 1.28.4.2 yamt m->m_len = m->m_pkthdr.len = MCLBYTES; 2194 1.28.4.2 yamt m_adj(m, ETHER_ALIGN); 2195 1.28.4.2 yamt 2196 1.28.4.2 yamt error = bus_dmamap_load_mbuf(sc->sc_dmat, 2197 1.28.4.2 yamt sc->age_cdata.age_rx_sparemap, m, BUS_DMA_NOWAIT); 2198 1.28.4.2 yamt 2199 1.28.4.2 yamt if (error != 0) { 2200 1.28.4.2 yamt if (!error) { 2201 1.28.4.2 yamt bus_dmamap_unload(sc->sc_dmat, 2202 1.28.4.2 yamt sc->age_cdata.age_rx_sparemap); 2203 1.28.4.2 yamt error = EFBIG; 2204 1.28.4.2 yamt printf("%s: too many segments?!\n", 2205 1.28.4.2 yamt device_xname(sc->sc_dev)); 2206 1.28.4.2 yamt } 2207 1.28.4.2 yamt m_freem(m); 2208 1.28.4.2 yamt 2209 1.28.4.2 yamt if (init) 2210 1.28.4.2 yamt printf("%s: can't load RX mbuf\n", device_xname(sc->sc_dev)); 2211 1.28.4.2 yamt return error; 2212 1.28.4.2 yamt } 2213 1.28.4.2 yamt 2214 1.28.4.2 yamt if (rxd->rx_m != NULL) { 2215 1.28.4.2 yamt bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2216 1.28.4.2 yamt rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2217 1.28.4.2 yamt bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2218 1.28.4.2 yamt } 2219 1.28.4.2 yamt map = rxd->rx_dmamap; 2220 1.28.4.2 yamt rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 2221 1.28.4.2 yamt sc->age_cdata.age_rx_sparemap = map; 2222 1.28.4.2 yamt rxd->rx_m = m; 2223 1.28.4.2 yamt 2224 1.28.4.2 yamt desc = rxd->rx_desc; 2225 1.28.4.2 yamt desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 2226 1.28.4.2 yamt desc->len = 2227 1.28.4.2 yamt htole32((rxd->rx_dmamap->dm_segs[0].ds_len & AGE_RD_LEN_MASK) << 2228 1.28.4.2 yamt AGE_RD_LEN_SHIFT); 2229 1.28.4.2 yamt 2230 1.28.4.2 yamt return 0; 2231 1.28.4.2 yamt } 2232 1.28.4.2 yamt 2233 1.28.4.2 yamt static void 2234 1.28.4.2 yamt age_rxvlan(struct age_softc *sc) 2235 1.28.4.2 yamt { 2236 1.28.4.2 yamt uint32_t reg; 2237 1.28.4.2 yamt 2238 1.28.4.2 yamt reg = CSR_READ_4(sc, AGE_MAC_CFG); 2239 1.28.4.2 yamt reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2240 1.28.4.2 yamt if (sc->sc_ec.ec_capabilities & ETHERCAP_VLAN_HWTAGGING) 2241 1.28.4.2 yamt reg |= MAC_CFG_VLAN_TAG_STRIP; 2242 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2243 1.28.4.2 yamt } 2244 1.28.4.2 yamt 2245 1.28.4.2 yamt static void 2246 1.28.4.2 yamt age_rxfilter(struct age_softc *sc) 2247 1.28.4.2 yamt { 2248 1.28.4.2 yamt struct ethercom *ec = &sc->sc_ec; 2249 1.28.4.2 yamt struct ifnet *ifp = &sc->sc_ec.ec_if; 2250 1.28.4.2 yamt struct ether_multi *enm; 2251 1.28.4.2 yamt struct ether_multistep step; 2252 1.28.4.2 yamt uint32_t crc; 2253 1.28.4.2 yamt uint32_t mchash[2]; 2254 1.28.4.2 yamt uint32_t rxcfg; 2255 1.28.4.2 yamt 2256 1.28.4.2 yamt rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 2257 1.28.4.2 yamt rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2258 1.28.4.2 yamt ifp->if_flags &= ~IFF_ALLMULTI; 2259 1.28.4.2 yamt 2260 1.28.4.2 yamt /* 2261 1.28.4.2 yamt * Always accept broadcast frames. 2262 1.28.4.2 yamt */ 2263 1.28.4.2 yamt rxcfg |= MAC_CFG_BCAST; 2264 1.28.4.2 yamt 2265 1.28.4.2 yamt if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 2266 1.28.4.2 yamt ifp->if_flags |= IFF_ALLMULTI; 2267 1.28.4.2 yamt if (ifp->if_flags & IFF_PROMISC) 2268 1.28.4.2 yamt rxcfg |= MAC_CFG_PROMISC; 2269 1.28.4.2 yamt else 2270 1.28.4.2 yamt rxcfg |= MAC_CFG_ALLMULTI; 2271 1.28.4.2 yamt mchash[0] = mchash[1] = 0xFFFFFFFF; 2272 1.28.4.2 yamt } else { 2273 1.28.4.2 yamt /* Program new filter. */ 2274 1.28.4.2 yamt memset(mchash, 0, sizeof(mchash)); 2275 1.28.4.2 yamt 2276 1.28.4.2 yamt ETHER_FIRST_MULTI(step, ec, enm); 2277 1.28.4.2 yamt while (enm != NULL) { 2278 1.28.4.2 yamt crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2279 1.28.4.2 yamt mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2280 1.28.4.2 yamt ETHER_NEXT_MULTI(step, enm); 2281 1.28.4.2 yamt } 2282 1.28.4.2 yamt } 2283 1.28.4.2 yamt 2284 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 2285 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 2286 1.28.4.2 yamt CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 2287 1.28.4.2 yamt } 2288
Indexes created Fri Oct 03 02:09:57 GMT 2025