if_age.c revision 1.10
1 /* $NetBSD: if_age.c,v 1.10 2009/01/22 09:37:44 cegger Exp $ */ 2 /* $OpenBSD: if_age.c,v 1.1 2009/01/16 05:00:34 kevlo Exp $ */ 3 4 /*- 5 * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: if_age.c,v 1.10 2009/01/22 09:37:44 cegger Exp $"); 35 36 #include "bpfilter.h" 37 #include "vlan.h" 38 39 #include <sys/param.h> 40 #include <sys/proc.h> 41 #include <sys/endian.h> 42 #include <sys/systm.h> 43 #include <sys/types.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/queue.h> 47 #include <sys/kernel.h> 48 #include <sys/device.h> 49 #include <sys/callout.h> 50 #include <sys/socket.h> 51 52 #include <net/if.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #ifdef INET 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/in_var.h> 61 #include <netinet/ip.h> 62 #endif 63 64 #include <net/if_types.h> 65 #include <net/if_vlanvar.h> 66 67 #if NBPFILTER > 0 68 #include <net/bpf.h> 69 #endif 70 71 #include <sys/rnd.h> 72 73 #include <dev/mii/mii.h> 74 #include <dev/mii/miivar.h> 75 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/pcidevs.h> 79 80 #include <dev/pci/if_agereg.h> 81 82 static int age_match(device_t, cfdata_t, void *); 83 static void age_attach(device_t, device_t, void *); 84 static int age_detach(device_t, int); 85 86 static bool age_resume(device_t PMF_FN_PROTO); 87 88 static int age_miibus_readreg(device_t, int, int); 89 static void age_miibus_writereg(device_t, int, int, int); 90 static void age_miibus_statchg(device_t); 91 92 static int age_init(struct ifnet *); 93 static int age_ioctl(struct ifnet *, u_long, void *); 94 static void age_start(struct ifnet *); 95 static void age_watchdog(struct ifnet *); 96 static void age_mediastatus(struct ifnet *, struct ifmediareq *); 97 static int age_mediachange(struct ifnet *); 98 99 static int age_intr(void *); 100 static int age_read_vpd_word(struct age_softc *, uint32_t, uint32_t, uint32_t *); 101 static int age_dma_alloc(struct age_softc *); 102 static void age_dma_free(struct age_softc *); 103 static void age_get_macaddr(struct age_softc *, uint8_t[]); 104 static void age_phy_reset(struct age_softc *); 105 106 static int age_encap(struct age_softc *, struct mbuf **); 107 static void age_init_tx_ring(struct age_softc *); 108 static int age_init_rx_ring(struct age_softc *); 109 static void age_init_rr_ring(struct age_softc *); 110 static void age_init_cmb_block(struct age_softc *); 111 static void age_init_smb_block(struct age_softc *); 112 static int age_newbuf(struct age_softc *, struct age_rxdesc *, int); 113 static void age_mac_config(struct age_softc *); 114 static void age_txintr(struct age_softc *, int); 115 static void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 116 static void age_rxintr(struct age_softc *, int); 117 static void age_tick(void *); 118 static void age_reset(struct age_softc *); 119 static void age_stop(struct age_softc *); 120 static void age_stats_update(struct age_softc *); 121 static void age_stop_txmac(struct age_softc *); 122 static void age_stop_rxmac(struct age_softc *); 123 static void age_rxvlan(struct age_softc *sc); 124 static void age_rxfilter(struct age_softc *); 125 126 CFATTACH_DECL_NEW(age, sizeof(struct age_softc), 127 age_match, age_attach, age_detach, NULL); 128 129 int agedebug = 0; 130 #define DPRINTF(x) do { if (agedebug) printf x; } while (0) 131 132 #define ETHER_ALIGN 2 133 #define AGE_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 134 135 static int 136 age_match(device_t dev, cfdata_t match, void *aux) 137 { 138 struct pci_attach_args *pa = aux; 139 140 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && 141 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_GIGA); 142 } 143 144 static void 145 age_attach(device_t parent, device_t self, void *aux) 146 { 147 struct age_softc *sc = device_private(self); 148 struct pci_attach_args *pa = aux; 149 pci_intr_handle_t ih; 150 const char *intrstr; 151 struct ifnet *ifp = &sc->sc_ec.ec_if; 152 pcireg_t memtype; 153 int error = 0; 154 155 aprint_naive("\n"); 156 aprint_normal(": Attansic/Atheros L1 Gigabit Ethernet\n"); 157 158 sc->sc_dev = self; 159 sc->sc_dmat = pa->pa_dmat; 160 sc->sc_pct = pa->pa_pc; 161 sc->sc_pcitag = pa->pa_tag; 162 163 /* 164 * Allocate IO memory 165 */ 166 memtype = pci_mapreg_type(sc->sc_pct, sc->sc_pcitag, AGE_PCIR_BAR); 167 switch (memtype) { 168 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 169 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 170 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 171 break; 172 default: 173 aprint_error_dev(self, "invalid base address register\n"); 174 break; 175 } 176 177 if (pci_mapreg_map(pa, AGE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 178 &sc->sc_mem_bh, NULL, &sc->sc_mem_size) != 0) { 179 aprint_error_dev(self, "could not map mem space\n"); 180 return; 181 } 182 183 if (pci_intr_map(pa, &ih) != 0) { 184 aprint_error_dev(self, "could not map interrupt\n"); 185 return; 186 } 187 188 /* 189 * Allocate IRQ 190 */ 191 intrstr = pci_intr_string(sc->sc_pct, ih); 192 sc->sc_irq_handle = pci_intr_establish(sc->sc_pct, ih, IPL_NET, 193 age_intr, sc); 194 if (sc->sc_irq_handle == NULL) { 195 aprint_error_dev(self, "could not establish interrupt"); 196 if (intrstr != NULL) 197 aprint_error(" at %s", intrstr); 198 aprint_error("\n"); 199 return; 200 } 201 aprint_normal_dev(self, "%s\n", intrstr); 202 203 /* Set PHY address. */ 204 sc->age_phyaddr = AGE_PHY_ADDR; 205 206 /* Reset PHY. */ 207 age_phy_reset(sc); 208 209 /* Reset the ethernet controller. */ 210 age_reset(sc); 211 212 /* Get PCI and chip id/revision. */ 213 sc->age_rev = PCI_REVISION(pa->pa_class); 214 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 215 MASTER_CHIP_REV_SHIFT; 216 217 aprint_debug_dev(self, "PCI device revision : 0x%04x\n", sc->age_rev); 218 aprint_debug_dev(self, "Chip id/revision : 0x%04x\n", sc->age_chip_rev); 219 220 if (agedebug) { 221 aprint_debug_dev(self, "%d Tx FIFO, %d Rx FIFO\n", 222 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 223 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 224 } 225 226 /* Set max allowable DMA size. */ 227 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 228 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 229 230 /* Allocate DMA stuffs */ 231 error = age_dma_alloc(sc); 232 if (error) 233 goto fail; 234 235 callout_init(&sc->sc_tick_ch, 0); 236 callout_setfunc(&sc->sc_tick_ch, age_tick, sc); 237 238 /* Load station address. */ 239 age_get_macaddr(sc, sc->sc_enaddr); 240 241 aprint_normal_dev(self, "Ethernet address %s\n", 242 ether_sprintf(sc->sc_enaddr)); 243 244 ifp->if_softc = sc; 245 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 246 ifp->if_init = age_init; 247 ifp->if_ioctl = age_ioctl; 248 ifp->if_start = age_start; 249 ifp->if_watchdog = age_watchdog; 250 ifp->if_baudrate = IF_Gbps(1); 251 IFQ_SET_MAXLEN(&ifp->if_snd, AGE_TX_RING_CNT - 1); 252 IFQ_SET_READY(&ifp->if_snd); 253 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 254 255 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 256 257 #ifdef AGE_CHECKSUM 258 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 259 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 260 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 261 #endif 262 263 #if NVLAN > 0 264 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 265 #endif 266 267 /* Set up MII bus. */ 268 sc->sc_miibus.mii_ifp = ifp; 269 sc->sc_miibus.mii_readreg = age_miibus_readreg; 270 sc->sc_miibus.mii_writereg = age_miibus_writereg; 271 sc->sc_miibus.mii_statchg = age_miibus_statchg; 272 273 ifmedia_init(&sc->sc_miibus.mii_media, 0, age_mediachange, 274 age_mediastatus); 275 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 276 MII_OFFSET_ANY, 0); 277 278 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 279 aprint_error_dev(self, "no PHY found!\n"); 280 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 281 0, NULL); 282 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 283 } else 284 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 285 286 if_attach(ifp); 287 ether_ifattach(ifp, sc->sc_enaddr); 288 289 if (!pmf_device_register(self, NULL, age_resume)) 290 aprint_error_dev(self, "couldn't establish power handler\n"); 291 else 292 pmf_class_network_register(self, ifp); 293 294 return; 295 fail: 296 age_detach(sc->sc_dev, 0); 297 } 298 299 static int 300 age_detach(device_t self, int flags) 301 { 302 struct age_softc *sc = device_private(self); 303 struct ifnet *ifp = &sc->sc_ec.ec_if; 304 int s; 305 306 s = splnet(); 307 age_stop(sc); 308 splx(s); 309 310 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 311 312 /* Delete all remaining media. */ 313 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 314 315 ether_ifdetach(ifp); 316 if_detach(ifp); 317 age_dma_free(sc); 318 319 if (sc->sc_irq_handle != NULL) { 320 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 321 sc->sc_irq_handle = NULL; 322 } 323 324 return (0); 325 } 326 327 /* 328 * Read a PHY register on the MII of the L1. 329 */ 330 static int 331 age_miibus_readreg(struct device *dev, int phy, int reg) 332 { 333 struct age_softc *sc = device_private(dev); 334 uint32_t v; 335 int i; 336 337 if (phy != sc->age_phyaddr) 338 return (0); 339 340 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 341 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 342 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 343 DELAY(1); 344 v = CSR_READ_4(sc, AGE_MDIO); 345 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 346 break; 347 } 348 349 if (i == 0) { 350 printf("%s: phy read timeout: phy %d, reg %d\n", 351 device_xname(sc->sc_dev), phy, reg); 352 return (0); 353 } 354 355 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 356 } 357 358 /* 359 * Write a PHY register on the MII of the L1. 360 */ 361 static void 362 age_miibus_writereg(struct device *dev, int phy, int reg, int val) 363 { 364 struct age_softc *sc = device_private(dev); 365 uint32_t v; 366 int i; 367 368 if (phy != sc->age_phyaddr) 369 return; 370 371 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 372 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 373 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 374 375 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 376 DELAY(1); 377 v = CSR_READ_4(sc, AGE_MDIO); 378 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 379 break; 380 } 381 382 if (i == 0) { 383 printf("%s: phy write timeout: phy %d, reg %d\n", 384 device_xname(sc->sc_dev), phy, reg); 385 } 386 } 387 388 /* 389 * Callback from MII layer when media changes. 390 */ 391 static void 392 age_miibus_statchg(device_t dev) 393 { 394 struct age_softc *sc = device_private(dev); 395 struct ifnet *ifp = &sc->sc_ec.ec_if; 396 struct mii_data *mii; 397 398 if ((ifp->if_flags & IFF_RUNNING) == 0) 399 return; 400 401 mii = &sc->sc_miibus; 402 403 sc->age_flags &= ~AGE_FLAG_LINK; 404 if ((mii->mii_media_status & IFM_AVALID) != 0) { 405 switch (IFM_SUBTYPE(mii->mii_media_active)) { 406 case IFM_10_T: 407 case IFM_100_TX: 408 case IFM_1000_T: 409 sc->age_flags |= AGE_FLAG_LINK; 410 break; 411 default: 412 break; 413 } 414 } 415 416 /* Stop Rx/Tx MACs. */ 417 age_stop_rxmac(sc); 418 age_stop_txmac(sc); 419 420 /* Program MACs with resolved speed/duplex/flow-control. */ 421 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 422 uint32_t reg; 423 424 age_mac_config(sc); 425 reg = CSR_READ_4(sc, AGE_MAC_CFG); 426 /* Restart DMA engine and Tx/Rx MAC. */ 427 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 428 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 429 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 430 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 431 } 432 } 433 434 /* 435 * Get the current interface media status. 436 */ 437 static void 438 age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 439 { 440 struct age_softc *sc = ifp->if_softc; 441 struct mii_data *mii = &sc->sc_miibus; 442 443 mii_pollstat(mii); 444 ifmr->ifm_status = mii->mii_media_status; 445 ifmr->ifm_active = mii->mii_media_active; 446 } 447 448 /* 449 * Set hardware to newly-selected media. 450 */ 451 static int 452 age_mediachange(struct ifnet *ifp) 453 { 454 struct age_softc *sc = ifp->if_softc; 455 struct mii_data *mii = &sc->sc_miibus; 456 int error; 457 458 if (mii->mii_instance != 0) { 459 struct mii_softc *miisc; 460 461 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 462 mii_phy_reset(miisc); 463 } 464 error = mii_mediachg(mii); 465 466 return (error); 467 } 468 469 static int 470 age_intr(void *arg) 471 { 472 struct age_softc *sc = arg; 473 struct ifnet *ifp = &sc->sc_ec.ec_if; 474 struct cmb *cmb; 475 uint32_t status; 476 477 status = CSR_READ_4(sc, AGE_INTR_STATUS); 478 if (status == 0 || (status & AGE_INTRS) == 0) 479 return 0; 480 481 cmb = sc->age_rdata.age_cmb_block; 482 if (cmb == NULL) 483 return 0; 484 485 /* Disable interrupts. */ 486 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 487 488 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 489 sc->age_cdata.age_cmb_block_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 490 status = le32toh(cmb->intr_status); 491 if ((status & AGE_INTRS) == 0) 492 goto back; 493 494 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 495 TPD_CONS_SHIFT; 496 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 497 RRD_PROD_SHIFT; 498 499 /* Let hardware know CMB was served. */ 500 cmb->intr_status = 0; 501 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 502 sc->age_cdata.age_cmb_block_map->dm_mapsize, 503 BUS_DMASYNC_PREWRITE); 504 505 if (ifp->if_flags & IFF_RUNNING) { 506 if (status & INTR_CMB_RX) 507 age_rxintr(sc, sc->age_rr_prod); 508 509 if (status & INTR_CMB_TX) 510 age_txintr(sc, sc->age_tpd_cons); 511 512 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 513 if (status & INTR_DMA_RD_TO_RST) 514 printf("%s: DMA read error! -- resetting\n", 515 device_xname(sc->sc_dev)); 516 if (status & INTR_DMA_WR_TO_RST) 517 printf("%s: DMA write error! -- resetting\n", 518 device_xname(sc->sc_dev)); 519 age_init(ifp); 520 } 521 522 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 523 age_start(ifp); 524 525 if (status & INTR_SMB) 526 age_stats_update(sc); 527 } 528 529 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 530 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 531 sc->age_cdata.age_cmb_block_map->dm_mapsize, 532 BUS_DMASYNC_POSTREAD); 533 534 back: 535 /* Re-enable interrupts. */ 536 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 537 538 return (1); 539 } 540 541 static int 542 age_read_vpd_word(struct age_softc *sc, uint32_t vpdc, uint32_t offset, 543 uint32_t *word) 544 { 545 int i; 546 pcireg_t rv; 547 548 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_VPD_ADDRESS(vpdc), 549 offset << PCI_VPD_ADDRESS_SHIFT); 550 for (i = AGE_TIMEOUT; i > 0; i--) { 551 DELAY(10); 552 rv = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 553 PCI_VPD_ADDRESS(vpdc)); 554 if ((rv & PCI_VPD_OPFLAG) == PCI_VPD_OPFLAG) 555 break; 556 } 557 if (i == 0) { 558 printf("%s: VPD read timeout!\n", device_xname(sc->sc_dev)); 559 *word = 0; 560 return ETIMEDOUT; 561 } 562 563 *word = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_VPD_DATAREG(vpdc)); 564 return 0; 565 } 566 567 static void 568 age_get_macaddr(struct age_softc *sc, uint8_t eaddr[]) 569 { 570 uint32_t ea[2], off, reg, word; 571 int vpd_error, match, vpdc; 572 573 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 574 if ((reg & SPI_VPD_ENB) != 0) { 575 /* Get VPD stored in TWSI EEPROM. */ 576 reg &= ~SPI_VPD_ENB; 577 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 578 } 579 580 vpd_error = 0; 581 ea[0] = ea[1] = 0; 582 if ((vpd_error = pci_get_capability(sc->sc_pct, sc->sc_pcitag, 583 PCI_CAP_VPD, &vpdc, NULL))) { 584 /* 585 * PCI VPD capability exists, but it seems that it's 586 * not in the standard form as stated in PCI VPD 587 * specification such that driver could not use 588 * pci_get_vpd_readonly(9) with keyword 'NA'. 589 * Search VPD data starting at address 0x0100. The data 590 * should be used as initializers to set AGE_PAR0, 591 * AGE_PAR1 register including other PCI configuration 592 * registers. 593 */ 594 word = 0; 595 match = 0; 596 reg = 0; 597 for (off = AGE_VPD_REG_CONF_START; off < AGE_VPD_REG_CONF_END; 598 off += sizeof(uint32_t)) { 599 vpd_error = age_read_vpd_word(sc, vpdc, off, &word); 600 if (vpd_error != 0) 601 break; 602 if (match != 0) { 603 switch (reg) { 604 case AGE_PAR0: 605 ea[0] = word; 606 break; 607 case AGE_PAR1: 608 ea[1] = word; 609 break; 610 default: 611 break; 612 } 613 match = 0; 614 } else if ((word & 0xFF) == AGE_VPD_REG_CONF_SIG) { 615 match = 1; 616 reg = word >> 16; 617 } else 618 break; 619 } 620 if (off >= AGE_VPD_REG_CONF_END) 621 vpd_error = ENOENT; 622 if (vpd_error == 0) { 623 /* 624 * Don't blindly trust ethernet address obtained 625 * from VPD. Check whether ethernet address is 626 * valid one. Otherwise fall-back to reading 627 * PAR register. 628 */ 629 ea[1] &= 0xFFFF; 630 if ((ea[0] == 0 && ea[1] == 0) || 631 (ea[0] == 0xFFFFFFFF && ea[1] == 0xFFFF)) { 632 if (agedebug) 633 printf("%s: invalid ethernet address " 634 "returned from VPD.\n", 635 device_xname(sc->sc_dev)); 636 vpd_error = EINVAL; 637 } 638 } 639 if (vpd_error != 0 && (agedebug)) 640 printf("%s: VPD access failure!\n", 641 device_xname(sc->sc_dev)); 642 } else { 643 if (agedebug) 644 printf("%s: PCI VPD capability not found!\n", 645 device_xname(sc->sc_dev)); 646 } 647 648 /* 649 * It seems that L1 also provides a way to extract ethernet 650 * address via SPI flash interface. Because SPI flash memory 651 * device of different vendors vary in their instruction 652 * codes for read ID instruction, it's very hard to get 653 * instructions codes without detailed information for the 654 * flash memory device used on ethernet controller. To simplify 655 * code, just read AGE_PAR0/AGE_PAR1 register to get ethernet 656 * address which is supposed to be set by hardware during 657 * power on reset. 658 */ 659 if (vpd_error != 0) { 660 /* 661 * VPD is mapped to SPI flash memory or BIOS set it. 662 */ 663 ea[0] = CSR_READ_4(sc, AGE_PAR0); 664 ea[1] = CSR_READ_4(sc, AGE_PAR1); 665 } 666 667 ea[1] &= 0xFFFF; 668 eaddr[0] = (ea[1] >> 8) & 0xFF; 669 eaddr[1] = (ea[1] >> 0) & 0xFF; 670 eaddr[2] = (ea[0] >> 24) & 0xFF; 671 eaddr[3] = (ea[0] >> 16) & 0xFF; 672 eaddr[4] = (ea[0] >> 8) & 0xFF; 673 eaddr[5] = (ea[0] >> 0) & 0xFF; 674 } 675 676 static void 677 age_phy_reset(struct age_softc *sc) 678 { 679 /* Reset PHY. */ 680 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 681 DELAY(1000); 682 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 683 DELAY(1000); 684 } 685 686 static int 687 age_dma_alloc(struct age_softc *sc) 688 { 689 struct age_txdesc *txd; 690 struct age_rxdesc *rxd; 691 int nsegs, error, i; 692 693 /* 694 * Create DMA stuffs for TX ring 695 */ 696 error = bus_dmamap_create(sc->sc_dmat, AGE_TX_RING_SZ, 1, 697 AGE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_tx_ring_map); 698 if (error) 699 return (ENOBUFS); 700 701 /* Allocate DMA'able memory for TX ring */ 702 error = bus_dmamem_alloc(sc->sc_dmat, AGE_TX_RING_SZ, 703 PAGE_SIZE, 0, &sc->age_rdata.age_tx_ring_seg, 1, 704 &nsegs, BUS_DMA_WAITOK); 705 if (error) { 706 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 707 device_xname(sc->sc_dev)); 708 return error; 709 } 710 711 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_tx_ring_seg, 712 nsegs, AGE_TX_RING_SZ, (void **)&sc->age_rdata.age_tx_ring, 713 BUS_DMA_NOWAIT); 714 if (error) 715 return (ENOBUFS); 716 717 memset(sc->age_rdata.age_tx_ring, 0, AGE_TX_RING_SZ); 718 719 /* Load the DMA map for Tx ring. */ 720 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 721 sc->age_rdata.age_tx_ring, AGE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 722 if (error) { 723 printf("%s: could not load DMA'able memory for Tx ring.\n", 724 device_xname(sc->sc_dev)); 725 bus_dmamem_free(sc->sc_dmat, 726 (bus_dma_segment_t *)&sc->age_rdata.age_tx_ring, 1); 727 return error; 728 } 729 730 sc->age_rdata.age_tx_ring_paddr = 731 sc->age_cdata.age_tx_ring_map->dm_segs[0].ds_addr; 732 733 /* 734 * Create DMA stuffs for RX ring 735 */ 736 error = bus_dmamap_create(sc->sc_dmat, AGE_RX_RING_SZ, 1, 737 AGE_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_ring_map); 738 if (error) 739 return (ENOBUFS); 740 741 /* Allocate DMA'able memory for RX ring */ 742 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RX_RING_SZ, 743 PAGE_SIZE, 0, &sc->age_rdata.age_rx_ring_seg, 1, 744 &nsegs, BUS_DMA_WAITOK); 745 if (error) { 746 printf("%s: could not allocate DMA'able memory for Rx ring.\n", 747 device_xname(sc->sc_dev)); 748 return error; 749 } 750 751 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rx_ring_seg, 752 nsegs, AGE_RX_RING_SZ, (void **)&sc->age_rdata.age_rx_ring, 753 BUS_DMA_NOWAIT); 754 if (error) 755 return (ENOBUFS); 756 757 memset(sc->age_rdata.age_rx_ring, 0, AGE_RX_RING_SZ); 758 759 /* Load the DMA map for Rx ring. */ 760 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 761 sc->age_rdata.age_rx_ring, AGE_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 762 if (error) { 763 printf("%s: could not load DMA'able memory for Rx ring.\n", 764 device_xname(sc->sc_dev)); 765 bus_dmamem_free(sc->sc_dmat, 766 (bus_dma_segment_t *)sc->age_rdata.age_rx_ring, 1); 767 return error; 768 } 769 770 sc->age_rdata.age_rx_ring_paddr = 771 sc->age_cdata.age_rx_ring_map->dm_segs[0].ds_addr; 772 773 /* 774 * Create DMA stuffs for RX return ring 775 */ 776 error = bus_dmamap_create(sc->sc_dmat, AGE_RR_RING_SZ, 1, 777 AGE_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rr_ring_map); 778 if (error) 779 return (ENOBUFS); 780 781 /* Allocate DMA'able memory for RX return ring */ 782 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RR_RING_SZ, 783 PAGE_SIZE, 0, &sc->age_rdata.age_rr_ring_seg, 1, 784 &nsegs, BUS_DMA_WAITOK); 785 if (error) { 786 printf("%s: could not allocate DMA'able memory for Rx " 787 "return ring.\n", device_xname(sc->sc_dev)); 788 return error; 789 } 790 791 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rr_ring_seg, 792 nsegs, AGE_RR_RING_SZ, (void **)&sc->age_rdata.age_rr_ring, 793 BUS_DMA_NOWAIT); 794 if (error) 795 return (ENOBUFS); 796 797 memset(sc->age_rdata.age_rr_ring, 0, AGE_RR_RING_SZ); 798 799 /* Load the DMA map for Rx return ring. */ 800 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 801 sc->age_rdata.age_rr_ring, AGE_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 802 if (error) { 803 printf("%s: could not load DMA'able memory for Rx return ring." 804 "\n", device_xname(sc->sc_dev)); 805 bus_dmamem_free(sc->sc_dmat, 806 (bus_dma_segment_t *)&sc->age_rdata.age_rr_ring, 1); 807 return error; 808 } 809 810 sc->age_rdata.age_rr_ring_paddr = 811 sc->age_cdata.age_rr_ring_map->dm_segs[0].ds_addr; 812 813 /* 814 * Create DMA stuffs for CMB block 815 */ 816 error = bus_dmamap_create(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 1, 817 AGE_CMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 818 &sc->age_cdata.age_cmb_block_map); 819 if (error) 820 return (ENOBUFS); 821 822 /* Allocate DMA'able memory for CMB block */ 823 error = bus_dmamem_alloc(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 824 PAGE_SIZE, 0, &sc->age_rdata.age_cmb_block_seg, 1, 825 &nsegs, BUS_DMA_WAITOK); 826 if (error) { 827 printf("%s: could not allocate DMA'able memory for " 828 "CMB block\n", device_xname(sc->sc_dev)); 829 return error; 830 } 831 832 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_cmb_block_seg, 833 nsegs, AGE_CMB_BLOCK_SZ, (void **)&sc->age_rdata.age_cmb_block, 834 BUS_DMA_NOWAIT); 835 if (error) 836 return (ENOBUFS); 837 838 memset(sc->age_rdata.age_cmb_block, 0, AGE_CMB_BLOCK_SZ); 839 840 /* Load the DMA map for CMB block. */ 841 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 842 sc->age_rdata.age_cmb_block, AGE_CMB_BLOCK_SZ, NULL, 843 BUS_DMA_WAITOK); 844 if (error) { 845 printf("%s: could not load DMA'able memory for CMB block\n", 846 device_xname(sc->sc_dev)); 847 bus_dmamem_free(sc->sc_dmat, 848 (bus_dma_segment_t *)&sc->age_rdata.age_cmb_block, 1); 849 return error; 850 } 851 852 sc->age_rdata.age_cmb_block_paddr = 853 sc->age_cdata.age_cmb_block_map->dm_segs[0].ds_addr; 854 855 /* 856 * Create DMA stuffs for SMB block 857 */ 858 error = bus_dmamap_create(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 1, 859 AGE_SMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 860 &sc->age_cdata.age_smb_block_map); 861 if (error) 862 return (ENOBUFS); 863 864 /* Allocate DMA'able memory for SMB block */ 865 error = bus_dmamem_alloc(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 866 PAGE_SIZE, 0, &sc->age_rdata.age_smb_block_seg, 1, 867 &nsegs, BUS_DMA_WAITOK); 868 if (error) { 869 printf("%s: could not allocate DMA'able memory for " 870 "SMB block\n", device_xname(sc->sc_dev)); 871 return error; 872 } 873 874 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_smb_block_seg, 875 nsegs, AGE_SMB_BLOCK_SZ, (void **)&sc->age_rdata.age_smb_block, 876 BUS_DMA_NOWAIT); 877 if (error) 878 return (ENOBUFS); 879 880 memset(sc->age_rdata.age_smb_block, 0, AGE_SMB_BLOCK_SZ); 881 882 /* Load the DMA map for SMB block */ 883 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 884 sc->age_rdata.age_smb_block, AGE_SMB_BLOCK_SZ, NULL, 885 BUS_DMA_WAITOK); 886 if (error) { 887 printf("%s: could not load DMA'able memory for SMB block\n", 888 device_xname(sc->sc_dev)); 889 bus_dmamem_free(sc->sc_dmat, 890 (bus_dma_segment_t *)&sc->age_rdata.age_smb_block, 1); 891 return error; 892 } 893 894 sc->age_rdata.age_smb_block_paddr = 895 sc->age_cdata.age_smb_block_map->dm_segs[0].ds_addr; 896 897 /* Create DMA maps for Tx buffers. */ 898 for (i = 0; i < AGE_TX_RING_CNT; i++) { 899 txd = &sc->age_cdata.age_txdesc[i]; 900 txd->tx_m = NULL; 901 txd->tx_dmamap = NULL; 902 error = bus_dmamap_create(sc->sc_dmat, AGE_TSO_MAXSIZE, 903 AGE_MAXTXSEGS, AGE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 904 &txd->tx_dmamap); 905 if (error) { 906 printf("%s: could not create Tx dmamap.\n", 907 device_xname(sc->sc_dev)); 908 return error; 909 } 910 } 911 912 /* Create DMA maps for Rx buffers. */ 913 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 914 BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_sparemap); 915 if (error) { 916 printf("%s: could not create spare Rx dmamap.\n", 917 device_xname(sc->sc_dev)); 918 return error; 919 } 920 for (i = 0; i < AGE_RX_RING_CNT; i++) { 921 rxd = &sc->age_cdata.age_rxdesc[i]; 922 rxd->rx_m = NULL; 923 rxd->rx_dmamap = NULL; 924 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 925 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 926 if (error) { 927 printf("%s: could not create Rx dmamap.\n", 928 device_xname(sc->sc_dev)); 929 return error; 930 } 931 } 932 933 return (0); 934 } 935 936 static void 937 age_dma_free(struct age_softc *sc) 938 { 939 struct age_txdesc *txd; 940 struct age_rxdesc *rxd; 941 int i; 942 943 /* Tx buffers */ 944 for (i = 0; i < AGE_TX_RING_CNT; i++) { 945 txd = &sc->age_cdata.age_txdesc[i]; 946 if (txd->tx_dmamap != NULL) { 947 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 948 txd->tx_dmamap = NULL; 949 } 950 } 951 /* Rx buffers */ 952 for (i = 0; i < AGE_RX_RING_CNT; i++) { 953 rxd = &sc->age_cdata.age_rxdesc[i]; 954 if (rxd->rx_dmamap != NULL) { 955 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 956 rxd->rx_dmamap = NULL; 957 } 958 } 959 if (sc->age_cdata.age_rx_sparemap != NULL) { 960 bus_dmamap_destroy(sc->sc_dmat, sc->age_cdata.age_rx_sparemap); 961 sc->age_cdata.age_rx_sparemap = NULL; 962 } 963 964 /* Tx ring. */ 965 if (sc->age_cdata.age_tx_ring_map != NULL) 966 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_tx_ring_map); 967 if (sc->age_cdata.age_tx_ring_map != NULL && 968 sc->age_rdata.age_tx_ring != NULL) 969 bus_dmamem_free(sc->sc_dmat, 970 (bus_dma_segment_t *)sc->age_rdata.age_tx_ring, 1); 971 sc->age_rdata.age_tx_ring = NULL; 972 sc->age_cdata.age_tx_ring_map = NULL; 973 974 /* Rx ring. */ 975 if (sc->age_cdata.age_rx_ring_map != NULL) 976 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rx_ring_map); 977 if (sc->age_cdata.age_rx_ring_map != NULL && 978 sc->age_rdata.age_rx_ring != NULL) 979 bus_dmamem_free(sc->sc_dmat, 980 (bus_dma_segment_t *)sc->age_rdata.age_rx_ring, 1); 981 sc->age_rdata.age_rx_ring = NULL; 982 sc->age_cdata.age_rx_ring_map = NULL; 983 984 /* Rx return ring. */ 985 if (sc->age_cdata.age_rr_ring_map != NULL) 986 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rr_ring_map); 987 if (sc->age_cdata.age_rr_ring_map != NULL && 988 sc->age_rdata.age_rr_ring != NULL) 989 bus_dmamem_free(sc->sc_dmat, 990 (bus_dma_segment_t *)sc->age_rdata.age_rr_ring, 1); 991 sc->age_rdata.age_rr_ring = NULL; 992 sc->age_cdata.age_rr_ring_map = NULL; 993 994 /* CMB block */ 995 if (sc->age_cdata.age_cmb_block_map != NULL) 996 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_cmb_block_map); 997 if (sc->age_cdata.age_cmb_block_map != NULL && 998 sc->age_rdata.age_cmb_block != NULL) 999 bus_dmamem_free(sc->sc_dmat, 1000 (bus_dma_segment_t *)sc->age_rdata.age_cmb_block, 1); 1001 sc->age_rdata.age_cmb_block = NULL; 1002 sc->age_cdata.age_cmb_block_map = NULL; 1003 1004 /* SMB block */ 1005 if (sc->age_cdata.age_smb_block_map != NULL) 1006 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_smb_block_map); 1007 if (sc->age_cdata.age_smb_block_map != NULL && 1008 sc->age_rdata.age_smb_block != NULL) 1009 bus_dmamem_free(sc->sc_dmat, 1010 (bus_dma_segment_t *)sc->age_rdata.age_smb_block, 1); 1011 } 1012 1013 static void 1014 age_start(struct ifnet *ifp) 1015 { 1016 struct age_softc *sc = ifp->if_softc; 1017 struct mbuf *m_head; 1018 int enq; 1019 1020 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1021 return; 1022 1023 enq = 0; 1024 for (;;) { 1025 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1026 if (m_head == NULL) 1027 break; 1028 1029 /* 1030 * Pack the data into the transmit ring. If we 1031 * don't have room, set the OACTIVE flag and wait 1032 * for the NIC to drain the ring. 1033 */ 1034 if (age_encap(sc, &m_head)) { 1035 if (m_head == NULL) 1036 break; 1037 ifp->if_flags |= IFF_OACTIVE; 1038 break; 1039 } 1040 enq = 1; 1041 1042 #if NBPFILTER > 0 1043 /* 1044 * If there's a BPF listener, bounce a copy of this frame 1045 * to him. 1046 */ 1047 if (ifp->if_bpf != NULL) 1048 bpf_mtap(ifp->if_bpf, m_head); 1049 #endif 1050 } 1051 1052 if (enq) { 1053 /* Update mbox. */ 1054 AGE_COMMIT_MBOX(sc); 1055 /* Set a timeout in case the chip goes out to lunch. */ 1056 ifp->if_timer = AGE_TX_TIMEOUT; 1057 } 1058 } 1059 1060 static void 1061 age_watchdog(struct ifnet *ifp) 1062 { 1063 struct age_softc *sc = ifp->if_softc; 1064 1065 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1066 printf("%s: watchdog timeout (missed link)\n", 1067 device_xname(sc->sc_dev)); 1068 ifp->if_oerrors++; 1069 age_init(ifp); 1070 return; 1071 } 1072 1073 if (sc->age_cdata.age_tx_cnt == 0) { 1074 printf("%s: watchdog timeout (missed Tx interrupts) " 1075 "-- recovering\n", device_xname(sc->sc_dev)); 1076 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1077 age_start(ifp); 1078 return; 1079 } 1080 1081 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1082 ifp->if_oerrors++; 1083 age_init(ifp); 1084 1085 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1086 age_start(ifp); 1087 } 1088 1089 static int 1090 age_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1091 { 1092 struct age_softc *sc = ifp->if_softc; 1093 struct mii_data *mii = &sc->sc_miibus; 1094 struct ifreq *ifr = (struct ifreq *)data; 1095 int s, error = 0; 1096 1097 s = splnet(); 1098 1099 switch (cmd) { 1100 case SIOCSIFMEDIA: 1101 case SIOCGIFMEDIA: 1102 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1103 break; 1104 default: 1105 error = ether_ioctl(ifp, cmd, data); 1106 if (error == ENETRESET) { 1107 if (ifp->if_flags & IFF_RUNNING) 1108 age_rxfilter(sc); 1109 error = 0; 1110 } 1111 break; 1112 } 1113 1114 splx(s); 1115 return error; 1116 } 1117 1118 static void 1119 age_mac_config(struct age_softc *sc) 1120 { 1121 struct mii_data *mii; 1122 uint32_t reg; 1123 1124 mii = &sc->sc_miibus; 1125 1126 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1127 reg &= ~MAC_CFG_FULL_DUPLEX; 1128 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1129 reg &= ~MAC_CFG_SPEED_MASK; 1130 1131 /* Reprogram MAC with resolved speed/duplex. */ 1132 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1133 case IFM_10_T: 1134 case IFM_100_TX: 1135 reg |= MAC_CFG_SPEED_10_100; 1136 break; 1137 case IFM_1000_T: 1138 reg |= MAC_CFG_SPEED_1000; 1139 break; 1140 } 1141 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1142 reg |= MAC_CFG_FULL_DUPLEX; 1143 #ifdef notyet 1144 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1145 reg |= MAC_CFG_TX_FC; 1146 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1147 reg |= MAC_CFG_RX_FC; 1148 #endif 1149 } 1150 1151 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1152 } 1153 1154 static bool 1155 age_resume(device_t dv PMF_FN_ARGS) 1156 { 1157 struct age_softc *sc = device_private(dv); 1158 uint16_t cmd; 1159 1160 /* 1161 * Clear INTx emulation disable for hardware that 1162 * is set in resume event. From Linux. 1163 */ 1164 cmd = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 1165 if ((cmd & 0x0400) != 0) { 1166 cmd &= ~0x0400; 1167 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 1168 PCI_COMMAND_STATUS_REG, cmd); 1169 } 1170 1171 return true; 1172 } 1173 1174 static int 1175 age_encap(struct age_softc *sc, struct mbuf **m_head) 1176 { 1177 struct age_txdesc *txd, *txd_last; 1178 struct tx_desc *desc; 1179 struct mbuf *m; 1180 bus_dmamap_t map; 1181 uint32_t cflags, poff, vtag; 1182 int error, i, nsegs, prod; 1183 struct m_tag *mtag; 1184 1185 m = *m_head; 1186 cflags = vtag = 0; 1187 poff = 0; 1188 1189 prod = sc->age_cdata.age_tx_prod; 1190 txd = &sc->age_cdata.age_txdesc[prod]; 1191 txd_last = txd; 1192 map = txd->tx_dmamap; 1193 1194 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1195 1196 if (error != 0) { 1197 bus_dmamap_unload(sc->sc_dmat, map); 1198 error = EFBIG; 1199 } 1200 if (error == EFBIG) { 1201 error = 0; 1202 1203 MGETHDR(m, M_DONTWAIT, MT_DATA); 1204 if (m == NULL) { 1205 printf("%s: can't defrag TX mbuf\n", 1206 device_xname(sc->sc_dev)); 1207 m_freem(*m_head); 1208 *m_head = NULL; 1209 return (ENOBUFS); 1210 } 1211 1212 MCLGET(m, M_DONTWAIT); 1213 if (!(m->m_flags & M_EXT)) { 1214 m_freem(m); 1215 *m_head = NULL; 1216 return (ENOBUFS); 1217 } 1218 m->m_len = m->m_pkthdr.len; 1219 *m_head = m; 1220 1221 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1222 BUS_DMA_NOWAIT); 1223 1224 if (error != 0) { 1225 printf("%s: could not load defragged TX mbuf\n", 1226 device_xname(sc->sc_dev)); 1227 if (!error) { 1228 bus_dmamap_unload(sc->sc_dmat, map); 1229 error = EFBIG; 1230 } 1231 m_freem(*m_head); 1232 *m_head = NULL; 1233 return (error); 1234 } 1235 } else if (error) { 1236 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 1237 return (error); 1238 } 1239 1240 nsegs = map->dm_nsegs; 1241 1242 if (nsegs == 0) { 1243 m_freem(*m_head); 1244 *m_head = NULL; 1245 return (EIO); 1246 } 1247 1248 /* Check descriptor overrun. */ 1249 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1250 bus_dmamap_unload(sc->sc_dmat, map); 1251 return (ENOBUFS); 1252 } 1253 1254 m = *m_head; 1255 /* Configure Tx IP/TCP/UDP checksum offload. */ 1256 if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1257 cflags |= AGE_TD_CSUM; 1258 if ((m->m_pkthdr.csum_flags & M_CSUM_TCPv4) != 0) 1259 cflags |= AGE_TD_TCPCSUM; 1260 if ((m->m_pkthdr.csum_flags & M_CSUM_UDPv4) != 0) 1261 cflags |= AGE_TD_UDPCSUM; 1262 /* Set checksum start offset. */ 1263 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1264 } 1265 1266 #if NVLAN > 0 1267 /* Configure VLAN hardware tag insertion. */ 1268 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m))) { 1269 vtag = AGE_TX_VLAN_TAG(htons(VLAN_TAG_VALUE(mtag))); 1270 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1271 cflags |= AGE_TD_INSERT_VLAN_TAG; 1272 } 1273 #endif 1274 1275 desc = NULL; 1276 for (i = 0; i < nsegs; i++) { 1277 desc = &sc->age_rdata.age_tx_ring[prod]; 1278 desc->addr = htole64(map->dm_segs[i].ds_addr); 1279 desc->len = 1280 htole32(AGE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 1281 desc->flags = htole32(cflags); 1282 sc->age_cdata.age_tx_cnt++; 1283 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1284 } 1285 1286 /* Update producer index. */ 1287 sc->age_cdata.age_tx_prod = prod; 1288 1289 /* Set EOP on the last descriptor. */ 1290 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1291 desc = &sc->age_rdata.age_tx_ring[prod]; 1292 desc->flags |= htole32(AGE_TD_EOP); 1293 1294 /* Swap dmamap of the first and the last. */ 1295 txd = &sc->age_cdata.age_txdesc[prod]; 1296 map = txd_last->tx_dmamap; 1297 txd_last->tx_dmamap = txd->tx_dmamap; 1298 txd->tx_dmamap = map; 1299 txd->tx_m = m; 1300 1301 /* Sync descriptors. */ 1302 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1303 BUS_DMASYNC_PREWRITE); 1304 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1305 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1306 1307 return (0); 1308 } 1309 1310 static void 1311 age_txintr(struct age_softc *sc, int tpd_cons) 1312 { 1313 struct ifnet *ifp = &sc->sc_ec.ec_if; 1314 struct age_txdesc *txd; 1315 int cons, prog; 1316 1317 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1318 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1319 1320 /* 1321 * Go through our Tx list and free mbufs for those 1322 * frames which have been transmitted. 1323 */ 1324 cons = sc->age_cdata.age_tx_cons; 1325 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 1326 if (sc->age_cdata.age_tx_cnt <= 0) 1327 break; 1328 prog++; 1329 ifp->if_flags &= ~IFF_OACTIVE; 1330 sc->age_cdata.age_tx_cnt--; 1331 txd = &sc->age_cdata.age_txdesc[cons]; 1332 /* 1333 * Clear Tx descriptors, it's not required but would 1334 * help debugging in case of Tx issues. 1335 */ 1336 txd->tx_desc->addr = 0; 1337 txd->tx_desc->len = 0; 1338 txd->tx_desc->flags = 0; 1339 1340 if (txd->tx_m == NULL) 1341 continue; 1342 /* Reclaim transmitted mbufs. */ 1343 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1344 m_freem(txd->tx_m); 1345 txd->tx_m = NULL; 1346 } 1347 1348 if (prog > 0) { 1349 sc->age_cdata.age_tx_cons = cons; 1350 1351 /* 1352 * Unarm watchdog timer only when there are no pending 1353 * Tx descriptors in queue. 1354 */ 1355 if (sc->age_cdata.age_tx_cnt == 0) 1356 ifp->if_timer = 0; 1357 1358 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1359 sc->age_cdata.age_tx_ring_map->dm_mapsize, 1360 BUS_DMASYNC_PREWRITE); 1361 } 1362 } 1363 1364 /* Receive a frame. */ 1365 static void 1366 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 1367 { 1368 struct ifnet *ifp = &sc->sc_ec.ec_if; 1369 struct age_rxdesc *rxd; 1370 struct rx_desc *desc; 1371 struct mbuf *mp, *m; 1372 uint32_t status, index, vtag; 1373 int count, nsegs, pktlen; 1374 int rx_cons; 1375 1376 status = le32toh(rxrd->flags); 1377 index = le32toh(rxrd->index); 1378 rx_cons = AGE_RX_CONS(index); 1379 nsegs = AGE_RX_NSEGS(index); 1380 1381 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 1382 if ((status & AGE_RRD_ERROR) != 0 && 1383 (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 1384 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) { 1385 /* 1386 * We want to pass the following frames to upper 1387 * layer regardless of error status of Rx return 1388 * ring. 1389 * 1390 * o IP/TCP/UDP checksum is bad. 1391 * o frame length and protocol specific length 1392 * does not match. 1393 */ 1394 sc->age_cdata.age_rx_cons += nsegs; 1395 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1396 return; 1397 } 1398 1399 pktlen = 0; 1400 for (count = 0; count < nsegs; count++, 1401 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 1402 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 1403 mp = rxd->rx_m; 1404 desc = rxd->rx_desc; 1405 /* Add a new receive buffer to the ring. */ 1406 if (age_newbuf(sc, rxd, 0) != 0) { 1407 ifp->if_iqdrops++; 1408 /* Reuse Rx buffers. */ 1409 if (sc->age_cdata.age_rxhead != NULL) { 1410 m_freem(sc->age_cdata.age_rxhead); 1411 AGE_RXCHAIN_RESET(sc); 1412 } 1413 break; 1414 } 1415 1416 /* The length of the first mbuf is computed last. */ 1417 if (count != 0) { 1418 mp->m_len = AGE_RX_BYTES(le32toh(desc->len)); 1419 pktlen += mp->m_len; 1420 } 1421 1422 /* Chain received mbufs. */ 1423 if (sc->age_cdata.age_rxhead == NULL) { 1424 sc->age_cdata.age_rxhead = mp; 1425 sc->age_cdata.age_rxtail = mp; 1426 } else { 1427 mp->m_flags &= ~M_PKTHDR; 1428 sc->age_cdata.age_rxprev_tail = 1429 sc->age_cdata.age_rxtail; 1430 sc->age_cdata.age_rxtail->m_next = mp; 1431 sc->age_cdata.age_rxtail = mp; 1432 } 1433 1434 if (count == nsegs - 1) { 1435 /* 1436 * It seems that L1 controller has no way 1437 * to tell hardware to strip CRC bytes. 1438 */ 1439 sc->age_cdata.age_rxlen -= ETHER_CRC_LEN; 1440 if (nsegs > 1) { 1441 /* Remove the CRC bytes in chained mbufs. */ 1442 pktlen -= ETHER_CRC_LEN; 1443 if (mp->m_len <= ETHER_CRC_LEN) { 1444 sc->age_cdata.age_rxtail = 1445 sc->age_cdata.age_rxprev_tail; 1446 sc->age_cdata.age_rxtail->m_len -= 1447 (ETHER_CRC_LEN - mp->m_len); 1448 sc->age_cdata.age_rxtail->m_next = NULL; 1449 m_freem(mp); 1450 } else { 1451 mp->m_len -= ETHER_CRC_LEN; 1452 } 1453 } 1454 1455 m = sc->age_cdata.age_rxhead; 1456 m->m_flags |= M_PKTHDR; 1457 m->m_pkthdr.rcvif = ifp; 1458 m->m_pkthdr.len = sc->age_cdata.age_rxlen; 1459 /* Set the first mbuf length. */ 1460 m->m_len = sc->age_cdata.age_rxlen - pktlen; 1461 1462 /* 1463 * Set checksum information. 1464 * It seems that L1 controller can compute partial 1465 * checksum. The partial checksum value can be used 1466 * to accelerate checksum computation for fragmented 1467 * TCP/UDP packets. Upper network stack already 1468 * takes advantage of the partial checksum value in 1469 * IP reassembly stage. But I'm not sure the 1470 * correctness of the partial hardware checksum 1471 * assistance due to lack of data sheet. If it is 1472 * proven to work on L1 I'll enable it. 1473 */ 1474 if (status & AGE_RRD_IPV4) { 1475 if (!(status & AGE_RRD_IPCSUM_NOK)) 1476 m->m_pkthdr.csum_flags |= 1477 M_CSUM_IPv4_BAD; 1478 if (!((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 1479 (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0)) { 1480 m->m_pkthdr.csum_flags |= 1481 M_CSUM_TCP_UDP_BAD; 1482 } 1483 /* 1484 * Don't mark bad checksum for TCP/UDP frames 1485 * as fragmented frames may always have set 1486 * bad checksummed bit of descriptor status. 1487 */ 1488 } 1489 #if NVLAN > 0 1490 /* Check for VLAN tagged frames. */ 1491 if (status & AGE_RRD_VLAN) { 1492 vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 1493 VLAN_INPUT_TAG(ifp, m, AGE_RX_VLAN_TAG(vtag), 1494 continue); 1495 } 1496 #endif 1497 1498 #if NBPFILTER > 0 1499 if (ifp->if_bpf) 1500 bpf_mtap(ifp->if_bpf, m); 1501 #endif 1502 /* Pass it on. */ 1503 ether_input(ifp, m); 1504 1505 /* Reset mbuf chains. */ 1506 AGE_RXCHAIN_RESET(sc); 1507 } 1508 } 1509 1510 if (count != nsegs) { 1511 sc->age_cdata.age_rx_cons += nsegs; 1512 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1513 } else 1514 sc->age_cdata.age_rx_cons = rx_cons; 1515 } 1516 1517 static void 1518 age_rxintr(struct age_softc *sc, int rr_prod) 1519 { 1520 struct rx_rdesc *rxrd; 1521 int rr_cons, nsegs, pktlen, prog; 1522 1523 rr_cons = sc->age_cdata.age_rr_cons; 1524 if (rr_cons == rr_prod) 1525 return; 1526 1527 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1528 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1529 BUS_DMASYNC_POSTREAD); 1530 1531 for (prog = 0; rr_cons != rr_prod; prog++) { 1532 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 1533 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 1534 if (nsegs == 0) 1535 break; 1536 /* 1537 * Check number of segments against received bytes 1538 * Non-matching value would indicate that hardware 1539 * is still trying to update Rx return descriptors. 1540 * I'm not sure whether this check is really needed. 1541 */ 1542 pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 1543 if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) / 1544 (MCLBYTES - ETHER_ALIGN))) 1545 break; 1546 1547 /* Received a frame. */ 1548 age_rxeof(sc, rxrd); 1549 1550 /* Clear return ring. */ 1551 rxrd->index = 0; 1552 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 1553 } 1554 1555 if (prog > 0) { 1556 /* Update the consumer index. */ 1557 sc->age_cdata.age_rr_cons = rr_cons; 1558 1559 /* Sync descriptors. */ 1560 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1561 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1562 BUS_DMASYNC_PREWRITE); 1563 1564 /* Notify hardware availability of new Rx buffers. */ 1565 AGE_COMMIT_MBOX(sc); 1566 } 1567 } 1568 1569 static void 1570 age_tick(void *xsc) 1571 { 1572 struct age_softc *sc = xsc; 1573 struct mii_data *mii = &sc->sc_miibus; 1574 int s; 1575 1576 s = splnet(); 1577 mii_tick(mii); 1578 splx(s); 1579 1580 callout_schedule(&sc->sc_tick_ch, hz); 1581 } 1582 1583 static void 1584 age_reset(struct age_softc *sc) 1585 { 1586 uint32_t reg; 1587 int i; 1588 1589 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 1590 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1591 DELAY(1); 1592 if ((CSR_READ_4(sc, AGE_MASTER_CFG) & MASTER_RESET) == 0) 1593 break; 1594 } 1595 if (i == 0) 1596 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 1597 1598 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1599 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1600 break; 1601 DELAY(10); 1602 } 1603 1604 if (i == 0) 1605 printf("%s: reset timeout(0x%08x)!\n", device_xname(sc->sc_dev), 1606 reg); 1607 1608 /* Initialize PCIe module. From Linux. */ 1609 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1610 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1611 } 1612 1613 static int 1614 age_init(struct ifnet *ifp) 1615 { 1616 struct age_softc *sc = ifp->if_softc; 1617 struct mii_data *mii; 1618 uint8_t eaddr[ETHER_ADDR_LEN]; 1619 bus_addr_t paddr; 1620 uint32_t reg, fsize; 1621 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 1622 int error; 1623 1624 /* 1625 * Cancel any pending I/O. 1626 */ 1627 age_stop(sc); 1628 1629 /* 1630 * Reset the chip to a known state. 1631 */ 1632 age_reset(sc); 1633 1634 /* Initialize descriptors. */ 1635 error = age_init_rx_ring(sc); 1636 if (error != 0) { 1637 printf("%s: no memory for Rx buffers.\n", device_xname(sc->sc_dev)); 1638 age_stop(sc); 1639 return (error); 1640 } 1641 age_init_rr_ring(sc); 1642 age_init_tx_ring(sc); 1643 age_init_cmb_block(sc); 1644 age_init_smb_block(sc); 1645 1646 /* Reprogram the station address. */ 1647 memcpy(eaddr, CLLADDR(ifp->if_sadl), sizeof(eaddr)); 1648 CSR_WRITE_4(sc, AGE_PAR0, 1649 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1650 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 1651 1652 /* Set descriptor base addresses. */ 1653 paddr = sc->age_rdata.age_tx_ring_paddr; 1654 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 1655 paddr = sc->age_rdata.age_rx_ring_paddr; 1656 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 1657 paddr = sc->age_rdata.age_rr_ring_paddr; 1658 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 1659 paddr = sc->age_rdata.age_tx_ring_paddr; 1660 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 1661 paddr = sc->age_rdata.age_cmb_block_paddr; 1662 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1663 paddr = sc->age_rdata.age_smb_block_paddr; 1664 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1665 1666 /* Set Rx/Rx return descriptor counter. */ 1667 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 1668 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 1669 DESC_RRD_CNT_MASK) | 1670 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 1671 1672 /* Set Tx descriptor counter. */ 1673 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 1674 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 1675 1676 /* Tell hardware that we're ready to load descriptors. */ 1677 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 1678 1679 /* 1680 * Initialize mailbox register. 1681 * Updated producer/consumer index information is exchanged 1682 * through this mailbox register. However Tx producer and 1683 * Rx return consumer/Rx producer are all shared such that 1684 * it's hard to separate code path between Tx and Rx without 1685 * locking. If L1 hardware have a separate mail box register 1686 * for Tx and Rx consumer/producer management we could have 1687 * indepent Tx/Rx handler which in turn Rx handler could have 1688 * been run without any locking. 1689 */ 1690 AGE_COMMIT_MBOX(sc); 1691 1692 /* Configure IPG/IFG parameters. */ 1693 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 1694 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 1695 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1696 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1697 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 1698 1699 /* Set parameters for half-duplex media. */ 1700 CSR_WRITE_4(sc, AGE_HDPX_CFG, 1701 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1702 HDPX_CFG_LCOL_MASK) | 1703 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1704 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1705 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1706 HDPX_CFG_ABEBT_MASK) | 1707 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1708 HDPX_CFG_JAMIPG_MASK)); 1709 1710 /* Configure interrupt moderation timer. */ 1711 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 1712 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 1713 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 1714 reg &= ~MASTER_MTIMER_ENB; 1715 if (AGE_USECS(sc->age_int_mod) == 0) 1716 reg &= ~MASTER_ITIMER_ENB; 1717 else 1718 reg |= MASTER_ITIMER_ENB; 1719 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 1720 if (agedebug) 1721 printf("%s: interrupt moderation is %d us.\n", 1722 device_xname(sc->sc_dev), sc->age_int_mod); 1723 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 1724 1725 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 1726 if (ifp->if_mtu < ETHERMTU) 1727 sc->age_max_frame_size = ETHERMTU; 1728 else 1729 sc->age_max_frame_size = ifp->if_mtu; 1730 sc->age_max_frame_size += ETHER_HDR_LEN + 1731 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 1732 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 1733 1734 /* Configure jumbo frame. */ 1735 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 1736 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 1737 (((fsize / sizeof(uint64_t)) << 1738 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 1739 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 1740 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 1741 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 1742 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 1743 1744 /* Configure flow-control parameters. From Linux. */ 1745 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 1746 /* 1747 * Magic workaround for old-L1. 1748 * Don't know which hw revision requires this magic. 1749 */ 1750 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1751 /* 1752 * Another magic workaround for flow-control mode 1753 * change. From Linux. 1754 */ 1755 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1756 } 1757 /* 1758 * TODO 1759 * Should understand pause parameter relationships between FIFO 1760 * size and number of Rx descriptors and Rx return descriptors. 1761 * 1762 * Magic parameters came from Linux. 1763 */ 1764 switch (sc->age_chip_rev) { 1765 case 0x8001: 1766 case 0x9001: 1767 case 0x9002: 1768 case 0x9003: 1769 rxf_hi = AGE_RX_RING_CNT / 16; 1770 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 1771 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 1772 rrd_lo = AGE_RR_RING_CNT / 16; 1773 break; 1774 default: 1775 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 1776 rxf_lo = reg / 16; 1777 if (rxf_lo < 192) 1778 rxf_lo = 192; 1779 rxf_hi = (reg * 7) / 8; 1780 if (rxf_hi < rxf_lo) 1781 rxf_hi = rxf_lo + 16; 1782 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 1783 rrd_lo = reg / 8; 1784 rrd_hi = (reg * 7) / 8; 1785 if (rrd_lo < 2) 1786 rrd_lo = 2; 1787 if (rrd_hi < rrd_lo) 1788 rrd_hi = rrd_lo + 3; 1789 break; 1790 } 1791 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 1792 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 1793 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 1794 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 1795 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 1796 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 1797 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 1798 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 1799 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 1800 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 1801 1802 /* Configure RxQ. */ 1803 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1804 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 1805 RXQ_CFG_RD_BURST_MASK) | 1806 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 1807 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 1808 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 1809 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 1810 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1811 1812 /* Configure TxQ. */ 1813 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1814 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1815 TXQ_CFG_TPD_BURST_MASK) | 1816 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 1817 TXQ_CFG_TX_FIFO_BURST_MASK) | 1818 ((TXQ_CFG_TPD_FETCH_DEFAULT << 1819 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 1820 TXQ_CFG_ENB); 1821 1822 /* Configure DMA parameters. */ 1823 CSR_WRITE_4(sc, AGE_DMA_CFG, 1824 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 1825 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 1826 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 1827 1828 /* Configure CMB DMA write threshold. */ 1829 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 1830 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 1831 CMB_WR_THRESH_RRD_MASK) | 1832 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 1833 CMB_WR_THRESH_TPD_MASK)); 1834 1835 /* Set CMB/SMB timer and enable them. */ 1836 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 1837 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 1838 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 1839 1840 /* Request SMB updates for every seconds. */ 1841 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 1842 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 1843 1844 /* 1845 * Disable all WOL bits as WOL can interfere normal Rx 1846 * operation. 1847 */ 1848 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1849 1850 /* 1851 * Configure Tx/Rx MACs. 1852 * - Auto-padding for short frames. 1853 * - Enable CRC generation. 1854 * Start with full-duplex/1000Mbps media. Actual reconfiguration 1855 * of MAC is followed after link establishment. 1856 */ 1857 CSR_WRITE_4(sc, AGE_MAC_CFG, 1858 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 1859 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 1860 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1861 MAC_CFG_PREAMBLE_MASK)); 1862 1863 /* Set up the receive filter. */ 1864 age_rxfilter(sc); 1865 age_rxvlan(sc); 1866 1867 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1868 reg |= MAC_CFG_RXCSUM_ENB; 1869 1870 /* Ack all pending interrupts and clear it. */ 1871 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 1872 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 1873 1874 /* Finally enable Tx/Rx MAC. */ 1875 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 1876 1877 sc->age_flags &= ~AGE_FLAG_LINK; 1878 1879 /* Switch to the current media. */ 1880 mii = &sc->sc_miibus; 1881 mii_mediachg(mii); 1882 1883 callout_schedule(&sc->sc_tick_ch, hz); 1884 1885 ifp->if_flags |= IFF_RUNNING; 1886 ifp->if_flags &= ~IFF_OACTIVE; 1887 1888 return (0); 1889 } 1890 1891 static void 1892 age_stop(struct age_softc *sc) 1893 { 1894 struct ifnet *ifp = &sc->sc_ec.ec_if; 1895 struct age_txdesc *txd; 1896 struct age_rxdesc *rxd; 1897 uint32_t reg; 1898 int i; 1899 1900 callout_stop(&sc->sc_tick_ch); 1901 1902 /* 1903 * Mark the interface down and cancel the watchdog timer. 1904 */ 1905 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1906 ifp->if_timer = 0; 1907 1908 sc->age_flags &= ~AGE_FLAG_LINK; 1909 1910 /* 1911 * Disable interrupts. 1912 */ 1913 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 1914 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 1915 1916 /* Stop CMB/SMB updates. */ 1917 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 1918 1919 /* Stop Rx/Tx MAC. */ 1920 age_stop_rxmac(sc); 1921 age_stop_txmac(sc); 1922 1923 /* Stop DMA. */ 1924 CSR_WRITE_4(sc, AGE_DMA_CFG, 1925 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 1926 1927 /* Stop TxQ/RxQ. */ 1928 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1929 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 1930 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1931 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 1932 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1933 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1934 break; 1935 DELAY(10); 1936 } 1937 if (i == 0) 1938 printf("%s: stopping Rx/Tx MACs timed out(0x%08x)!\n", 1939 device_xname(sc->sc_dev), reg); 1940 1941 /* Reclaim Rx buffers that have been processed. */ 1942 if (sc->age_cdata.age_rxhead != NULL) 1943 m_freem(sc->age_cdata.age_rxhead); 1944 AGE_RXCHAIN_RESET(sc); 1945 1946 /* 1947 * Free RX and TX mbufs still in the queues. 1948 */ 1949 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1950 rxd = &sc->age_cdata.age_rxdesc[i]; 1951 if (rxd->rx_m != NULL) { 1952 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1953 m_freem(rxd->rx_m); 1954 rxd->rx_m = NULL; 1955 } 1956 } 1957 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1958 txd = &sc->age_cdata.age_txdesc[i]; 1959 if (txd->tx_m != NULL) { 1960 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1961 m_freem(txd->tx_m); 1962 txd->tx_m = NULL; 1963 } 1964 } 1965 } 1966 1967 static void 1968 age_stats_update(struct age_softc *sc) 1969 { 1970 struct ifnet *ifp = &sc->sc_ec.ec_if; 1971 struct age_stats *stat; 1972 struct smb *smb; 1973 1974 stat = &sc->age_stat; 1975 1976 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 1977 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1978 1979 smb = sc->age_rdata.age_smb_block; 1980 if (smb->updated == 0) 1981 return; 1982 1983 /* Rx stats. */ 1984 stat->rx_frames += smb->rx_frames; 1985 stat->rx_bcast_frames += smb->rx_bcast_frames; 1986 stat->rx_mcast_frames += smb->rx_mcast_frames; 1987 stat->rx_pause_frames += smb->rx_pause_frames; 1988 stat->rx_control_frames += smb->rx_control_frames; 1989 stat->rx_crcerrs += smb->rx_crcerrs; 1990 stat->rx_lenerrs += smb->rx_lenerrs; 1991 stat->rx_bytes += smb->rx_bytes; 1992 stat->rx_runts += smb->rx_runts; 1993 stat->rx_fragments += smb->rx_fragments; 1994 stat->rx_pkts_64 += smb->rx_pkts_64; 1995 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1996 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1997 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1998 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1999 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2000 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2001 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2002 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2003 stat->rx_desc_oflows += smb->rx_desc_oflows; 2004 stat->rx_alignerrs += smb->rx_alignerrs; 2005 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2006 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2007 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2008 2009 /* Tx stats. */ 2010 stat->tx_frames += smb->tx_frames; 2011 stat->tx_bcast_frames += smb->tx_bcast_frames; 2012 stat->tx_mcast_frames += smb->tx_mcast_frames; 2013 stat->tx_pause_frames += smb->tx_pause_frames; 2014 stat->tx_excess_defer += smb->tx_excess_defer; 2015 stat->tx_control_frames += smb->tx_control_frames; 2016 stat->tx_deferred += smb->tx_deferred; 2017 stat->tx_bytes += smb->tx_bytes; 2018 stat->tx_pkts_64 += smb->tx_pkts_64; 2019 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2020 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2021 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2022 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2023 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2024 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2025 stat->tx_single_colls += smb->tx_single_colls; 2026 stat->tx_multi_colls += smb->tx_multi_colls; 2027 stat->tx_late_colls += smb->tx_late_colls; 2028 stat->tx_excess_colls += smb->tx_excess_colls; 2029 stat->tx_underrun += smb->tx_underrun; 2030 stat->tx_desc_underrun += smb->tx_desc_underrun; 2031 stat->tx_lenerrs += smb->tx_lenerrs; 2032 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2033 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2034 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2035 2036 /* Update counters in ifnet. */ 2037 ifp->if_opackets += smb->tx_frames; 2038 2039 ifp->if_collisions += smb->tx_single_colls + 2040 smb->tx_multi_colls + smb->tx_late_colls + 2041 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 2042 2043 ifp->if_oerrors += smb->tx_excess_colls + 2044 smb->tx_late_colls + smb->tx_underrun + 2045 smb->tx_pkts_truncated; 2046 2047 ifp->if_ipackets += smb->rx_frames; 2048 2049 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2050 smb->rx_runts + smb->rx_pkts_truncated + 2051 smb->rx_fifo_oflows + smb->rx_desc_oflows + 2052 smb->rx_alignerrs; 2053 2054 /* Update done, clear. */ 2055 smb->updated = 0; 2056 2057 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2058 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2059 } 2060 2061 static void 2062 age_stop_txmac(struct age_softc *sc) 2063 { 2064 uint32_t reg; 2065 int i; 2066 2067 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2068 if ((reg & MAC_CFG_TX_ENB) != 0) { 2069 reg &= ~MAC_CFG_TX_ENB; 2070 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2071 } 2072 /* Stop Tx DMA engine. */ 2073 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2074 if ((reg & DMA_CFG_RD_ENB) != 0) { 2075 reg &= ~DMA_CFG_RD_ENB; 2076 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2077 } 2078 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2079 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2080 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2081 break; 2082 DELAY(10); 2083 } 2084 if (i == 0) 2085 printf("%s: stopping TxMAC timeout!\n", device_xname(sc->sc_dev)); 2086 } 2087 2088 static void 2089 age_stop_rxmac(struct age_softc *sc) 2090 { 2091 uint32_t reg; 2092 int i; 2093 2094 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2095 if ((reg & MAC_CFG_RX_ENB) != 0) { 2096 reg &= ~MAC_CFG_RX_ENB; 2097 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2098 } 2099 /* Stop Rx DMA engine. */ 2100 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2101 if ((reg & DMA_CFG_WR_ENB) != 0) { 2102 reg &= ~DMA_CFG_WR_ENB; 2103 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2104 } 2105 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2106 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2107 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2108 break; 2109 DELAY(10); 2110 } 2111 if (i == 0) 2112 printf("%s: stopping RxMAC timeout!\n", device_xname(sc->sc_dev)); 2113 } 2114 2115 static void 2116 age_init_tx_ring(struct age_softc *sc) 2117 { 2118 struct age_ring_data *rd; 2119 struct age_txdesc *txd; 2120 int i; 2121 2122 sc->age_cdata.age_tx_prod = 0; 2123 sc->age_cdata.age_tx_cons = 0; 2124 sc->age_cdata.age_tx_cnt = 0; 2125 2126 rd = &sc->age_rdata; 2127 memset(rd->age_tx_ring, 0, AGE_TX_RING_SZ); 2128 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2129 txd = &sc->age_cdata.age_txdesc[i]; 2130 txd->tx_desc = &rd->age_tx_ring[i]; 2131 txd->tx_m = NULL; 2132 } 2133 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 2134 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2135 } 2136 2137 static int 2138 age_init_rx_ring(struct age_softc *sc) 2139 { 2140 struct age_ring_data *rd; 2141 struct age_rxdesc *rxd; 2142 int i; 2143 2144 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 2145 rd = &sc->age_rdata; 2146 memset(rd->age_rx_ring, 0, AGE_RX_RING_SZ); 2147 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2148 rxd = &sc->age_cdata.age_rxdesc[i]; 2149 rxd->rx_m = NULL; 2150 rxd->rx_desc = &rd->age_rx_ring[i]; 2151 if (age_newbuf(sc, rxd, 1) != 0) 2152 return (ENOBUFS); 2153 } 2154 2155 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 0, 2156 sc->age_cdata.age_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2157 2158 return (0); 2159 } 2160 2161 static void 2162 age_init_rr_ring(struct age_softc *sc) 2163 { 2164 struct age_ring_data *rd; 2165 2166 sc->age_cdata.age_rr_cons = 0; 2167 AGE_RXCHAIN_RESET(sc); 2168 2169 rd = &sc->age_rdata; 2170 memset(rd->age_rr_ring, 0, AGE_RR_RING_SZ); 2171 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 2172 sc->age_cdata.age_rr_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2173 } 2174 2175 static void 2176 age_init_cmb_block(struct age_softc *sc) 2177 { 2178 struct age_ring_data *rd; 2179 2180 rd = &sc->age_rdata; 2181 memset(rd->age_cmb_block, 0, AGE_CMB_BLOCK_SZ); 2182 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 2183 sc->age_cdata.age_cmb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2184 } 2185 2186 static void 2187 age_init_smb_block(struct age_softc *sc) 2188 { 2189 struct age_ring_data *rd; 2190 2191 rd = &sc->age_rdata; 2192 memset(rd->age_smb_block, 0, AGE_SMB_BLOCK_SZ); 2193 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2194 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2195 } 2196 2197 static int 2198 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd, int init) 2199 { 2200 struct rx_desc *desc; 2201 struct mbuf *m; 2202 bus_dmamap_t map; 2203 int error; 2204 2205 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 2206 if (m == NULL) 2207 return (ENOBUFS); 2208 MCLGET(m, init ? M_WAITOK : M_DONTWAIT); 2209 if (!(m->m_flags & M_EXT)) { 2210 m_freem(m); 2211 return (ENOBUFS); 2212 } 2213 2214 m->m_len = m->m_pkthdr.len = MCLBYTES; 2215 m_adj(m, ETHER_ALIGN); 2216 2217 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2218 sc->age_cdata.age_rx_sparemap, m, BUS_DMA_NOWAIT); 2219 2220 if (error != 0) { 2221 if (!error) { 2222 bus_dmamap_unload(sc->sc_dmat, 2223 sc->age_cdata.age_rx_sparemap); 2224 error = EFBIG; 2225 printf("%s: too many segments?!\n", 2226 device_xname(sc->sc_dev)); 2227 } 2228 m_freem(m); 2229 2230 if (init) 2231 printf("%s: can't load RX mbuf\n", device_xname(sc->sc_dev)); 2232 return (error); 2233 } 2234 2235 if (rxd->rx_m != NULL) { 2236 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2237 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2238 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2239 } 2240 map = rxd->rx_dmamap; 2241 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 2242 sc->age_cdata.age_rx_sparemap = map; 2243 rxd->rx_m = m; 2244 2245 desc = rxd->rx_desc; 2246 desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 2247 desc->len = 2248 htole32((rxd->rx_dmamap->dm_segs[0].ds_len & AGE_RD_LEN_MASK) << 2249 AGE_RD_LEN_SHIFT); 2250 2251 return (0); 2252 } 2253 2254 static void 2255 age_rxvlan(struct age_softc *sc) 2256 { 2257 uint32_t reg; 2258 2259 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2260 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2261 if (sc->sc_ec.ec_capabilities & ETHERCAP_VLAN_HWTAGGING) 2262 reg |= MAC_CFG_VLAN_TAG_STRIP; 2263 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2264 } 2265 2266 static void 2267 age_rxfilter(struct age_softc *sc) 2268 { 2269 struct ethercom *ec = &sc->sc_ec; 2270 struct ifnet *ifp = &sc->sc_ec.ec_if; 2271 struct ether_multi *enm; 2272 struct ether_multistep step; 2273 uint32_t crc; 2274 uint32_t mchash[2]; 2275 uint32_t rxcfg; 2276 2277 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 2278 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2279 2280 if (ifp->if_flags & IFF_BROADCAST) 2281 rxcfg |= MAC_CFG_BCAST; 2282 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 2283 if (ifp->if_flags & IFF_PROMISC) 2284 rxcfg |= MAC_CFG_PROMISC; 2285 if (ifp->if_flags & IFF_ALLMULTI) 2286 rxcfg |= MAC_CFG_ALLMULTI; 2287 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF); 2288 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF); 2289 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 2290 return; 2291 } 2292 2293 /* Program new filter. */ 2294 memset(mchash, 0, sizeof(mchash)); 2295 2296 ETHER_FIRST_MULTI(step, ec, enm); 2297 while (enm != NULL) { 2298 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 2299 enm->enm_addrlo), ETHER_ADDR_LEN); 2300 2301 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2302 ETHER_NEXT_MULTI(step, enm); 2303 } 2304 2305 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 2306 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 2307 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 2308 } 2309
Indexes created Mon Sep 29 21:09:56 GMT 2025