if_age.c revision 1.15
1 /* $NetBSD: if_age.c,v 1.15 2009/01/30 08:46:25 cegger Exp $ */ 2 /* $OpenBSD: if_age.c,v 1.1 2009/01/16 05:00:34 kevlo Exp $ */ 3 4 /*- 5 * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: if_age.c,v 1.15 2009/01/30 08:46:25 cegger Exp $"); 35 36 #include "bpfilter.h" 37 #include "vlan.h" 38 39 #include <sys/param.h> 40 #include <sys/proc.h> 41 #include <sys/endian.h> 42 #include <sys/systm.h> 43 #include <sys/types.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/queue.h> 47 #include <sys/kernel.h> 48 #include <sys/device.h> 49 #include <sys/callout.h> 50 #include <sys/socket.h> 51 52 #include <net/if.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #ifdef INET 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/in_var.h> 61 #include <netinet/ip.h> 62 #endif 63 64 #include <net/if_types.h> 65 #include <net/if_vlanvar.h> 66 67 #if NBPFILTER > 0 68 #include <net/bpf.h> 69 #endif 70 71 #include <sys/rnd.h> 72 73 #include <dev/mii/mii.h> 74 #include <dev/mii/miivar.h> 75 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/pcidevs.h> 79 80 #include <dev/pci/if_agereg.h> 81 82 static int age_match(device_t, cfdata_t, void *); 83 static void age_attach(device_t, device_t, void *); 84 static int age_detach(device_t, int); 85 86 static bool age_resume(device_t PMF_FN_PROTO); 87 88 static int age_miibus_readreg(device_t, int, int); 89 static void age_miibus_writereg(device_t, int, int, int); 90 static void age_miibus_statchg(device_t); 91 92 static int age_init(struct ifnet *); 93 static int age_ioctl(struct ifnet *, u_long, void *); 94 static void age_start(struct ifnet *); 95 static void age_watchdog(struct ifnet *); 96 static void age_mediastatus(struct ifnet *, struct ifmediareq *); 97 static int age_mediachange(struct ifnet *); 98 99 static int age_intr(void *); 100 static int age_read_vpd_word(struct age_softc *, uint32_t, uint32_t, uint32_t *); 101 static int age_dma_alloc(struct age_softc *); 102 static void age_dma_free(struct age_softc *); 103 static void age_get_macaddr(struct age_softc *, uint8_t[]); 104 static void age_phy_reset(struct age_softc *); 105 106 static int age_encap(struct age_softc *, struct mbuf **); 107 static void age_init_tx_ring(struct age_softc *); 108 static int age_init_rx_ring(struct age_softc *); 109 static void age_init_rr_ring(struct age_softc *); 110 static void age_init_cmb_block(struct age_softc *); 111 static void age_init_smb_block(struct age_softc *); 112 static int age_newbuf(struct age_softc *, struct age_rxdesc *, int); 113 static void age_mac_config(struct age_softc *); 114 static void age_txintr(struct age_softc *, int); 115 static void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 116 static void age_rxintr(struct age_softc *, int); 117 static void age_tick(void *); 118 static void age_reset(struct age_softc *); 119 static void age_stop(struct age_softc *); 120 static void age_stats_update(struct age_softc *); 121 static void age_stop_txmac(struct age_softc *); 122 static void age_stop_rxmac(struct age_softc *); 123 static void age_rxvlan(struct age_softc *sc); 124 static void age_rxfilter(struct age_softc *); 125 126 CFATTACH_DECL_NEW(age, sizeof(struct age_softc), 127 age_match, age_attach, age_detach, NULL); 128 129 int agedebug = 0; 130 #define DPRINTF(x) do { if (agedebug) printf x; } while (0) 131 132 #define ETHER_ALIGN 2 133 #define AGE_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 134 135 static int 136 age_match(device_t dev, cfdata_t match, void *aux) 137 { 138 struct pci_attach_args *pa = aux; 139 140 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && 141 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_GIGA); 142 } 143 144 static void 145 age_attach(device_t parent, device_t self, void *aux) 146 { 147 struct age_softc *sc = device_private(self); 148 struct pci_attach_args *pa = aux; 149 pci_intr_handle_t ih; 150 const char *intrstr; 151 struct ifnet *ifp = &sc->sc_ec.ec_if; 152 pcireg_t memtype; 153 int error = 0; 154 155 aprint_naive("\n"); 156 aprint_normal(": Attansic/Atheros L1 Gigabit Ethernet\n"); 157 158 sc->sc_dev = self; 159 sc->sc_dmat = pa->pa_dmat; 160 sc->sc_pct = pa->pa_pc; 161 sc->sc_pcitag = pa->pa_tag; 162 163 /* 164 * Allocate IO memory 165 */ 166 memtype = pci_mapreg_type(sc->sc_pct, sc->sc_pcitag, AGE_PCIR_BAR); 167 switch (memtype) { 168 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 169 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 170 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 171 break; 172 default: 173 aprint_error_dev(self, "invalid base address register\n"); 174 break; 175 } 176 177 if (pci_mapreg_map(pa, AGE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 178 &sc->sc_mem_bh, NULL, &sc->sc_mem_size) != 0) { 179 aprint_error_dev(self, "could not map mem space\n"); 180 return; 181 } 182 183 if (pci_intr_map(pa, &ih) != 0) { 184 aprint_error_dev(self, "could not map interrupt\n"); 185 return; 186 } 187 188 /* 189 * Allocate IRQ 190 */ 191 intrstr = pci_intr_string(sc->sc_pct, ih); 192 sc->sc_irq_handle = pci_intr_establish(sc->sc_pct, ih, IPL_NET, 193 age_intr, sc); 194 if (sc->sc_irq_handle == NULL) { 195 aprint_error_dev(self, "could not establish interrupt"); 196 if (intrstr != NULL) 197 aprint_error(" at %s", intrstr); 198 aprint_error("\n"); 199 return; 200 } 201 aprint_normal_dev(self, "%s\n", intrstr); 202 203 /* Set PHY address. */ 204 sc->age_phyaddr = AGE_PHY_ADDR; 205 206 /* Reset PHY. */ 207 age_phy_reset(sc); 208 209 /* Reset the ethernet controller. */ 210 age_reset(sc); 211 212 /* Get PCI and chip id/revision. */ 213 sc->age_rev = PCI_REVISION(pa->pa_class); 214 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 215 MASTER_CHIP_REV_SHIFT; 216 217 aprint_debug_dev(self, "PCI device revision : 0x%04x\n", sc->age_rev); 218 aprint_debug_dev(self, "Chip id/revision : 0x%04x\n", sc->age_chip_rev); 219 220 if (agedebug) { 221 aprint_debug_dev(self, "%d Tx FIFO, %d Rx FIFO\n", 222 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 223 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 224 } 225 226 /* Set max allowable DMA size. */ 227 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 228 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 229 230 /* Allocate DMA stuffs */ 231 error = age_dma_alloc(sc); 232 if (error) 233 goto fail; 234 235 callout_init(&sc->sc_tick_ch, 0); 236 callout_setfunc(&sc->sc_tick_ch, age_tick, sc); 237 238 /* Load station address. */ 239 age_get_macaddr(sc, sc->sc_enaddr); 240 241 aprint_normal_dev(self, "Ethernet address %s\n", 242 ether_sprintf(sc->sc_enaddr)); 243 244 ifp->if_softc = sc; 245 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 246 ifp->if_init = age_init; 247 ifp->if_ioctl = age_ioctl; 248 ifp->if_start = age_start; 249 ifp->if_watchdog = age_watchdog; 250 ifp->if_baudrate = IF_Gbps(1); 251 IFQ_SET_MAXLEN(&ifp->if_snd, AGE_TX_RING_CNT - 1); 252 IFQ_SET_READY(&ifp->if_snd); 253 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 254 255 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 256 257 #ifdef AGE_CHECKSUM 258 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 259 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 260 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 261 #endif 262 263 #if NVLAN > 0 264 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 265 #endif 266 267 /* Set up MII bus. */ 268 sc->sc_miibus.mii_ifp = ifp; 269 sc->sc_miibus.mii_readreg = age_miibus_readreg; 270 sc->sc_miibus.mii_writereg = age_miibus_writereg; 271 sc->sc_miibus.mii_statchg = age_miibus_statchg; 272 273 ifmedia_init(&sc->sc_miibus.mii_media, 0, age_mediachange, 274 age_mediastatus); 275 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 276 MII_OFFSET_ANY, 0); 277 278 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 279 aprint_error_dev(self, "no PHY found!\n"); 280 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 281 0, NULL); 282 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 283 } else 284 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 285 286 if_attach(ifp); 287 ether_ifattach(ifp, sc->sc_enaddr); 288 289 if (!pmf_device_register(self, NULL, age_resume)) 290 aprint_error_dev(self, "couldn't establish power handler\n"); 291 else 292 pmf_class_network_register(self, ifp); 293 294 return; 295 296 fail: 297 if (sc->sc_irq_handle != NULL) { 298 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 299 sc->sc_irq_handle = NULL; 300 } 301 } 302 303 static int 304 age_detach(device_t self, int flags) 305 { 306 struct age_softc *sc = device_private(self); 307 struct ifnet *ifp = &sc->sc_ec.ec_if; 308 int s; 309 310 s = splnet(); 311 age_stop(sc); 312 splx(s); 313 314 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 315 316 /* Delete all remaining media. */ 317 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 318 319 ether_ifdetach(ifp); 320 if_detach(ifp); 321 age_dma_free(sc); 322 323 if (sc->sc_irq_handle != NULL) { 324 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 325 sc->sc_irq_handle = NULL; 326 } 327 328 return 0; 329 } 330 331 /* 332 * Read a PHY register on the MII of the L1. 333 */ 334 static int 335 age_miibus_readreg(device_t dev, int phy, int reg) 336 { 337 struct age_softc *sc = device_private(dev); 338 uint32_t v; 339 int i; 340 341 if (phy != sc->age_phyaddr) 342 return 0; 343 344 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 345 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 346 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 347 DELAY(1); 348 v = CSR_READ_4(sc, AGE_MDIO); 349 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 350 break; 351 } 352 353 if (i == 0) { 354 printf("%s: phy read timeout: phy %d, reg %d\n", 355 device_xname(sc->sc_dev), phy, reg); 356 return 0; 357 } 358 359 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 360 } 361 362 /* 363 * Write a PHY register on the MII of the L1. 364 */ 365 static void 366 age_miibus_writereg(device_t dev, int phy, int reg, int val) 367 { 368 struct age_softc *sc = device_private(dev); 369 uint32_t v; 370 int i; 371 372 if (phy != sc->age_phyaddr) 373 return; 374 375 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 376 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 377 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 378 379 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 380 DELAY(1); 381 v = CSR_READ_4(sc, AGE_MDIO); 382 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 383 break; 384 } 385 386 if (i == 0) { 387 printf("%s: phy write timeout: phy %d, reg %d\n", 388 device_xname(sc->sc_dev), phy, reg); 389 } 390 } 391 392 /* 393 * Callback from MII layer when media changes. 394 */ 395 static void 396 age_miibus_statchg(device_t dev) 397 { 398 struct age_softc *sc = device_private(dev); 399 struct ifnet *ifp = &sc->sc_ec.ec_if; 400 struct mii_data *mii; 401 402 if ((ifp->if_flags & IFF_RUNNING) == 0) 403 return; 404 405 mii = &sc->sc_miibus; 406 407 sc->age_flags &= ~AGE_FLAG_LINK; 408 if ((mii->mii_media_status & IFM_AVALID) != 0) { 409 switch (IFM_SUBTYPE(mii->mii_media_active)) { 410 case IFM_10_T: 411 case IFM_100_TX: 412 case IFM_1000_T: 413 sc->age_flags |= AGE_FLAG_LINK; 414 break; 415 default: 416 break; 417 } 418 } 419 420 /* Stop Rx/Tx MACs. */ 421 age_stop_rxmac(sc); 422 age_stop_txmac(sc); 423 424 /* Program MACs with resolved speed/duplex/flow-control. */ 425 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 426 uint32_t reg; 427 428 age_mac_config(sc); 429 reg = CSR_READ_4(sc, AGE_MAC_CFG); 430 /* Restart DMA engine and Tx/Rx MAC. */ 431 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 432 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 433 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 434 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 435 } 436 } 437 438 /* 439 * Get the current interface media status. 440 */ 441 static void 442 age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 443 { 444 struct age_softc *sc = ifp->if_softc; 445 struct mii_data *mii = &sc->sc_miibus; 446 447 mii_pollstat(mii); 448 ifmr->ifm_status = mii->mii_media_status; 449 ifmr->ifm_active = mii->mii_media_active; 450 } 451 452 /* 453 * Set hardware to newly-selected media. 454 */ 455 static int 456 age_mediachange(struct ifnet *ifp) 457 { 458 struct age_softc *sc = ifp->if_softc; 459 struct mii_data *mii = &sc->sc_miibus; 460 int error; 461 462 if (mii->mii_instance != 0) { 463 struct mii_softc *miisc; 464 465 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 466 mii_phy_reset(miisc); 467 } 468 error = mii_mediachg(mii); 469 470 return error; 471 } 472 473 static int 474 age_intr(void *arg) 475 { 476 struct age_softc *sc = arg; 477 struct ifnet *ifp = &sc->sc_ec.ec_if; 478 struct cmb *cmb; 479 uint32_t status; 480 481 status = CSR_READ_4(sc, AGE_INTR_STATUS); 482 if (status == 0 || (status & AGE_INTRS) == 0) 483 return 0; 484 485 cmb = sc->age_rdata.age_cmb_block; 486 if (cmb == NULL) 487 return 0; 488 489 /* Disable interrupts. */ 490 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 491 492 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 493 sc->age_cdata.age_cmb_block_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 494 status = le32toh(cmb->intr_status); 495 if ((status & AGE_INTRS) == 0) 496 goto back; 497 498 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 499 TPD_CONS_SHIFT; 500 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 501 RRD_PROD_SHIFT; 502 503 /* Let hardware know CMB was served. */ 504 cmb->intr_status = 0; 505 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 506 sc->age_cdata.age_cmb_block_map->dm_mapsize, 507 BUS_DMASYNC_PREWRITE); 508 509 if (ifp->if_flags & IFF_RUNNING) { 510 if (status & INTR_CMB_RX) 511 age_rxintr(sc, sc->age_rr_prod); 512 513 if (status & INTR_CMB_TX) 514 age_txintr(sc, sc->age_tpd_cons); 515 516 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 517 if (status & INTR_DMA_RD_TO_RST) 518 printf("%s: DMA read error! -- resetting\n", 519 device_xname(sc->sc_dev)); 520 if (status & INTR_DMA_WR_TO_RST) 521 printf("%s: DMA write error! -- resetting\n", 522 device_xname(sc->sc_dev)); 523 age_init(ifp); 524 } 525 526 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 527 age_start(ifp); 528 529 if (status & INTR_SMB) 530 age_stats_update(sc); 531 } 532 533 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 534 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 535 sc->age_cdata.age_cmb_block_map->dm_mapsize, 536 BUS_DMASYNC_POSTREAD); 537 538 back: 539 /* Re-enable interrupts. */ 540 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 541 542 return 1; 543 } 544 545 static int 546 age_read_vpd_word(struct age_softc *sc, uint32_t vpdc, uint32_t offset, 547 uint32_t *word) 548 { 549 int i; 550 pcireg_t rv; 551 552 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_VPD_ADDRESS(vpdc), 553 offset << PCI_VPD_ADDRESS_SHIFT); 554 for (i = AGE_TIMEOUT; i > 0; i--) { 555 DELAY(10); 556 rv = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 557 PCI_VPD_ADDRESS(vpdc)); 558 if ((rv & PCI_VPD_OPFLAG) == PCI_VPD_OPFLAG) 559 break; 560 } 561 if (i == 0) { 562 printf("%s: VPD read timeout!\n", device_xname(sc->sc_dev)); 563 *word = 0; 564 return ETIMEDOUT; 565 } 566 567 *word = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_VPD_DATAREG(vpdc)); 568 return 0; 569 } 570 571 static void 572 age_get_macaddr(struct age_softc *sc, uint8_t eaddr[]) 573 { 574 uint32_t ea[2], off, reg, word; 575 int vpd_error, match, vpdc; 576 577 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 578 if ((reg & SPI_VPD_ENB) != 0) { 579 /* Get VPD stored in TWSI EEPROM. */ 580 reg &= ~SPI_VPD_ENB; 581 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 582 } 583 584 vpd_error = 0; 585 ea[0] = ea[1] = 0; 586 if ((vpd_error = pci_get_capability(sc->sc_pct, sc->sc_pcitag, 587 PCI_CAP_VPD, &vpdc, NULL))) { 588 /* 589 * PCI VPD capability exists, but it seems that it's 590 * not in the standard form as stated in PCI VPD 591 * specification such that driver could not use 592 * pci_get_vpd_readonly(9) with keyword 'NA'. 593 * Search VPD data starting at address 0x0100. The data 594 * should be used as initializers to set AGE_PAR0, 595 * AGE_PAR1 register including other PCI configuration 596 * registers. 597 */ 598 word = 0; 599 match = 0; 600 reg = 0; 601 for (off = AGE_VPD_REG_CONF_START; off < AGE_VPD_REG_CONF_END; 602 off += sizeof(uint32_t)) { 603 vpd_error = age_read_vpd_word(sc, vpdc, off, &word); 604 if (vpd_error != 0) 605 break; 606 if (match != 0) { 607 switch (reg) { 608 case AGE_PAR0: 609 ea[0] = word; 610 break; 611 case AGE_PAR1: 612 ea[1] = word; 613 break; 614 default: 615 break; 616 } 617 match = 0; 618 } else if ((word & 0xFF) == AGE_VPD_REG_CONF_SIG) { 619 match = 1; 620 reg = word >> 16; 621 } else 622 break; 623 } 624 if (off >= AGE_VPD_REG_CONF_END) 625 vpd_error = ENOENT; 626 if (vpd_error == 0) { 627 /* 628 * Don't blindly trust ethernet address obtained 629 * from VPD. Check whether ethernet address is 630 * valid one. Otherwise fall-back to reading 631 * PAR register. 632 */ 633 ea[1] &= 0xFFFF; 634 if ((ea[0] == 0 && ea[1] == 0) || 635 (ea[0] == 0xFFFFFFFF && ea[1] == 0xFFFF)) { 636 if (agedebug) 637 printf("%s: invalid ethernet address " 638 "returned from VPD.\n", 639 device_xname(sc->sc_dev)); 640 vpd_error = EINVAL; 641 } 642 } 643 if (vpd_error != 0 && (agedebug)) 644 printf("%s: VPD access failure!\n", 645 device_xname(sc->sc_dev)); 646 } else { 647 if (agedebug) 648 printf("%s: PCI VPD capability not found!\n", 649 device_xname(sc->sc_dev)); 650 } 651 652 /* 653 * It seems that L1 also provides a way to extract ethernet 654 * address via SPI flash interface. Because SPI flash memory 655 * device of different vendors vary in their instruction 656 * codes for read ID instruction, it's very hard to get 657 * instructions codes without detailed information for the 658 * flash memory device used on ethernet controller. To simplify 659 * code, just read AGE_PAR0/AGE_PAR1 register to get ethernet 660 * address which is supposed to be set by hardware during 661 * power on reset. 662 */ 663 if (vpd_error != 0) { 664 /* 665 * VPD is mapped to SPI flash memory or BIOS set it. 666 */ 667 ea[0] = CSR_READ_4(sc, AGE_PAR0); 668 ea[1] = CSR_READ_4(sc, AGE_PAR1); 669 } 670 671 ea[1] &= 0xFFFF; 672 eaddr[0] = (ea[1] >> 8) & 0xFF; 673 eaddr[1] = (ea[1] >> 0) & 0xFF; 674 eaddr[2] = (ea[0] >> 24) & 0xFF; 675 eaddr[3] = (ea[0] >> 16) & 0xFF; 676 eaddr[4] = (ea[0] >> 8) & 0xFF; 677 eaddr[5] = (ea[0] >> 0) & 0xFF; 678 } 679 680 static void 681 age_phy_reset(struct age_softc *sc) 682 { 683 /* Reset PHY. */ 684 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 685 DELAY(1000); 686 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 687 DELAY(1000); 688 } 689 690 static int 691 age_dma_alloc(struct age_softc *sc) 692 { 693 struct age_txdesc *txd; 694 struct age_rxdesc *rxd; 695 int nsegs, error, i; 696 697 /* 698 * Create DMA stuffs for TX ring 699 */ 700 error = bus_dmamap_create(sc->sc_dmat, AGE_TX_RING_SZ, 1, 701 AGE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_tx_ring_map); 702 if (error) 703 return ENOBUFS; 704 705 /* Allocate DMA'able memory for TX ring */ 706 error = bus_dmamem_alloc(sc->sc_dmat, AGE_TX_RING_SZ, 707 PAGE_SIZE, 0, &sc->age_rdata.age_tx_ring_seg, 1, 708 &nsegs, BUS_DMA_WAITOK); 709 if (error) { 710 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 711 device_xname(sc->sc_dev)); 712 return error; 713 } 714 715 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_tx_ring_seg, 716 nsegs, AGE_TX_RING_SZ, (void **)&sc->age_rdata.age_tx_ring, 717 BUS_DMA_NOWAIT); 718 if (error) 719 return ENOBUFS; 720 721 memset(sc->age_rdata.age_tx_ring, 0, AGE_TX_RING_SZ); 722 723 /* Load the DMA map for Tx ring. */ 724 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 725 sc->age_rdata.age_tx_ring, AGE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 726 if (error) { 727 printf("%s: could not load DMA'able memory for Tx ring.\n", 728 device_xname(sc->sc_dev)); 729 bus_dmamem_free(sc->sc_dmat, 730 (bus_dma_segment_t *)&sc->age_rdata.age_tx_ring, 1); 731 return error; 732 } 733 734 sc->age_rdata.age_tx_ring_paddr = 735 sc->age_cdata.age_tx_ring_map->dm_segs[0].ds_addr; 736 737 /* 738 * Create DMA stuffs for RX ring 739 */ 740 error = bus_dmamap_create(sc->sc_dmat, AGE_RX_RING_SZ, 1, 741 AGE_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_ring_map); 742 if (error) 743 return ENOBUFS; 744 745 /* Allocate DMA'able memory for RX ring */ 746 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RX_RING_SZ, 747 PAGE_SIZE, 0, &sc->age_rdata.age_rx_ring_seg, 1, 748 &nsegs, BUS_DMA_WAITOK); 749 if (error) { 750 printf("%s: could not allocate DMA'able memory for Rx ring.\n", 751 device_xname(sc->sc_dev)); 752 return error; 753 } 754 755 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rx_ring_seg, 756 nsegs, AGE_RX_RING_SZ, (void **)&sc->age_rdata.age_rx_ring, 757 BUS_DMA_NOWAIT); 758 if (error) 759 return ENOBUFS; 760 761 memset(sc->age_rdata.age_rx_ring, 0, AGE_RX_RING_SZ); 762 763 /* Load the DMA map for Rx ring. */ 764 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 765 sc->age_rdata.age_rx_ring, AGE_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 766 if (error) { 767 printf("%s: could not load DMA'able memory for Rx ring.\n", 768 device_xname(sc->sc_dev)); 769 bus_dmamem_free(sc->sc_dmat, 770 (bus_dma_segment_t *)sc->age_rdata.age_rx_ring, 1); 771 return error; 772 } 773 774 sc->age_rdata.age_rx_ring_paddr = 775 sc->age_cdata.age_rx_ring_map->dm_segs[0].ds_addr; 776 777 /* 778 * Create DMA stuffs for RX return ring 779 */ 780 error = bus_dmamap_create(sc->sc_dmat, AGE_RR_RING_SZ, 1, 781 AGE_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rr_ring_map); 782 if (error) 783 return ENOBUFS; 784 785 /* Allocate DMA'able memory for RX return ring */ 786 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RR_RING_SZ, 787 PAGE_SIZE, 0, &sc->age_rdata.age_rr_ring_seg, 1, 788 &nsegs, BUS_DMA_WAITOK); 789 if (error) { 790 printf("%s: could not allocate DMA'able memory for Rx " 791 "return ring.\n", device_xname(sc->sc_dev)); 792 return error; 793 } 794 795 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rr_ring_seg, 796 nsegs, AGE_RR_RING_SZ, (void **)&sc->age_rdata.age_rr_ring, 797 BUS_DMA_NOWAIT); 798 if (error) 799 return ENOBUFS; 800 801 memset(sc->age_rdata.age_rr_ring, 0, AGE_RR_RING_SZ); 802 803 /* Load the DMA map for Rx return ring. */ 804 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 805 sc->age_rdata.age_rr_ring, AGE_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 806 if (error) { 807 printf("%s: could not load DMA'able memory for Rx return ring." 808 "\n", device_xname(sc->sc_dev)); 809 bus_dmamem_free(sc->sc_dmat, 810 (bus_dma_segment_t *)&sc->age_rdata.age_rr_ring, 1); 811 return error; 812 } 813 814 sc->age_rdata.age_rr_ring_paddr = 815 sc->age_cdata.age_rr_ring_map->dm_segs[0].ds_addr; 816 817 /* 818 * Create DMA stuffs for CMB block 819 */ 820 error = bus_dmamap_create(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 1, 821 AGE_CMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 822 &sc->age_cdata.age_cmb_block_map); 823 if (error) 824 return ENOBUFS; 825 826 /* Allocate DMA'able memory for CMB block */ 827 error = bus_dmamem_alloc(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 828 PAGE_SIZE, 0, &sc->age_rdata.age_cmb_block_seg, 1, 829 &nsegs, BUS_DMA_WAITOK); 830 if (error) { 831 printf("%s: could not allocate DMA'able memory for " 832 "CMB block\n", device_xname(sc->sc_dev)); 833 return error; 834 } 835 836 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_cmb_block_seg, 837 nsegs, AGE_CMB_BLOCK_SZ, (void **)&sc->age_rdata.age_cmb_block, 838 BUS_DMA_NOWAIT); 839 if (error) 840 return ENOBUFS; 841 842 memset(sc->age_rdata.age_cmb_block, 0, AGE_CMB_BLOCK_SZ); 843 844 /* Load the DMA map for CMB block. */ 845 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 846 sc->age_rdata.age_cmb_block, AGE_CMB_BLOCK_SZ, NULL, 847 BUS_DMA_WAITOK); 848 if (error) { 849 printf("%s: could not load DMA'able memory for CMB block\n", 850 device_xname(sc->sc_dev)); 851 bus_dmamem_free(sc->sc_dmat, 852 (bus_dma_segment_t *)&sc->age_rdata.age_cmb_block, 1); 853 return error; 854 } 855 856 sc->age_rdata.age_cmb_block_paddr = 857 sc->age_cdata.age_cmb_block_map->dm_segs[0].ds_addr; 858 859 /* 860 * Create DMA stuffs for SMB block 861 */ 862 error = bus_dmamap_create(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 1, 863 AGE_SMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 864 &sc->age_cdata.age_smb_block_map); 865 if (error) 866 return ENOBUFS; 867 868 /* Allocate DMA'able memory for SMB block */ 869 error = bus_dmamem_alloc(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 870 PAGE_SIZE, 0, &sc->age_rdata.age_smb_block_seg, 1, 871 &nsegs, BUS_DMA_WAITOK); 872 if (error) { 873 printf("%s: could not allocate DMA'able memory for " 874 "SMB block\n", device_xname(sc->sc_dev)); 875 return error; 876 } 877 878 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_smb_block_seg, 879 nsegs, AGE_SMB_BLOCK_SZ, (void **)&sc->age_rdata.age_smb_block, 880 BUS_DMA_NOWAIT); 881 if (error) 882 return ENOBUFS; 883 884 memset(sc->age_rdata.age_smb_block, 0, AGE_SMB_BLOCK_SZ); 885 886 /* Load the DMA map for SMB block */ 887 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 888 sc->age_rdata.age_smb_block, AGE_SMB_BLOCK_SZ, NULL, 889 BUS_DMA_WAITOK); 890 if (error) { 891 printf("%s: could not load DMA'able memory for SMB block\n", 892 device_xname(sc->sc_dev)); 893 bus_dmamem_free(sc->sc_dmat, 894 (bus_dma_segment_t *)&sc->age_rdata.age_smb_block, 1); 895 return error; 896 } 897 898 sc->age_rdata.age_smb_block_paddr = 899 sc->age_cdata.age_smb_block_map->dm_segs[0].ds_addr; 900 901 /* Create DMA maps for Tx buffers. */ 902 for (i = 0; i < AGE_TX_RING_CNT; i++) { 903 txd = &sc->age_cdata.age_txdesc[i]; 904 txd->tx_m = NULL; 905 txd->tx_dmamap = NULL; 906 error = bus_dmamap_create(sc->sc_dmat, AGE_TSO_MAXSIZE, 907 AGE_MAXTXSEGS, AGE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 908 &txd->tx_dmamap); 909 if (error) { 910 printf("%s: could not create Tx dmamap.\n", 911 device_xname(sc->sc_dev)); 912 return error; 913 } 914 } 915 916 /* Create DMA maps for Rx buffers. */ 917 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 918 BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_sparemap); 919 if (error) { 920 printf("%s: could not create spare Rx dmamap.\n", 921 device_xname(sc->sc_dev)); 922 return error; 923 } 924 for (i = 0; i < AGE_RX_RING_CNT; i++) { 925 rxd = &sc->age_cdata.age_rxdesc[i]; 926 rxd->rx_m = NULL; 927 rxd->rx_dmamap = NULL; 928 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 929 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 930 if (error) { 931 printf("%s: could not create Rx dmamap.\n", 932 device_xname(sc->sc_dev)); 933 return error; 934 } 935 } 936 937 return 0; 938 } 939 940 static void 941 age_dma_free(struct age_softc *sc) 942 { 943 struct age_txdesc *txd; 944 struct age_rxdesc *rxd; 945 int i; 946 947 /* Tx buffers */ 948 for (i = 0; i < AGE_TX_RING_CNT; i++) { 949 txd = &sc->age_cdata.age_txdesc[i]; 950 if (txd->tx_dmamap != NULL) { 951 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 952 txd->tx_dmamap = NULL; 953 } 954 } 955 /* Rx buffers */ 956 for (i = 0; i < AGE_RX_RING_CNT; i++) { 957 rxd = &sc->age_cdata.age_rxdesc[i]; 958 if (rxd->rx_dmamap != NULL) { 959 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 960 rxd->rx_dmamap = NULL; 961 } 962 } 963 if (sc->age_cdata.age_rx_sparemap != NULL) { 964 bus_dmamap_destroy(sc->sc_dmat, sc->age_cdata.age_rx_sparemap); 965 sc->age_cdata.age_rx_sparemap = NULL; 966 } 967 968 /* Tx ring. */ 969 if (sc->age_cdata.age_tx_ring_map != NULL) 970 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_tx_ring_map); 971 if (sc->age_cdata.age_tx_ring_map != NULL && 972 sc->age_rdata.age_tx_ring != NULL) 973 bus_dmamem_free(sc->sc_dmat, 974 (bus_dma_segment_t *)sc->age_rdata.age_tx_ring, 1); 975 sc->age_rdata.age_tx_ring = NULL; 976 sc->age_cdata.age_tx_ring_map = NULL; 977 978 /* Rx ring. */ 979 if (sc->age_cdata.age_rx_ring_map != NULL) 980 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rx_ring_map); 981 if (sc->age_cdata.age_rx_ring_map != NULL && 982 sc->age_rdata.age_rx_ring != NULL) 983 bus_dmamem_free(sc->sc_dmat, 984 (bus_dma_segment_t *)sc->age_rdata.age_rx_ring, 1); 985 sc->age_rdata.age_rx_ring = NULL; 986 sc->age_cdata.age_rx_ring_map = NULL; 987 988 /* Rx return ring. */ 989 if (sc->age_cdata.age_rr_ring_map != NULL) 990 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rr_ring_map); 991 if (sc->age_cdata.age_rr_ring_map != NULL && 992 sc->age_rdata.age_rr_ring != NULL) 993 bus_dmamem_free(sc->sc_dmat, 994 (bus_dma_segment_t *)sc->age_rdata.age_rr_ring, 1); 995 sc->age_rdata.age_rr_ring = NULL; 996 sc->age_cdata.age_rr_ring_map = NULL; 997 998 /* CMB block */ 999 if (sc->age_cdata.age_cmb_block_map != NULL) 1000 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_cmb_block_map); 1001 if (sc->age_cdata.age_cmb_block_map != NULL && 1002 sc->age_rdata.age_cmb_block != NULL) 1003 bus_dmamem_free(sc->sc_dmat, 1004 (bus_dma_segment_t *)sc->age_rdata.age_cmb_block, 1); 1005 sc->age_rdata.age_cmb_block = NULL; 1006 sc->age_cdata.age_cmb_block_map = NULL; 1007 1008 /* SMB block */ 1009 if (sc->age_cdata.age_smb_block_map != NULL) 1010 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_smb_block_map); 1011 if (sc->age_cdata.age_smb_block_map != NULL && 1012 sc->age_rdata.age_smb_block != NULL) 1013 bus_dmamem_free(sc->sc_dmat, 1014 (bus_dma_segment_t *)sc->age_rdata.age_smb_block, 1); 1015 } 1016 1017 static void 1018 age_start(struct ifnet *ifp) 1019 { 1020 struct age_softc *sc = ifp->if_softc; 1021 struct mbuf *m_head; 1022 int enq; 1023 1024 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1025 return; 1026 1027 enq = 0; 1028 for (;;) { 1029 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1030 if (m_head == NULL) 1031 break; 1032 1033 /* 1034 * Pack the data into the transmit ring. If we 1035 * don't have room, set the OACTIVE flag and wait 1036 * for the NIC to drain the ring. 1037 */ 1038 if (age_encap(sc, &m_head)) { 1039 if (m_head == NULL) 1040 break; 1041 ifp->if_flags |= IFF_OACTIVE; 1042 break; 1043 } 1044 enq = 1; 1045 1046 #if NBPFILTER > 0 1047 /* 1048 * If there's a BPF listener, bounce a copy of this frame 1049 * to him. 1050 */ 1051 if (ifp->if_bpf != NULL) 1052 bpf_mtap(ifp->if_bpf, m_head); 1053 #endif 1054 } 1055 1056 if (enq) { 1057 /* Update mbox. */ 1058 AGE_COMMIT_MBOX(sc); 1059 /* Set a timeout in case the chip goes out to lunch. */ 1060 ifp->if_timer = AGE_TX_TIMEOUT; 1061 } 1062 } 1063 1064 static void 1065 age_watchdog(struct ifnet *ifp) 1066 { 1067 struct age_softc *sc = ifp->if_softc; 1068 1069 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1070 printf("%s: watchdog timeout (missed link)\n", 1071 device_xname(sc->sc_dev)); 1072 ifp->if_oerrors++; 1073 age_init(ifp); 1074 return; 1075 } 1076 1077 if (sc->age_cdata.age_tx_cnt == 0) { 1078 printf("%s: watchdog timeout (missed Tx interrupts) " 1079 "-- recovering\n", device_xname(sc->sc_dev)); 1080 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1081 age_start(ifp); 1082 return; 1083 } 1084 1085 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1086 ifp->if_oerrors++; 1087 age_init(ifp); 1088 1089 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1090 age_start(ifp); 1091 } 1092 1093 static int 1094 age_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1095 { 1096 struct age_softc *sc = ifp->if_softc; 1097 struct mii_data *mii = &sc->sc_miibus; 1098 struct ifreq *ifr = (struct ifreq *)data; 1099 int s, error = 0; 1100 1101 s = splnet(); 1102 1103 switch (cmd) { 1104 case SIOCSIFMEDIA: 1105 case SIOCGIFMEDIA: 1106 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1107 break; 1108 default: 1109 error = ether_ioctl(ifp, cmd, data); 1110 if (error == ENETRESET) { 1111 if (ifp->if_flags & IFF_RUNNING) 1112 age_rxfilter(sc); 1113 error = 0; 1114 } 1115 break; 1116 } 1117 1118 splx(s); 1119 return error; 1120 } 1121 1122 static void 1123 age_mac_config(struct age_softc *sc) 1124 { 1125 struct mii_data *mii; 1126 uint32_t reg; 1127 1128 mii = &sc->sc_miibus; 1129 1130 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1131 reg &= ~MAC_CFG_FULL_DUPLEX; 1132 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1133 reg &= ~MAC_CFG_SPEED_MASK; 1134 1135 /* Reprogram MAC with resolved speed/duplex. */ 1136 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1137 case IFM_10_T: 1138 case IFM_100_TX: 1139 reg |= MAC_CFG_SPEED_10_100; 1140 break; 1141 case IFM_1000_T: 1142 reg |= MAC_CFG_SPEED_1000; 1143 break; 1144 } 1145 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1146 reg |= MAC_CFG_FULL_DUPLEX; 1147 #ifdef notyet 1148 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1149 reg |= MAC_CFG_TX_FC; 1150 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1151 reg |= MAC_CFG_RX_FC; 1152 #endif 1153 } 1154 1155 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1156 } 1157 1158 static bool 1159 age_resume(device_t dv PMF_FN_ARGS) 1160 { 1161 struct age_softc *sc = device_private(dv); 1162 uint16_t cmd; 1163 1164 /* 1165 * Clear INTx emulation disable for hardware that 1166 * is set in resume event. From Linux. 1167 */ 1168 cmd = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 1169 if ((cmd & 0x0400) != 0) { 1170 cmd &= ~0x0400; 1171 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 1172 PCI_COMMAND_STATUS_REG, cmd); 1173 } 1174 1175 return true; 1176 } 1177 1178 static int 1179 age_encap(struct age_softc *sc, struct mbuf **m_head) 1180 { 1181 struct age_txdesc *txd, *txd_last; 1182 struct tx_desc *desc; 1183 struct mbuf *m; 1184 bus_dmamap_t map; 1185 uint32_t cflags, poff, vtag; 1186 int error, i, nsegs, prod; 1187 struct m_tag *mtag; 1188 1189 m = *m_head; 1190 cflags = vtag = 0; 1191 poff = 0; 1192 1193 prod = sc->age_cdata.age_tx_prod; 1194 txd = &sc->age_cdata.age_txdesc[prod]; 1195 txd_last = txd; 1196 map = txd->tx_dmamap; 1197 1198 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1199 1200 if (error != 0) { 1201 bus_dmamap_unload(sc->sc_dmat, map); 1202 error = EFBIG; 1203 } 1204 if (error == EFBIG) { 1205 error = 0; 1206 1207 MGETHDR(m, M_DONTWAIT, MT_DATA); 1208 if (m == NULL) { 1209 printf("%s: can't defrag TX mbuf\n", 1210 device_xname(sc->sc_dev)); 1211 m_freem(*m_head); 1212 *m_head = NULL; 1213 return ENOBUFS; 1214 } 1215 1216 M_COPY_PKTHDR(m, *m_head); 1217 if ((*m_head)->m_pkthdr.len > MHLEN) { 1218 MCLGET(m, M_DONTWAIT); 1219 if (!(m->m_flags & M_EXT)) { 1220 m_freem(*m_head); 1221 m_freem(m); 1222 *m_head = NULL; 1223 return ENOBUFS; 1224 } 1225 } 1226 m_copydata(*m_head, 0, (*m_head)->m_pkthdr.len, 1227 mtod(m, void *)); 1228 m_freem(*m_head); 1229 m->m_len = m->m_pkthdr.len; 1230 *m_head = m; 1231 1232 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1233 BUS_DMA_NOWAIT); 1234 1235 if (error != 0) { 1236 printf("%s: could not load defragged TX mbuf\n", 1237 device_xname(sc->sc_dev)); 1238 if (!error) { 1239 bus_dmamap_unload(sc->sc_dmat, map); 1240 error = EFBIG; 1241 } 1242 m_freem(*m_head); 1243 *m_head = NULL; 1244 return error; 1245 } 1246 } else if (error) { 1247 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 1248 return error; 1249 } 1250 1251 nsegs = map->dm_nsegs; 1252 1253 if (nsegs == 0) { 1254 m_freem(*m_head); 1255 *m_head = NULL; 1256 return EIO; 1257 } 1258 1259 /* Check descriptor overrun. */ 1260 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1261 bus_dmamap_unload(sc->sc_dmat, map); 1262 return ENOBUFS; 1263 } 1264 1265 m = *m_head; 1266 /* Configure Tx IP/TCP/UDP checksum offload. */ 1267 if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1268 cflags |= AGE_TD_CSUM; 1269 if ((m->m_pkthdr.csum_flags & M_CSUM_TCPv4) != 0) 1270 cflags |= AGE_TD_TCPCSUM; 1271 if ((m->m_pkthdr.csum_flags & M_CSUM_UDPv4) != 0) 1272 cflags |= AGE_TD_UDPCSUM; 1273 /* Set checksum start offset. */ 1274 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1275 } 1276 1277 #if NVLAN > 0 1278 /* Configure VLAN hardware tag insertion. */ 1279 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m))) { 1280 vtag = AGE_TX_VLAN_TAG(htons(VLAN_TAG_VALUE(mtag))); 1281 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1282 cflags |= AGE_TD_INSERT_VLAN_TAG; 1283 } 1284 #endif 1285 1286 desc = NULL; 1287 for (i = 0; i < nsegs; i++) { 1288 desc = &sc->age_rdata.age_tx_ring[prod]; 1289 desc->addr = htole64(map->dm_segs[i].ds_addr); 1290 desc->len = 1291 htole32(AGE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 1292 desc->flags = htole32(cflags); 1293 sc->age_cdata.age_tx_cnt++; 1294 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1295 } 1296 1297 /* Update producer index. */ 1298 sc->age_cdata.age_tx_prod = prod; 1299 1300 /* Set EOP on the last descriptor. */ 1301 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1302 desc = &sc->age_rdata.age_tx_ring[prod]; 1303 desc->flags |= htole32(AGE_TD_EOP); 1304 1305 /* Swap dmamap of the first and the last. */ 1306 txd = &sc->age_cdata.age_txdesc[prod]; 1307 map = txd_last->tx_dmamap; 1308 txd_last->tx_dmamap = txd->tx_dmamap; 1309 txd->tx_dmamap = map; 1310 txd->tx_m = m; 1311 1312 /* Sync descriptors. */ 1313 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1314 BUS_DMASYNC_PREWRITE); 1315 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1316 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1317 1318 return 0; 1319 } 1320 1321 static void 1322 age_txintr(struct age_softc *sc, int tpd_cons) 1323 { 1324 struct ifnet *ifp = &sc->sc_ec.ec_if; 1325 struct age_txdesc *txd; 1326 int cons, prog; 1327 1328 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1329 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1330 1331 /* 1332 * Go through our Tx list and free mbufs for those 1333 * frames which have been transmitted. 1334 */ 1335 cons = sc->age_cdata.age_tx_cons; 1336 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 1337 if (sc->age_cdata.age_tx_cnt <= 0) 1338 break; 1339 prog++; 1340 ifp->if_flags &= ~IFF_OACTIVE; 1341 sc->age_cdata.age_tx_cnt--; 1342 txd = &sc->age_cdata.age_txdesc[cons]; 1343 /* 1344 * Clear Tx descriptors, it's not required but would 1345 * help debugging in case of Tx issues. 1346 */ 1347 txd->tx_desc->addr = 0; 1348 txd->tx_desc->len = 0; 1349 txd->tx_desc->flags = 0; 1350 1351 if (txd->tx_m == NULL) 1352 continue; 1353 /* Reclaim transmitted mbufs. */ 1354 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1355 m_freem(txd->tx_m); 1356 txd->tx_m = NULL; 1357 } 1358 1359 if (prog > 0) { 1360 sc->age_cdata.age_tx_cons = cons; 1361 1362 /* 1363 * Unarm watchdog timer only when there are no pending 1364 * Tx descriptors in queue. 1365 */ 1366 if (sc->age_cdata.age_tx_cnt == 0) 1367 ifp->if_timer = 0; 1368 1369 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1370 sc->age_cdata.age_tx_ring_map->dm_mapsize, 1371 BUS_DMASYNC_PREWRITE); 1372 } 1373 } 1374 1375 /* Receive a frame. */ 1376 static void 1377 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 1378 { 1379 struct ifnet *ifp = &sc->sc_ec.ec_if; 1380 struct age_rxdesc *rxd; 1381 struct rx_desc *desc; 1382 struct mbuf *mp, *m; 1383 uint32_t status, index, vtag; 1384 int count, nsegs, pktlen; 1385 int rx_cons; 1386 1387 status = le32toh(rxrd->flags); 1388 index = le32toh(rxrd->index); 1389 rx_cons = AGE_RX_CONS(index); 1390 nsegs = AGE_RX_NSEGS(index); 1391 1392 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 1393 if ((status & AGE_RRD_ERROR) != 0 && 1394 (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 1395 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) { 1396 /* 1397 * We want to pass the following frames to upper 1398 * layer regardless of error status of Rx return 1399 * ring. 1400 * 1401 * o IP/TCP/UDP checksum is bad. 1402 * o frame length and protocol specific length 1403 * does not match. 1404 */ 1405 sc->age_cdata.age_rx_cons += nsegs; 1406 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1407 return; 1408 } 1409 1410 pktlen = 0; 1411 for (count = 0; count < nsegs; count++, 1412 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 1413 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 1414 mp = rxd->rx_m; 1415 desc = rxd->rx_desc; 1416 /* Add a new receive buffer to the ring. */ 1417 if (age_newbuf(sc, rxd, 0) != 0) { 1418 ifp->if_iqdrops++; 1419 /* Reuse Rx buffers. */ 1420 if (sc->age_cdata.age_rxhead != NULL) { 1421 m_freem(sc->age_cdata.age_rxhead); 1422 AGE_RXCHAIN_RESET(sc); 1423 } 1424 break; 1425 } 1426 1427 /* The length of the first mbuf is computed last. */ 1428 if (count != 0) { 1429 mp->m_len = AGE_RX_BYTES(le32toh(desc->len)); 1430 pktlen += mp->m_len; 1431 } 1432 1433 /* Chain received mbufs. */ 1434 if (sc->age_cdata.age_rxhead == NULL) { 1435 sc->age_cdata.age_rxhead = mp; 1436 sc->age_cdata.age_rxtail = mp; 1437 } else { 1438 mp->m_flags &= ~M_PKTHDR; 1439 sc->age_cdata.age_rxprev_tail = 1440 sc->age_cdata.age_rxtail; 1441 sc->age_cdata.age_rxtail->m_next = mp; 1442 sc->age_cdata.age_rxtail = mp; 1443 } 1444 1445 if (count == nsegs - 1) { 1446 /* 1447 * It seems that L1 controller has no way 1448 * to tell hardware to strip CRC bytes. 1449 */ 1450 sc->age_cdata.age_rxlen -= ETHER_CRC_LEN; 1451 if (nsegs > 1) { 1452 /* Remove the CRC bytes in chained mbufs. */ 1453 pktlen -= ETHER_CRC_LEN; 1454 if (mp->m_len <= ETHER_CRC_LEN) { 1455 sc->age_cdata.age_rxtail = 1456 sc->age_cdata.age_rxprev_tail; 1457 sc->age_cdata.age_rxtail->m_len -= 1458 (ETHER_CRC_LEN - mp->m_len); 1459 sc->age_cdata.age_rxtail->m_next = NULL; 1460 m_freem(mp); 1461 } else { 1462 mp->m_len -= ETHER_CRC_LEN; 1463 } 1464 } 1465 1466 m = sc->age_cdata.age_rxhead; 1467 m->m_flags |= M_PKTHDR; 1468 m->m_pkthdr.rcvif = ifp; 1469 m->m_pkthdr.len = sc->age_cdata.age_rxlen; 1470 /* Set the first mbuf length. */ 1471 m->m_len = sc->age_cdata.age_rxlen - pktlen; 1472 1473 /* 1474 * Set checksum information. 1475 * It seems that L1 controller can compute partial 1476 * checksum. The partial checksum value can be used 1477 * to accelerate checksum computation for fragmented 1478 * TCP/UDP packets. Upper network stack already 1479 * takes advantage of the partial checksum value in 1480 * IP reassembly stage. But I'm not sure the 1481 * correctness of the partial hardware checksum 1482 * assistance due to lack of data sheet. If it is 1483 * proven to work on L1 I'll enable it. 1484 */ 1485 if (status & AGE_RRD_IPV4) { 1486 if (status & AGE_RRD_IPCSUM_NOK) 1487 m->m_pkthdr.csum_flags |= 1488 M_CSUM_IPv4_BAD; 1489 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 1490 (status & AGE_RRD_TCP_UDPCSUM_NOK)) { 1491 m->m_pkthdr.csum_flags |= 1492 M_CSUM_TCP_UDP_BAD; 1493 } 1494 /* 1495 * Don't mark bad checksum for TCP/UDP frames 1496 * as fragmented frames may always have set 1497 * bad checksummed bit of descriptor status. 1498 */ 1499 } 1500 #if NVLAN > 0 1501 /* Check for VLAN tagged frames. */ 1502 if (status & AGE_RRD_VLAN) { 1503 vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 1504 VLAN_INPUT_TAG(ifp, m, AGE_RX_VLAN_TAG(vtag), 1505 continue); 1506 } 1507 #endif 1508 1509 #if NBPFILTER > 0 1510 if (ifp->if_bpf) 1511 bpf_mtap(ifp->if_bpf, m); 1512 #endif 1513 /* Pass it on. */ 1514 ether_input(ifp, m); 1515 1516 /* Reset mbuf chains. */ 1517 AGE_RXCHAIN_RESET(sc); 1518 } 1519 } 1520 1521 if (count != nsegs) { 1522 sc->age_cdata.age_rx_cons += nsegs; 1523 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1524 } else 1525 sc->age_cdata.age_rx_cons = rx_cons; 1526 } 1527 1528 static void 1529 age_rxintr(struct age_softc *sc, int rr_prod) 1530 { 1531 struct rx_rdesc *rxrd; 1532 int rr_cons, nsegs, pktlen, prog; 1533 1534 rr_cons = sc->age_cdata.age_rr_cons; 1535 if (rr_cons == rr_prod) 1536 return; 1537 1538 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1539 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1540 BUS_DMASYNC_POSTREAD); 1541 1542 for (prog = 0; rr_cons != rr_prod; prog++) { 1543 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 1544 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 1545 if (nsegs == 0) 1546 break; 1547 /* 1548 * Check number of segments against received bytes 1549 * Non-matching value would indicate that hardware 1550 * is still trying to update Rx return descriptors. 1551 * I'm not sure whether this check is really needed. 1552 */ 1553 pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 1554 if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) / 1555 (MCLBYTES - ETHER_ALIGN))) 1556 break; 1557 1558 /* Received a frame. */ 1559 age_rxeof(sc, rxrd); 1560 1561 /* Clear return ring. */ 1562 rxrd->index = 0; 1563 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 1564 } 1565 1566 if (prog > 0) { 1567 /* Update the consumer index. */ 1568 sc->age_cdata.age_rr_cons = rr_cons; 1569 1570 /* Sync descriptors. */ 1571 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1572 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1573 BUS_DMASYNC_PREWRITE); 1574 1575 /* Notify hardware availability of new Rx buffers. */ 1576 AGE_COMMIT_MBOX(sc); 1577 } 1578 } 1579 1580 static void 1581 age_tick(void *xsc) 1582 { 1583 struct age_softc *sc = xsc; 1584 struct mii_data *mii = &sc->sc_miibus; 1585 int s; 1586 1587 s = splnet(); 1588 mii_tick(mii); 1589 splx(s); 1590 1591 callout_schedule(&sc->sc_tick_ch, hz); 1592 } 1593 1594 static void 1595 age_reset(struct age_softc *sc) 1596 { 1597 uint32_t reg; 1598 int i; 1599 1600 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 1601 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1602 DELAY(1); 1603 if ((CSR_READ_4(sc, AGE_MASTER_CFG) & MASTER_RESET) == 0) 1604 break; 1605 } 1606 if (i == 0) 1607 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 1608 1609 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1610 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1611 break; 1612 DELAY(10); 1613 } 1614 1615 if (i == 0) 1616 printf("%s: reset timeout(0x%08x)!\n", device_xname(sc->sc_dev), 1617 reg); 1618 1619 /* Initialize PCIe module. From Linux. */ 1620 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1621 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1622 } 1623 1624 static int 1625 age_init(struct ifnet *ifp) 1626 { 1627 struct age_softc *sc = ifp->if_softc; 1628 struct mii_data *mii; 1629 uint8_t eaddr[ETHER_ADDR_LEN]; 1630 bus_addr_t paddr; 1631 uint32_t reg, fsize; 1632 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 1633 int error; 1634 1635 /* 1636 * Cancel any pending I/O. 1637 */ 1638 age_stop(sc); 1639 1640 /* 1641 * Reset the chip to a known state. 1642 */ 1643 age_reset(sc); 1644 1645 /* Initialize descriptors. */ 1646 error = age_init_rx_ring(sc); 1647 if (error != 0) { 1648 printf("%s: no memory for Rx buffers.\n", device_xname(sc->sc_dev)); 1649 age_stop(sc); 1650 return error; 1651 } 1652 age_init_rr_ring(sc); 1653 age_init_tx_ring(sc); 1654 age_init_cmb_block(sc); 1655 age_init_smb_block(sc); 1656 1657 /* Reprogram the station address. */ 1658 memcpy(eaddr, CLLADDR(ifp->if_sadl), sizeof(eaddr)); 1659 CSR_WRITE_4(sc, AGE_PAR0, 1660 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1661 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 1662 1663 /* Set descriptor base addresses. */ 1664 paddr = sc->age_rdata.age_tx_ring_paddr; 1665 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 1666 paddr = sc->age_rdata.age_rx_ring_paddr; 1667 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 1668 paddr = sc->age_rdata.age_rr_ring_paddr; 1669 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 1670 paddr = sc->age_rdata.age_tx_ring_paddr; 1671 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 1672 paddr = sc->age_rdata.age_cmb_block_paddr; 1673 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1674 paddr = sc->age_rdata.age_smb_block_paddr; 1675 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1676 1677 /* Set Rx/Rx return descriptor counter. */ 1678 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 1679 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 1680 DESC_RRD_CNT_MASK) | 1681 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 1682 1683 /* Set Tx descriptor counter. */ 1684 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 1685 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 1686 1687 /* Tell hardware that we're ready to load descriptors. */ 1688 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 1689 1690 /* 1691 * Initialize mailbox register. 1692 * Updated producer/consumer index information is exchanged 1693 * through this mailbox register. However Tx producer and 1694 * Rx return consumer/Rx producer are all shared such that 1695 * it's hard to separate code path between Tx and Rx without 1696 * locking. If L1 hardware have a separate mail box register 1697 * for Tx and Rx consumer/producer management we could have 1698 * indepent Tx/Rx handler which in turn Rx handler could have 1699 * been run without any locking. 1700 */ 1701 AGE_COMMIT_MBOX(sc); 1702 1703 /* Configure IPG/IFG parameters. */ 1704 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 1705 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 1706 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1707 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1708 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 1709 1710 /* Set parameters for half-duplex media. */ 1711 CSR_WRITE_4(sc, AGE_HDPX_CFG, 1712 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1713 HDPX_CFG_LCOL_MASK) | 1714 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1715 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1716 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1717 HDPX_CFG_ABEBT_MASK) | 1718 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1719 HDPX_CFG_JAMIPG_MASK)); 1720 1721 /* Configure interrupt moderation timer. */ 1722 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 1723 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 1724 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 1725 reg &= ~MASTER_MTIMER_ENB; 1726 if (AGE_USECS(sc->age_int_mod) == 0) 1727 reg &= ~MASTER_ITIMER_ENB; 1728 else 1729 reg |= MASTER_ITIMER_ENB; 1730 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 1731 if (agedebug) 1732 printf("%s: interrupt moderation is %d us.\n", 1733 device_xname(sc->sc_dev), sc->age_int_mod); 1734 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 1735 1736 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 1737 if (ifp->if_mtu < ETHERMTU) 1738 sc->age_max_frame_size = ETHERMTU; 1739 else 1740 sc->age_max_frame_size = ifp->if_mtu; 1741 sc->age_max_frame_size += ETHER_HDR_LEN + 1742 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 1743 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 1744 1745 /* Configure jumbo frame. */ 1746 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 1747 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 1748 (((fsize / sizeof(uint64_t)) << 1749 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 1750 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 1751 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 1752 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 1753 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 1754 1755 /* Configure flow-control parameters. From Linux. */ 1756 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 1757 /* 1758 * Magic workaround for old-L1. 1759 * Don't know which hw revision requires this magic. 1760 */ 1761 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1762 /* 1763 * Another magic workaround for flow-control mode 1764 * change. From Linux. 1765 */ 1766 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1767 } 1768 /* 1769 * TODO 1770 * Should understand pause parameter relationships between FIFO 1771 * size and number of Rx descriptors and Rx return descriptors. 1772 * 1773 * Magic parameters came from Linux. 1774 */ 1775 switch (sc->age_chip_rev) { 1776 case 0x8001: 1777 case 0x9001: 1778 case 0x9002: 1779 case 0x9003: 1780 rxf_hi = AGE_RX_RING_CNT / 16; 1781 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 1782 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 1783 rrd_lo = AGE_RR_RING_CNT / 16; 1784 break; 1785 default: 1786 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 1787 rxf_lo = reg / 16; 1788 if (rxf_lo < 192) 1789 rxf_lo = 192; 1790 rxf_hi = (reg * 7) / 8; 1791 if (rxf_hi < rxf_lo) 1792 rxf_hi = rxf_lo + 16; 1793 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 1794 rrd_lo = reg / 8; 1795 rrd_hi = (reg * 7) / 8; 1796 if (rrd_lo < 2) 1797 rrd_lo = 2; 1798 if (rrd_hi < rrd_lo) 1799 rrd_hi = rrd_lo + 3; 1800 break; 1801 } 1802 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 1803 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 1804 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 1805 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 1806 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 1807 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 1808 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 1809 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 1810 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 1811 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 1812 1813 /* Configure RxQ. */ 1814 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1815 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 1816 RXQ_CFG_RD_BURST_MASK) | 1817 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 1818 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 1819 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 1820 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 1821 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1822 1823 /* Configure TxQ. */ 1824 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1825 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1826 TXQ_CFG_TPD_BURST_MASK) | 1827 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 1828 TXQ_CFG_TX_FIFO_BURST_MASK) | 1829 ((TXQ_CFG_TPD_FETCH_DEFAULT << 1830 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 1831 TXQ_CFG_ENB); 1832 1833 /* Configure DMA parameters. */ 1834 CSR_WRITE_4(sc, AGE_DMA_CFG, 1835 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 1836 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 1837 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 1838 1839 /* Configure CMB DMA write threshold. */ 1840 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 1841 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 1842 CMB_WR_THRESH_RRD_MASK) | 1843 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 1844 CMB_WR_THRESH_TPD_MASK)); 1845 1846 /* Set CMB/SMB timer and enable them. */ 1847 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 1848 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 1849 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 1850 1851 /* Request SMB updates for every seconds. */ 1852 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 1853 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 1854 1855 /* 1856 * Disable all WOL bits as WOL can interfere normal Rx 1857 * operation. 1858 */ 1859 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1860 1861 /* 1862 * Configure Tx/Rx MACs. 1863 * - Auto-padding for short frames. 1864 * - Enable CRC generation. 1865 * Start with full-duplex/1000Mbps media. Actual reconfiguration 1866 * of MAC is followed after link establishment. 1867 */ 1868 CSR_WRITE_4(sc, AGE_MAC_CFG, 1869 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 1870 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 1871 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1872 MAC_CFG_PREAMBLE_MASK)); 1873 1874 /* Set up the receive filter. */ 1875 age_rxfilter(sc); 1876 age_rxvlan(sc); 1877 1878 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1879 reg |= MAC_CFG_RXCSUM_ENB; 1880 1881 /* Ack all pending interrupts and clear it. */ 1882 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 1883 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 1884 1885 /* Finally enable Tx/Rx MAC. */ 1886 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 1887 1888 sc->age_flags &= ~AGE_FLAG_LINK; 1889 1890 /* Switch to the current media. */ 1891 mii = &sc->sc_miibus; 1892 mii_mediachg(mii); 1893 1894 callout_schedule(&sc->sc_tick_ch, hz); 1895 1896 ifp->if_flags |= IFF_RUNNING; 1897 ifp->if_flags &= ~IFF_OACTIVE; 1898 1899 return 0; 1900 } 1901 1902 static void 1903 age_stop(struct age_softc *sc) 1904 { 1905 struct ifnet *ifp = &sc->sc_ec.ec_if; 1906 struct age_txdesc *txd; 1907 struct age_rxdesc *rxd; 1908 uint32_t reg; 1909 int i; 1910 1911 callout_stop(&sc->sc_tick_ch); 1912 1913 /* 1914 * Mark the interface down and cancel the watchdog timer. 1915 */ 1916 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1917 ifp->if_timer = 0; 1918 1919 sc->age_flags &= ~AGE_FLAG_LINK; 1920 1921 /* 1922 * Disable interrupts. 1923 */ 1924 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 1925 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 1926 1927 /* Stop CMB/SMB updates. */ 1928 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 1929 1930 /* Stop Rx/Tx MAC. */ 1931 age_stop_rxmac(sc); 1932 age_stop_txmac(sc); 1933 1934 /* Stop DMA. */ 1935 CSR_WRITE_4(sc, AGE_DMA_CFG, 1936 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 1937 1938 /* Stop TxQ/RxQ. */ 1939 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1940 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 1941 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1942 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 1943 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1944 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1945 break; 1946 DELAY(10); 1947 } 1948 if (i == 0) 1949 printf("%s: stopping Rx/Tx MACs timed out(0x%08x)!\n", 1950 device_xname(sc->sc_dev), reg); 1951 1952 /* Reclaim Rx buffers that have been processed. */ 1953 if (sc->age_cdata.age_rxhead != NULL) 1954 m_freem(sc->age_cdata.age_rxhead); 1955 AGE_RXCHAIN_RESET(sc); 1956 1957 /* 1958 * Free RX and TX mbufs still in the queues. 1959 */ 1960 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1961 rxd = &sc->age_cdata.age_rxdesc[i]; 1962 if (rxd->rx_m != NULL) { 1963 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1964 m_freem(rxd->rx_m); 1965 rxd->rx_m = NULL; 1966 } 1967 } 1968 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1969 txd = &sc->age_cdata.age_txdesc[i]; 1970 if (txd->tx_m != NULL) { 1971 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1972 m_freem(txd->tx_m); 1973 txd->tx_m = NULL; 1974 } 1975 } 1976 } 1977 1978 static void 1979 age_stats_update(struct age_softc *sc) 1980 { 1981 struct ifnet *ifp = &sc->sc_ec.ec_if; 1982 struct age_stats *stat; 1983 struct smb *smb; 1984 1985 stat = &sc->age_stat; 1986 1987 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 1988 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1989 1990 smb = sc->age_rdata.age_smb_block; 1991 if (smb->updated == 0) 1992 return; 1993 1994 /* Rx stats. */ 1995 stat->rx_frames += smb->rx_frames; 1996 stat->rx_bcast_frames += smb->rx_bcast_frames; 1997 stat->rx_mcast_frames += smb->rx_mcast_frames; 1998 stat->rx_pause_frames += smb->rx_pause_frames; 1999 stat->rx_control_frames += smb->rx_control_frames; 2000 stat->rx_crcerrs += smb->rx_crcerrs; 2001 stat->rx_lenerrs += smb->rx_lenerrs; 2002 stat->rx_bytes += smb->rx_bytes; 2003 stat->rx_runts += smb->rx_runts; 2004 stat->rx_fragments += smb->rx_fragments; 2005 stat->rx_pkts_64 += smb->rx_pkts_64; 2006 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2007 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2008 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2009 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2010 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2011 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2012 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2013 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2014 stat->rx_desc_oflows += smb->rx_desc_oflows; 2015 stat->rx_alignerrs += smb->rx_alignerrs; 2016 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2017 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2018 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2019 2020 /* Tx stats. */ 2021 stat->tx_frames += smb->tx_frames; 2022 stat->tx_bcast_frames += smb->tx_bcast_frames; 2023 stat->tx_mcast_frames += smb->tx_mcast_frames; 2024 stat->tx_pause_frames += smb->tx_pause_frames; 2025 stat->tx_excess_defer += smb->tx_excess_defer; 2026 stat->tx_control_frames += smb->tx_control_frames; 2027 stat->tx_deferred += smb->tx_deferred; 2028 stat->tx_bytes += smb->tx_bytes; 2029 stat->tx_pkts_64 += smb->tx_pkts_64; 2030 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2031 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2032 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2033 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2034 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2035 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2036 stat->tx_single_colls += smb->tx_single_colls; 2037 stat->tx_multi_colls += smb->tx_multi_colls; 2038 stat->tx_late_colls += smb->tx_late_colls; 2039 stat->tx_excess_colls += smb->tx_excess_colls; 2040 stat->tx_underrun += smb->tx_underrun; 2041 stat->tx_desc_underrun += smb->tx_desc_underrun; 2042 stat->tx_lenerrs += smb->tx_lenerrs; 2043 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2044 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2045 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2046 2047 /* Update counters in ifnet. */ 2048 ifp->if_opackets += smb->tx_frames; 2049 2050 ifp->if_collisions += smb->tx_single_colls + 2051 smb->tx_multi_colls + smb->tx_late_colls + 2052 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 2053 2054 ifp->if_oerrors += smb->tx_excess_colls + 2055 smb->tx_late_colls + smb->tx_underrun + 2056 smb->tx_pkts_truncated; 2057 2058 ifp->if_ipackets += smb->rx_frames; 2059 2060 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2061 smb->rx_runts + smb->rx_pkts_truncated + 2062 smb->rx_fifo_oflows + smb->rx_desc_oflows + 2063 smb->rx_alignerrs; 2064 2065 /* Update done, clear. */ 2066 smb->updated = 0; 2067 2068 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2069 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2070 } 2071 2072 static void 2073 age_stop_txmac(struct age_softc *sc) 2074 { 2075 uint32_t reg; 2076 int i; 2077 2078 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2079 if ((reg & MAC_CFG_TX_ENB) != 0) { 2080 reg &= ~MAC_CFG_TX_ENB; 2081 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2082 } 2083 /* Stop Tx DMA engine. */ 2084 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2085 if ((reg & DMA_CFG_RD_ENB) != 0) { 2086 reg &= ~DMA_CFG_RD_ENB; 2087 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2088 } 2089 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2090 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2091 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2092 break; 2093 DELAY(10); 2094 } 2095 if (i == 0) 2096 printf("%s: stopping TxMAC timeout!\n", device_xname(sc->sc_dev)); 2097 } 2098 2099 static void 2100 age_stop_rxmac(struct age_softc *sc) 2101 { 2102 uint32_t reg; 2103 int i; 2104 2105 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2106 if ((reg & MAC_CFG_RX_ENB) != 0) { 2107 reg &= ~MAC_CFG_RX_ENB; 2108 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2109 } 2110 /* Stop Rx DMA engine. */ 2111 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2112 if ((reg & DMA_CFG_WR_ENB) != 0) { 2113 reg &= ~DMA_CFG_WR_ENB; 2114 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2115 } 2116 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2117 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2118 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2119 break; 2120 DELAY(10); 2121 } 2122 if (i == 0) 2123 printf("%s: stopping RxMAC timeout!\n", device_xname(sc->sc_dev)); 2124 } 2125 2126 static void 2127 age_init_tx_ring(struct age_softc *sc) 2128 { 2129 struct age_ring_data *rd; 2130 struct age_txdesc *txd; 2131 int i; 2132 2133 sc->age_cdata.age_tx_prod = 0; 2134 sc->age_cdata.age_tx_cons = 0; 2135 sc->age_cdata.age_tx_cnt = 0; 2136 2137 rd = &sc->age_rdata; 2138 memset(rd->age_tx_ring, 0, AGE_TX_RING_SZ); 2139 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2140 txd = &sc->age_cdata.age_txdesc[i]; 2141 txd->tx_desc = &rd->age_tx_ring[i]; 2142 txd->tx_m = NULL; 2143 } 2144 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 2145 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2146 } 2147 2148 static int 2149 age_init_rx_ring(struct age_softc *sc) 2150 { 2151 struct age_ring_data *rd; 2152 struct age_rxdesc *rxd; 2153 int i; 2154 2155 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 2156 rd = &sc->age_rdata; 2157 memset(rd->age_rx_ring, 0, AGE_RX_RING_SZ); 2158 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2159 rxd = &sc->age_cdata.age_rxdesc[i]; 2160 rxd->rx_m = NULL; 2161 rxd->rx_desc = &rd->age_rx_ring[i]; 2162 if (age_newbuf(sc, rxd, 1) != 0) 2163 return ENOBUFS; 2164 } 2165 2166 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 0, 2167 sc->age_cdata.age_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2168 2169 return 0; 2170 } 2171 2172 static void 2173 age_init_rr_ring(struct age_softc *sc) 2174 { 2175 struct age_ring_data *rd; 2176 2177 sc->age_cdata.age_rr_cons = 0; 2178 AGE_RXCHAIN_RESET(sc); 2179 2180 rd = &sc->age_rdata; 2181 memset(rd->age_rr_ring, 0, AGE_RR_RING_SZ); 2182 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 2183 sc->age_cdata.age_rr_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2184 } 2185 2186 static void 2187 age_init_cmb_block(struct age_softc *sc) 2188 { 2189 struct age_ring_data *rd; 2190 2191 rd = &sc->age_rdata; 2192 memset(rd->age_cmb_block, 0, AGE_CMB_BLOCK_SZ); 2193 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 2194 sc->age_cdata.age_cmb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2195 } 2196 2197 static void 2198 age_init_smb_block(struct age_softc *sc) 2199 { 2200 struct age_ring_data *rd; 2201 2202 rd = &sc->age_rdata; 2203 memset(rd->age_smb_block, 0, AGE_SMB_BLOCK_SZ); 2204 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2205 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2206 } 2207 2208 static int 2209 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd, int init) 2210 { 2211 struct rx_desc *desc; 2212 struct mbuf *m; 2213 bus_dmamap_t map; 2214 int error; 2215 2216 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 2217 if (m == NULL) 2218 return ENOBUFS; 2219 MCLGET(m, init ? M_WAITOK : M_DONTWAIT); 2220 if (!(m->m_flags & M_EXT)) { 2221 m_freem(m); 2222 return ENOBUFS; 2223 } 2224 2225 m->m_len = m->m_pkthdr.len = MCLBYTES; 2226 m_adj(m, ETHER_ALIGN); 2227 2228 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2229 sc->age_cdata.age_rx_sparemap, m, BUS_DMA_NOWAIT); 2230 2231 if (error != 0) { 2232 if (!error) { 2233 bus_dmamap_unload(sc->sc_dmat, 2234 sc->age_cdata.age_rx_sparemap); 2235 error = EFBIG; 2236 printf("%s: too many segments?!\n", 2237 device_xname(sc->sc_dev)); 2238 } 2239 m_freem(m); 2240 2241 if (init) 2242 printf("%s: can't load RX mbuf\n", device_xname(sc->sc_dev)); 2243 return error; 2244 } 2245 2246 if (rxd->rx_m != NULL) { 2247 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2248 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2249 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2250 } 2251 map = rxd->rx_dmamap; 2252 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 2253 sc->age_cdata.age_rx_sparemap = map; 2254 rxd->rx_m = m; 2255 2256 desc = rxd->rx_desc; 2257 desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 2258 desc->len = 2259 htole32((rxd->rx_dmamap->dm_segs[0].ds_len & AGE_RD_LEN_MASK) << 2260 AGE_RD_LEN_SHIFT); 2261 2262 return 0; 2263 } 2264 2265 static void 2266 age_rxvlan(struct age_softc *sc) 2267 { 2268 uint32_t reg; 2269 2270 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2271 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2272 if (sc->sc_ec.ec_capabilities & ETHERCAP_VLAN_HWTAGGING) 2273 reg |= MAC_CFG_VLAN_TAG_STRIP; 2274 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2275 } 2276 2277 static void 2278 age_rxfilter(struct age_softc *sc) 2279 { 2280 struct ethercom *ec = &sc->sc_ec; 2281 struct ifnet *ifp = &sc->sc_ec.ec_if; 2282 struct ether_multi *enm; 2283 struct ether_multistep step; 2284 uint32_t crc; 2285 uint32_t mchash[2]; 2286 uint32_t rxcfg; 2287 2288 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 2289 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2290 2291 if (ifp->if_flags & IFF_BROADCAST) 2292 rxcfg |= MAC_CFG_BCAST; 2293 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 2294 if (ifp->if_flags & IFF_PROMISC) 2295 rxcfg |= MAC_CFG_PROMISC; 2296 if (ifp->if_flags & IFF_ALLMULTI) 2297 rxcfg |= MAC_CFG_ALLMULTI; 2298 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF); 2299 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF); 2300 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 2301 return; 2302 } 2303 2304 /* Program new filter. */ 2305 memset(mchash, 0, sizeof(mchash)); 2306 2307 ETHER_FIRST_MULTI(step, ec, enm); 2308 while (enm != NULL) { 2309 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 2310 enm->enm_addrlo), ETHER_ADDR_LEN); 2311 2312 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2313 ETHER_NEXT_MULTI(step, enm); 2314 } 2315 2316 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 2317 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 2318 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 2319 } 2320
Indexes created Mon Sep 29 18:09:42 GMT 2025