if_age.c revision 1.2
1 /* $NetBSD: if_age.c,v 1.2 2009/01/16 21:47:56 cegger Exp $ */ 2 /* $OpenBSD: if_age.c,v 1.1 2009/01/16 05:00:34 kevlo Exp $ */ 3 4 /*- 5 * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: if_age.c,v 1.2 2009/01/16 21:47:56 cegger Exp $"); 35 36 #include "bpfilter.h" 37 #include "vlan.h" 38 39 #include <sys/param.h> 40 #include <sys/proc.h> 41 #include <sys/endian.h> 42 #include <sys/systm.h> 43 #include <sys/types.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/queue.h> 47 #include <sys/kernel.h> 48 #include <sys/device.h> 49 #include <sys/callout.h> 50 #include <sys/socket.h> 51 52 #include <net/if.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #ifdef INET 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/in_var.h> 61 #include <netinet/ip.h> 62 #endif 63 64 #include <net/if_types.h> 65 #include <net/if_vlanvar.h> 66 67 #if NBPFILTER > 0 68 #include <net/bpf.h> 69 #endif 70 71 #include <sys/rnd.h> 72 73 #include <dev/mii/mii.h> 74 #include <dev/mii/miivar.h> 75 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/pcidevs.h> 79 80 #include <dev/pci/if_agereg.h> 81 82 static int age_match(device_t, cfdata_t, void *); 83 static void age_attach(device_t, device_t, void *); 84 static int age_detach(device_t, int); 85 86 static int age_miibus_readreg(device_t, int, int); 87 static void age_miibus_writereg(device_t, int, int, int); 88 static void age_miibus_statchg(device_t); 89 90 static int age_init(struct ifnet *); 91 static int age_ioctl(struct ifnet *, u_long, void *); 92 static void age_start(struct ifnet *); 93 static void age_watchdog(struct ifnet *); 94 static void age_mediastatus(struct ifnet *, struct ifmediareq *); 95 static int age_mediachange(struct ifnet *); 96 97 static int age_intr(void *); 98 static int age_read_vpd_word(struct age_softc *, uint32_t, uint32_t, uint32_t *); 99 static int age_dma_alloc(struct age_softc *); 100 static void age_dma_free(struct age_softc *); 101 static void age_get_macaddr(struct age_softc *, uint8_t[]); 102 static void age_phy_reset(struct age_softc *); 103 104 static int age_encap(struct age_softc *, struct mbuf **); 105 static void age_init_tx_ring(struct age_softc *); 106 static int age_init_rx_ring(struct age_softc *); 107 static void age_init_rr_ring(struct age_softc *); 108 static void age_init_cmb_block(struct age_softc *); 109 static void age_init_smb_block(struct age_softc *); 110 static int age_newbuf(struct age_softc *, struct age_rxdesc *, int); 111 static void age_mac_config(struct age_softc *); 112 static void age_txintr(struct age_softc *, int); 113 static void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 114 static void age_rxintr(struct age_softc *, int); 115 static void age_tick(void *); 116 static void age_reset(struct age_softc *); 117 static void age_stop(struct age_softc *); 118 static void age_stats_update(struct age_softc *); 119 static void age_stop_txmac(struct age_softc *); 120 static void age_stop_rxmac(struct age_softc *); 121 static void age_rxvlan(struct age_softc *sc); 122 static void age_rxfilter(struct age_softc *); 123 124 CFATTACH_DECL_NEW(age, sizeof(struct age_softc), 125 age_match, age_attach, age_detach, NULL); 126 127 int agedebug = 0; 128 #define DPRINTF(x) do { if (agedebug) printf x; } while (0) 129 130 #define AGE_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 131 132 static int 133 age_match(device_t dev, cfdata_t match, void *aux) 134 { 135 struct pci_attach_args *pa = aux; 136 137 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && 138 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_GIGA); 139 } 140 141 static void 142 age_attach(device_t parent, device_t self, void *aux) 143 { 144 struct age_softc *sc = device_private(self); 145 struct pci_attach_args *pa = aux; 146 pci_intr_handle_t ih; 147 const char *intrstr; 148 struct ifnet *ifp = &sc->sc_ec.ec_if; 149 pcireg_t memtype; 150 int error = 0; 151 152 aprint_naive("\n"); 153 aprint_normal(": Attansic/Atheros L1 Gigabit Ethernet\n"); 154 155 sc->sc_dev = self; 156 sc->sc_dmat = pa->pa_dmat; 157 sc->sc_pct = pa->pa_pc; 158 sc->sc_pcitag = pa->pa_tag; 159 160 /* 161 * Allocate IO memory 162 */ 163 memtype = pci_mapreg_type(sc->sc_pct, sc->sc_pcitag, AGE_PCIR_BAR); 164 switch (memtype) { 165 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 166 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 167 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 168 break; 169 default: 170 aprint_error_dev(self, "invalid base address register\n"); 171 break; 172 } 173 174 if (pci_mapreg_map(pa, AGE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 175 &sc->sc_mem_bh, NULL, &sc->sc_mem_size) != 0) { 176 aprint_error_dev(self, "could not map mem space\n"); 177 return; 178 } 179 180 if (pci_intr_map(pa, &ih) != 0) { 181 aprint_error_dev(self, "could not map interrupt\n"); 182 return; 183 } 184 185 /* 186 * Allocate IRQ 187 */ 188 intrstr = pci_intr_string(sc->sc_pct, ih); 189 sc->sc_irq_handle = pci_intr_establish(sc->sc_pct, ih, IPL_NET, 190 age_intr, sc); 191 if (sc->sc_irq_handle == NULL) { 192 aprint_error_dev(self, "could not establish interrupt"); 193 if (intrstr != NULL) 194 aprint_error(" at %s", intrstr); 195 aprint_error("\n"); 196 return; 197 } 198 aprint_normal_dev(self, "%s", intrstr); 199 200 /* Set PHY address. */ 201 sc->age_phyaddr = AGE_PHY_ADDR; 202 203 /* Reset PHY. */ 204 age_phy_reset(sc); 205 206 /* Reset the ethernet controller. */ 207 age_reset(sc); 208 209 /* Get PCI and chip id/revision. */ 210 sc->age_rev = PCI_REVISION(pa->pa_class); 211 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 212 MASTER_CHIP_REV_SHIFT; 213 214 aprint_debug_dev(self, "PCI device revision : 0x%04x\n", sc->age_rev); 215 aprint_debug_dev(self, "Chip id/revision : 0x%04x\n", sc->age_chip_rev); 216 217 if (agedebug) { 218 aprint_debug_dev(self, "%d Tx FIFO, %d Rx FIFO\n", 219 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 220 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 221 } 222 223 /* Set max allowable DMA size. */ 224 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 225 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 226 227 /* Allocate DMA stuffs */ 228 error = age_dma_alloc(sc); 229 if (error) 230 goto fail; 231 232 callout_init(&sc->sc_tick_ch, 0); 233 callout_setfunc(&sc->sc_tick_ch, age_tick, sc); 234 235 /* Load station address. */ 236 age_get_macaddr(sc, sc->sc_enaddr); 237 238 aprint_normal_dev(self, "Ethernet address %s\n", 239 ether_sprintf(sc->sc_enaddr)); 240 241 ifp->if_softc = sc; 242 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 243 ifp->if_init = age_init; 244 ifp->if_ioctl = age_ioctl; 245 ifp->if_start = age_start; 246 ifp->if_watchdog = age_watchdog; 247 ifp->if_baudrate = IF_Gbps(1); 248 IFQ_SET_MAXLEN(&ifp->if_snd, AGE_TX_RING_CNT - 1); 249 IFQ_SET_READY(&ifp->if_snd); 250 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 251 252 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 253 254 #ifdef AGE_CHECKSUM 255 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 256 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 257 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 258 #endif 259 260 #if NVLAN > 0 261 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 262 #endif 263 264 /* Set up MII bus. */ 265 sc->sc_miibus.mii_ifp = ifp; 266 sc->sc_miibus.mii_readreg = age_miibus_readreg; 267 sc->sc_miibus.mii_writereg = age_miibus_writereg; 268 sc->sc_miibus.mii_statchg = age_miibus_statchg; 269 270 ifmedia_init(&sc->sc_miibus.mii_media, 0, age_mediachange, 271 age_mediastatus); 272 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 273 MII_OFFSET_ANY, 0); 274 275 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 276 aprint_error_dev(self, "no PHY found!\n"); 277 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 278 0, NULL); 279 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 280 } else 281 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 282 283 if_attach(ifp); 284 ether_ifattach(ifp, sc->sc_enaddr); 285 286 if (!pmf_device_register(self, NULL, NULL)) 287 aprint_error_dev(self, "couldn't establish power handler\n"); 288 else 289 pmf_class_network_register(self, ifp); 290 291 return; 292 fail: 293 age_detach(sc->sc_dev, 0); 294 } 295 296 static int 297 age_detach(device_t self, int flags) 298 { 299 struct age_softc *sc = device_private(self); 300 struct ifnet *ifp = &sc->sc_ec.ec_if; 301 int s; 302 303 s = splnet(); 304 age_stop(sc); 305 splx(s); 306 307 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 308 309 /* Delete all remaining media. */ 310 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 311 312 ether_ifdetach(ifp); 313 if_detach(ifp); 314 age_dma_free(sc); 315 316 if (sc->sc_irq_handle != NULL) { 317 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 318 sc->sc_irq_handle = NULL; 319 } 320 321 return (0); 322 } 323 324 /* 325 * Read a PHY register on the MII of the L1. 326 */ 327 static int 328 age_miibus_readreg(struct device *dev, int phy, int reg) 329 { 330 struct age_softc *sc = device_private(dev); 331 uint32_t v; 332 int i; 333 334 if (phy != sc->age_phyaddr) 335 return (0); 336 337 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 338 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 339 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 340 DELAY(1); 341 v = CSR_READ_4(sc, AGE_MDIO); 342 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 343 break; 344 } 345 346 if (i == 0) { 347 printf("%s: phy read timeout: phy %d, reg %d\n", 348 device_xname(sc->sc_dev), phy, reg); 349 return (0); 350 } 351 352 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 353 } 354 355 /* 356 * Write a PHY register on the MII of the L1. 357 */ 358 static void 359 age_miibus_writereg(struct device *dev, int phy, int reg, int val) 360 { 361 struct age_softc *sc = device_private(dev); 362 uint32_t v; 363 int i; 364 365 if (phy != sc->age_phyaddr) 366 return; 367 368 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 369 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 370 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 371 372 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 373 DELAY(1); 374 v = CSR_READ_4(sc, AGE_MDIO); 375 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 376 break; 377 } 378 379 if (i == 0) { 380 printf("%s: phy write timeout: phy %d, reg %d\n", 381 device_xname(sc->sc_dev), phy, reg); 382 } 383 } 384 385 /* 386 * Callback from MII layer when media changes. 387 */ 388 static void 389 age_miibus_statchg(device_t dev) 390 { 391 struct age_softc *sc = device_private(dev); 392 struct ifnet *ifp = &sc->sc_ec.ec_if; 393 struct mii_data *mii; 394 395 if ((ifp->if_flags & IFF_RUNNING) == 0) 396 return; 397 398 mii = &sc->sc_miibus; 399 400 sc->age_flags &= ~AGE_FLAG_LINK; 401 if ((mii->mii_media_status & IFM_AVALID) != 0) { 402 switch (IFM_SUBTYPE(mii->mii_media_active)) { 403 case IFM_10_T: 404 case IFM_100_TX: 405 case IFM_1000_T: 406 sc->age_flags |= AGE_FLAG_LINK; 407 break; 408 default: 409 break; 410 } 411 } 412 413 /* Stop Rx/Tx MACs. */ 414 age_stop_rxmac(sc); 415 age_stop_txmac(sc); 416 417 /* Program MACs with resolved speed/duplex/flow-control. */ 418 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 419 uint32_t reg; 420 421 age_mac_config(sc); 422 reg = CSR_READ_4(sc, AGE_MAC_CFG); 423 /* Restart DMA engine and Tx/Rx MAC. */ 424 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 425 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 426 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 427 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 428 } 429 } 430 431 /* 432 * Get the current interface media status. 433 */ 434 static void 435 age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 436 { 437 struct age_softc *sc = ifp->if_softc; 438 struct mii_data *mii = &sc->sc_miibus; 439 440 mii_pollstat(mii); 441 ifmr->ifm_status = mii->mii_media_status; 442 ifmr->ifm_active = mii->mii_media_active; 443 } 444 445 /* 446 * Set hardware to newly-selected media. 447 */ 448 static int 449 age_mediachange(struct ifnet *ifp) 450 { 451 struct age_softc *sc = ifp->if_softc; 452 struct mii_data *mii = &sc->sc_miibus; 453 int error; 454 455 if (mii->mii_instance != 0) { 456 struct mii_softc *miisc; 457 458 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 459 mii_phy_reset(miisc); 460 } 461 error = mii_mediachg(mii); 462 463 return (error); 464 } 465 466 static int 467 age_intr(void *arg) 468 { 469 struct age_softc *sc = arg; 470 struct ifnet *ifp = &sc->sc_ec.ec_if; 471 struct cmb *cmb; 472 uint32_t status; 473 474 status = CSR_READ_4(sc, AGE_INTR_STATUS); 475 if (status == 0 || (status & AGE_INTRS) == 0) 476 return (0); 477 478 /* Disable interrupts. */ 479 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 480 481 cmb = sc->age_rdata.age_cmb_block; 482 483 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 484 sc->age_cdata.age_cmb_block_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 485 status = le32toh(cmb->intr_status); 486 if ((status & AGE_INTRS) == 0) 487 goto back; 488 489 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 490 TPD_CONS_SHIFT; 491 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 492 RRD_PROD_SHIFT; 493 494 /* Let hardware know CMB was served. */ 495 cmb->intr_status = 0; 496 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 497 sc->age_cdata.age_cmb_block_map->dm_mapsize, 498 BUS_DMASYNC_PREWRITE); 499 500 if (ifp->if_flags & IFF_RUNNING) { 501 if (status & INTR_CMB_RX) 502 age_rxintr(sc, sc->age_rr_prod); 503 504 if (status & INTR_CMB_TX) 505 age_txintr(sc, sc->age_tpd_cons); 506 507 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 508 if (status & INTR_DMA_RD_TO_RST) 509 printf("%s: DMA read error! -- resetting\n", 510 device_xname(sc->sc_dev)); 511 if (status & INTR_DMA_WR_TO_RST) 512 printf("%s: DMA write error! -- resetting\n", 513 device_xname(sc->sc_dev)); 514 age_init(ifp); 515 } 516 517 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 518 age_start(ifp); 519 520 if (status & INTR_SMB) 521 age_stats_update(sc); 522 } 523 524 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 525 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 526 sc->age_cdata.age_cmb_block_map->dm_mapsize, 527 BUS_DMASYNC_POSTREAD); 528 529 back: 530 /* Re-enable interrupts. */ 531 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 532 533 return (1); 534 } 535 536 static int 537 age_read_vpd_word(struct age_softc *sc, uint32_t vpdc, uint32_t offset, 538 uint32_t *word) 539 { 540 int i; 541 542 pci_conf_write(sc->sc_pct, sc->sc_pcitag, vpdc + 0x0, offset << 16); 543 for (i = AGE_TIMEOUT; i > 0; i--) { 544 DELAY(10); 545 if ((pci_conf_read(sc->sc_pct, sc->sc_pcitag, 546 vpdc + 0x0) >> 16 & 0x8000) == 0x8000) 547 break; 548 } 549 if (i == 0) { 550 printf("%s: VPD read timeout!\n", device_xname(sc->sc_dev)); 551 *word = 0; 552 return (ETIMEDOUT); 553 } 554 555 *word = pci_conf_read(sc->sc_pct, sc->sc_pcitag, vpdc + 0x4); 556 return (0); 557 } 558 559 static void 560 age_get_macaddr(struct age_softc *sc, uint8_t eaddr[]) 561 { 562 uint32_t ea[2], off, reg, word; 563 int vpd_error, match, vpdc; 564 565 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 566 if ((reg & SPI_VPD_ENB) != 0) { 567 /* Get VPD stored in TWSI EEPROM. */ 568 reg &= ~SPI_VPD_ENB; 569 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 570 } 571 572 vpd_error = 0; 573 ea[0] = ea[1] = 0; 574 if ((vpd_error = pci_get_capability(sc->sc_pct, sc->sc_pcitag, 575 PCI_CAP_VPD, &vpdc, NULL))) { 576 /* 577 * PCI VPD capability exists, but it seems that it's 578 * not in the standard form as stated in PCI VPD 579 * specification such that driver could not use 580 * pci_get_vpd_readonly(9) with keyword 'NA'. 581 * Search VPD data starting at address 0x0100. The data 582 * should be used as initializers to set AGE_PAR0, 583 * AGE_PAR1 register including other PCI configuration 584 * registers. 585 */ 586 word = 0; 587 match = 0; 588 reg = 0; 589 for (off = AGE_VPD_REG_CONF_START; off < AGE_VPD_REG_CONF_END; 590 off += sizeof(uint32_t)) { 591 vpd_error = age_read_vpd_word(sc, vpdc, off, &word); 592 if (vpd_error != 0) 593 break; 594 if (match != 0) { 595 switch (reg) { 596 case AGE_PAR0: 597 ea[0] = word; 598 break; 599 case AGE_PAR1: 600 ea[1] = word; 601 break; 602 default: 603 break; 604 } 605 match = 0; 606 } else if ((word & 0xFF) == AGE_VPD_REG_CONF_SIG) { 607 match = 1; 608 reg = word >> 16; 609 } else 610 break; 611 } 612 if (off >= AGE_VPD_REG_CONF_END) 613 vpd_error = ENOENT; 614 if (vpd_error == 0) { 615 /* 616 * Don't blindly trust ethernet address obtained 617 * from VPD. Check whether ethernet address is 618 * valid one. Otherwise fall-back to reading 619 * PAR register. 620 */ 621 ea[1] &= 0xFFFF; 622 if ((ea[0] == 0 && ea[1] == 0) || 623 (ea[0] == 0xFFFFFFFF && ea[1] == 0xFFFF)) { 624 if (agedebug) 625 printf("%s: invalid ethernet address " 626 "returned from VPD.\n", 627 device_xname(sc->sc_dev)); 628 vpd_error = EINVAL; 629 } 630 } 631 if (vpd_error != 0 && (agedebug)) 632 printf("%s: VPD access failure!\n", 633 device_xname(sc->sc_dev)); 634 } else { 635 if (agedebug) 636 printf("%s: PCI VPD capability not found!\n", 637 device_xname(sc->sc_dev)); 638 } 639 640 /* 641 * It seems that L1 also provides a way to extract ethernet 642 * address via SPI flash interface. Because SPI flash memory 643 * device of different vendors vary in their instruction 644 * codes for read ID instruction, it's very hard to get 645 * instructions codes without detailed information for the 646 * flash memory device used on ethernet controller. To simplify 647 * code, just read AGE_PAR0/AGE_PAR1 register to get ethernet 648 * address which is supposed to be set by hardware during 649 * power on reset. 650 */ 651 if (vpd_error != 0) { 652 /* 653 * VPD is mapped to SPI flash memory or BIOS set it. 654 */ 655 ea[0] = CSR_READ_4(sc, AGE_PAR0); 656 ea[1] = CSR_READ_4(sc, AGE_PAR1); 657 } 658 659 ea[1] &= 0xFFFF; 660 eaddr[0] = (ea[1] >> 8) & 0xFF; 661 eaddr[1] = (ea[1] >> 0) & 0xFF; 662 eaddr[2] = (ea[0] >> 24) & 0xFF; 663 eaddr[3] = (ea[0] >> 16) & 0xFF; 664 eaddr[4] = (ea[0] >> 8) & 0xFF; 665 eaddr[5] = (ea[0] >> 0) & 0xFF; 666 } 667 668 static void 669 age_phy_reset(struct age_softc *sc) 670 { 671 /* Reset PHY. */ 672 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 673 DELAY(1000); 674 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 675 DELAY(1000); 676 } 677 678 static int 679 age_dma_alloc(struct age_softc *sc) 680 { 681 struct age_txdesc *txd; 682 struct age_rxdesc *rxd; 683 int nsegs, error, i; 684 685 /* 686 * Create DMA stuffs for TX ring 687 */ 688 error = bus_dmamap_create(sc->sc_dmat, AGE_TX_RING_SZ, 1, 689 AGE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_tx_ring_map); 690 if (error) 691 return (ENOBUFS); 692 693 /* Allocate DMA'able memory for TX ring */ 694 error = bus_dmamem_alloc(sc->sc_dmat, AGE_TX_RING_SZ, 695 PAGE_SIZE, 0, &sc->age_rdata.age_tx_ring_seg, 1, 696 &nsegs, BUS_DMA_WAITOK); 697 if (error) { 698 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 699 device_xname(sc->sc_dev)); 700 return error; 701 } 702 703 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_tx_ring_seg, 704 nsegs, AGE_TX_RING_SZ, (void **)&sc->age_rdata.age_tx_ring, 705 BUS_DMA_NOWAIT); 706 if (error) 707 return (ENOBUFS); 708 709 memset(sc->age_rdata.age_tx_ring, 0, AGE_TX_RING_SZ); 710 711 /* Load the DMA map for Tx ring. */ 712 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 713 sc->age_rdata.age_tx_ring, AGE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 714 if (error) { 715 printf("%s: could not load DMA'able memory for Tx ring.\n", 716 device_xname(sc->sc_dev)); 717 bus_dmamem_free(sc->sc_dmat, 718 (bus_dma_segment_t *)&sc->age_rdata.age_tx_ring, 1); 719 return error; 720 } 721 722 sc->age_rdata.age_tx_ring_paddr = 723 sc->age_cdata.age_tx_ring_map->dm_segs[0].ds_addr; 724 725 /* 726 * Create DMA stuffs for RX ring 727 */ 728 error = bus_dmamap_create(sc->sc_dmat, AGE_RX_RING_SZ, 1, 729 AGE_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_ring_map); 730 if (error) 731 return (ENOBUFS); 732 733 /* Allocate DMA'able memory for RX ring */ 734 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RX_RING_SZ, 735 PAGE_SIZE, 0, &sc->age_rdata.age_rx_ring_seg, 1, 736 &nsegs, BUS_DMA_WAITOK); 737 if (error) { 738 printf("%s: could not allocate DMA'able memory for Rx ring.\n", 739 device_xname(sc->sc_dev)); 740 return error; 741 } 742 743 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rx_ring_seg, 744 nsegs, AGE_RX_RING_SZ, (void **)&sc->age_rdata.age_rx_ring, 745 BUS_DMA_NOWAIT); 746 if (error) 747 return (ENOBUFS); 748 749 memset(sc->age_rdata.age_rx_ring, 0, AGE_RX_RING_SZ); 750 751 /* Load the DMA map for Rx ring. */ 752 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 753 sc->age_rdata.age_rx_ring, AGE_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 754 if (error) { 755 printf("%s: could not load DMA'able memory for Rx ring.\n", 756 device_xname(sc->sc_dev)); 757 bus_dmamem_free(sc->sc_dmat, 758 (bus_dma_segment_t *)sc->age_rdata.age_rx_ring, 1); 759 return error; 760 } 761 762 sc->age_rdata.age_rx_ring_paddr = 763 sc->age_cdata.age_rx_ring_map->dm_segs[0].ds_addr; 764 765 /* 766 * Create DMA stuffs for RX return ring 767 */ 768 error = bus_dmamap_create(sc->sc_dmat, AGE_RR_RING_SZ, 1, 769 AGE_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rr_ring_map); 770 if (error) 771 return (ENOBUFS); 772 773 /* Allocate DMA'able memory for RX return ring */ 774 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RR_RING_SZ, 775 PAGE_SIZE, 0, &sc->age_rdata.age_rr_ring_seg, 1, 776 &nsegs, BUS_DMA_WAITOK); 777 if (error) { 778 printf("%s: could not allocate DMA'able memory for Rx " 779 "return ring.\n", device_xname(sc->sc_dev)); 780 return error; 781 } 782 783 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rr_ring_seg, 784 nsegs, AGE_RR_RING_SZ, (void **)&sc->age_rdata.age_rr_ring, 785 BUS_DMA_NOWAIT); 786 if (error) 787 return (ENOBUFS); 788 789 memset(sc->age_rdata.age_rr_ring, 0, AGE_RR_RING_SZ); 790 791 /* Load the DMA map for Rx return ring. */ 792 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 793 sc->age_rdata.age_rr_ring, AGE_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 794 if (error) { 795 printf("%s: could not load DMA'able memory for Rx return ring." 796 "\n", device_xname(sc->sc_dev)); 797 bus_dmamem_free(sc->sc_dmat, 798 (bus_dma_segment_t *)&sc->age_rdata.age_rr_ring, 1); 799 return error; 800 } 801 802 sc->age_rdata.age_rr_ring_paddr = 803 sc->age_cdata.age_rr_ring_map->dm_segs[0].ds_addr; 804 805 /* 806 * Create DMA stuffs for CMB block 807 */ 808 error = bus_dmamap_create(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 1, 809 AGE_CMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 810 &sc->age_cdata.age_cmb_block_map); 811 if (error) 812 return (ENOBUFS); 813 814 /* Allocate DMA'able memory for CMB block */ 815 error = bus_dmamem_alloc(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 816 PAGE_SIZE, 0, &sc->age_rdata.age_cmb_block_seg, 1, 817 &nsegs, BUS_DMA_WAITOK); 818 if (error) { 819 printf("%s: could not allocate DMA'able memory for " 820 "CMB block\n", device_xname(sc->sc_dev)); 821 return error; 822 } 823 824 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_cmb_block_seg, 825 nsegs, AGE_CMB_BLOCK_SZ, (void **)&sc->age_rdata.age_cmb_block, 826 BUS_DMA_NOWAIT); 827 if (error) 828 return (ENOBUFS); 829 830 memset(sc->age_rdata.age_cmb_block, 0, AGE_CMB_BLOCK_SZ); 831 832 /* Load the DMA map for CMB block. */ 833 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 834 sc->age_rdata.age_cmb_block, AGE_CMB_BLOCK_SZ, NULL, 835 BUS_DMA_WAITOK); 836 if (error) { 837 printf("%s: could not load DMA'able memory for CMB block\n", 838 device_xname(sc->sc_dev)); 839 bus_dmamem_free(sc->sc_dmat, 840 (bus_dma_segment_t *)&sc->age_rdata.age_cmb_block, 1); 841 return error; 842 } 843 844 sc->age_rdata.age_cmb_block_paddr = 845 sc->age_cdata.age_cmb_block_map->dm_segs[0].ds_addr; 846 847 /* 848 * Create DMA stuffs for SMB block 849 */ 850 error = bus_dmamap_create(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 1, 851 AGE_SMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 852 &sc->age_cdata.age_smb_block_map); 853 if (error) 854 return (ENOBUFS); 855 856 /* Allocate DMA'able memory for SMB block */ 857 error = bus_dmamem_alloc(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 858 PAGE_SIZE, 0, &sc->age_rdata.age_smb_block_seg, 1, 859 &nsegs, BUS_DMA_WAITOK); 860 if (error) { 861 printf("%s: could not allocate DMA'able memory for " 862 "SMB block\n", device_xname(sc->sc_dev)); 863 return error; 864 } 865 866 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_smb_block_seg, 867 nsegs, AGE_SMB_BLOCK_SZ, (void **)&sc->age_rdata.age_smb_block, 868 BUS_DMA_NOWAIT); 869 if (error) 870 return (ENOBUFS); 871 872 memset(sc->age_rdata.age_smb_block, 0, AGE_SMB_BLOCK_SZ); 873 874 /* Load the DMA map for SMB block */ 875 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 876 sc->age_rdata.age_smb_block, AGE_SMB_BLOCK_SZ, NULL, 877 BUS_DMA_WAITOK); 878 if (error) { 879 printf("%s: could not load DMA'able memory for SMB block\n", 880 device_xname(sc->sc_dev)); 881 bus_dmamem_free(sc->sc_dmat, 882 (bus_dma_segment_t *)&sc->age_rdata.age_smb_block, 1); 883 return error; 884 } 885 886 sc->age_rdata.age_smb_block_paddr = 887 sc->age_cdata.age_smb_block_map->dm_segs[0].ds_addr; 888 889 /* Create DMA maps for Tx buffers. */ 890 for (i = 0; i < AGE_TX_RING_CNT; i++) { 891 txd = &sc->age_cdata.age_txdesc[i]; 892 txd->tx_m = NULL; 893 txd->tx_dmamap = NULL; 894 error = bus_dmamap_create(sc->sc_dmat, AGE_TSO_MAXSIZE, 895 AGE_MAXTXSEGS, AGE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 896 &txd->tx_dmamap); 897 if (error) { 898 printf("%s: could not create Tx dmamap.\n", 899 device_xname(sc->sc_dev)); 900 return error; 901 } 902 } 903 904 /* Create DMA maps for Rx buffers. */ 905 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 906 BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_sparemap); 907 if (error) { 908 printf("%s: could not create spare Rx dmamap.\n", 909 device_xname(sc->sc_dev)); 910 return error; 911 } 912 for (i = 0; i < AGE_RX_RING_CNT; i++) { 913 rxd = &sc->age_cdata.age_rxdesc[i]; 914 rxd->rx_m = NULL; 915 rxd->rx_dmamap = NULL; 916 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 917 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 918 if (error) { 919 printf("%s: could not create Rx dmamap.\n", 920 device_xname(sc->sc_dev)); 921 return error; 922 } 923 } 924 925 return (0); 926 } 927 928 static void 929 age_dma_free(struct age_softc *sc) 930 { 931 struct age_txdesc *txd; 932 struct age_rxdesc *rxd; 933 int i; 934 935 /* Tx buffers */ 936 for (i = 0; i < AGE_TX_RING_CNT; i++) { 937 txd = &sc->age_cdata.age_txdesc[i]; 938 if (txd->tx_dmamap != NULL) { 939 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 940 txd->tx_dmamap = NULL; 941 } 942 } 943 /* Rx buffers */ 944 for (i = 0; i < AGE_RX_RING_CNT; i++) { 945 rxd = &sc->age_cdata.age_rxdesc[i]; 946 if (rxd->rx_dmamap != NULL) { 947 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 948 rxd->rx_dmamap = NULL; 949 } 950 } 951 if (sc->age_cdata.age_rx_sparemap != NULL) { 952 bus_dmamap_destroy(sc->sc_dmat, sc->age_cdata.age_rx_sparemap); 953 sc->age_cdata.age_rx_sparemap = NULL; 954 } 955 956 /* Tx ring. */ 957 if (sc->age_cdata.age_tx_ring_map != NULL) 958 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_tx_ring_map); 959 if (sc->age_cdata.age_tx_ring_map != NULL && 960 sc->age_rdata.age_tx_ring != NULL) 961 bus_dmamem_free(sc->sc_dmat, 962 (bus_dma_segment_t *)sc->age_rdata.age_tx_ring, 1); 963 sc->age_rdata.age_tx_ring = NULL; 964 sc->age_cdata.age_tx_ring_map = NULL; 965 966 /* Rx ring. */ 967 if (sc->age_cdata.age_rx_ring_map != NULL) 968 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rx_ring_map); 969 if (sc->age_cdata.age_rx_ring_map != NULL && 970 sc->age_rdata.age_rx_ring != NULL) 971 bus_dmamem_free(sc->sc_dmat, 972 (bus_dma_segment_t *)sc->age_rdata.age_rx_ring, 1); 973 sc->age_rdata.age_rx_ring = NULL; 974 sc->age_cdata.age_rx_ring_map = NULL; 975 976 /* Rx return ring. */ 977 if (sc->age_cdata.age_rr_ring_map != NULL) 978 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rr_ring_map); 979 if (sc->age_cdata.age_rr_ring_map != NULL && 980 sc->age_rdata.age_rr_ring != NULL) 981 bus_dmamem_free(sc->sc_dmat, 982 (bus_dma_segment_t *)sc->age_rdata.age_rr_ring, 1); 983 sc->age_rdata.age_rr_ring = NULL; 984 sc->age_cdata.age_rr_ring_map = NULL; 985 986 /* CMB block */ 987 if (sc->age_cdata.age_cmb_block_map != NULL) 988 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_cmb_block_map); 989 if (sc->age_cdata.age_cmb_block_map != NULL && 990 sc->age_rdata.age_cmb_block != NULL) 991 bus_dmamem_free(sc->sc_dmat, 992 (bus_dma_segment_t *)sc->age_rdata.age_cmb_block, 1); 993 sc->age_rdata.age_cmb_block = NULL; 994 sc->age_cdata.age_cmb_block_map = NULL; 995 996 /* SMB block */ 997 if (sc->age_cdata.age_smb_block_map != NULL) 998 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_smb_block_map); 999 if (sc->age_cdata.age_smb_block_map != NULL && 1000 sc->age_rdata.age_smb_block != NULL) 1001 bus_dmamem_free(sc->sc_dmat, 1002 (bus_dma_segment_t *)sc->age_rdata.age_smb_block, 1); 1003 } 1004 1005 static void 1006 age_start(struct ifnet *ifp) 1007 { 1008 struct age_softc *sc = ifp->if_softc; 1009 struct mbuf *m_head; 1010 int enq; 1011 1012 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1013 return; 1014 1015 enq = 0; 1016 for (;;) { 1017 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1018 if (m_head == NULL) 1019 break; 1020 1021 /* 1022 * Pack the data into the transmit ring. If we 1023 * don't have room, set the OACTIVE flag and wait 1024 * for the NIC to drain the ring. 1025 */ 1026 if (age_encap(sc, &m_head)) { 1027 if (m_head == NULL) 1028 break; 1029 ifp->if_flags |= IFF_OACTIVE; 1030 break; 1031 } 1032 enq = 1; 1033 1034 #if NBPFILTER > 0 1035 /* 1036 * If there's a BPF listener, bounce a copy of this frame 1037 * to him. 1038 */ 1039 if (ifp->if_bpf != NULL) 1040 bpf_mtap(ifp->if_bpf, m_head); 1041 #endif 1042 } 1043 1044 if (enq) { 1045 /* Update mbox. */ 1046 AGE_COMMIT_MBOX(sc); 1047 /* Set a timeout in case the chip goes out to lunch. */ 1048 ifp->if_timer = AGE_TX_TIMEOUT; 1049 } 1050 } 1051 1052 static void 1053 age_watchdog(struct ifnet *ifp) 1054 { 1055 struct age_softc *sc = ifp->if_softc; 1056 1057 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1058 printf("%s: watchdog timeout (missed link)\n", 1059 device_xname(sc->sc_dev)); 1060 ifp->if_oerrors++; 1061 age_init(ifp); 1062 return; 1063 } 1064 1065 if (sc->age_cdata.age_tx_cnt == 0) { 1066 printf("%s: watchdog timeout (missed Tx interrupts) " 1067 "-- recovering\n", device_xname(sc->sc_dev)); 1068 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1069 age_start(ifp); 1070 return; 1071 } 1072 1073 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1074 ifp->if_oerrors++; 1075 age_init(ifp); 1076 1077 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1078 age_start(ifp); 1079 } 1080 1081 static int 1082 age_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1083 { 1084 struct age_softc *sc = ifp->if_softc; 1085 struct mii_data *mii = &sc->sc_miibus; 1086 struct ifreq *ifr = (struct ifreq *)data; 1087 int s, error = 0; 1088 1089 s = splnet(); 1090 1091 switch (cmd) { 1092 case SIOCSIFADDR: 1093 ifp->if_flags |= IFF_UP; 1094 if (!(ifp->if_flags & IFF_RUNNING)) 1095 age_init(ifp); 1096 #ifdef INET 1097 if (ifa->ifa_addr->sa_family == AF_INET) 1098 arp_ifinit(&sc->sc_ec, ifa); 1099 #endif 1100 break; 1101 1102 case SIOCSIFFLAGS: 1103 error = ifioctl_common(ifp, cmd, data); 1104 if (error) 1105 break; 1106 if (ifp->if_flags & IFF_UP) { 1107 if (ifp->if_flags & IFF_RUNNING) 1108 age_rxfilter(sc); 1109 else 1110 age_init(ifp); 1111 } else { 1112 if (ifp->if_flags & IFF_RUNNING) 1113 age_stop(sc); 1114 } 1115 sc->age_if_flags = ifp->if_flags; 1116 break; 1117 1118 case SIOCADDMULTI: 1119 case SIOCDELMULTI: 1120 error = ether_ioctl(ifp, cmd, data); 1121 break; 1122 1123 case SIOCSIFMEDIA: 1124 case SIOCGIFMEDIA: 1125 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1126 break; 1127 default: 1128 error = ether_ioctl(ifp, cmd, data); 1129 break; 1130 } 1131 1132 if (error == ENETRESET) { 1133 if (ifp->if_flags & IFF_RUNNING) 1134 age_rxfilter(sc); 1135 error = 0; 1136 } 1137 1138 splx(s); 1139 return (error); 1140 } 1141 1142 static void 1143 age_mac_config(struct age_softc *sc) 1144 { 1145 struct mii_data *mii; 1146 uint32_t reg; 1147 1148 mii = &sc->sc_miibus; 1149 1150 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1151 reg &= ~MAC_CFG_FULL_DUPLEX; 1152 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1153 reg &= ~MAC_CFG_SPEED_MASK; 1154 1155 /* Reprogram MAC with resolved speed/duplex. */ 1156 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1157 case IFM_10_T: 1158 case IFM_100_TX: 1159 reg |= MAC_CFG_SPEED_10_100; 1160 break; 1161 case IFM_1000_T: 1162 reg |= MAC_CFG_SPEED_1000; 1163 break; 1164 } 1165 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1166 reg |= MAC_CFG_FULL_DUPLEX; 1167 #ifdef notyet 1168 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1169 reg |= MAC_CFG_TX_FC; 1170 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1171 reg |= MAC_CFG_RX_FC; 1172 #endif 1173 } 1174 1175 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1176 } 1177 1178 static int 1179 age_encap(struct age_softc *sc, struct mbuf **m_head) 1180 { 1181 struct age_txdesc *txd, *txd_last; 1182 struct tx_desc *desc; 1183 struct mbuf *m; 1184 bus_dmamap_t map; 1185 uint32_t cflags, poff, vtag; 1186 int error, i, nsegs, prod; 1187 struct m_tag *mtag; 1188 1189 m = *m_head; 1190 cflags = vtag = 0; 1191 poff = 0; 1192 1193 prod = sc->age_cdata.age_tx_prod; 1194 txd = &sc->age_cdata.age_txdesc[prod]; 1195 txd_last = txd; 1196 map = txd->tx_dmamap; 1197 1198 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1199 1200 if (error != 0) { 1201 bus_dmamap_unload(sc->sc_dmat, map); 1202 error = EFBIG; 1203 } 1204 if (error == EFBIG) { 1205 error = 0; 1206 1207 MGETHDR(m, M_DONTWAIT, MT_DATA); 1208 if (m == NULL) { 1209 printf("%s: can't defrag TX mbuf\n", 1210 device_xname(sc->sc_dev)); 1211 m_freem(*m_head); 1212 *m_head = NULL; 1213 return (ENOBUFS); 1214 } 1215 1216 MCLGET(m, M_DONTWAIT); 1217 if (!(m->m_flags & M_EXT)) { 1218 m_freem(m); 1219 *m_head = NULL; 1220 return (ENOBUFS); 1221 } 1222 m->m_len = m->m_pkthdr.len; 1223 *m_head = m; 1224 1225 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1226 BUS_DMA_NOWAIT); 1227 1228 if (error != 0) { 1229 printf("%s: could not load defragged TX mbuf\n", 1230 device_xname(sc->sc_dev)); 1231 if (!error) { 1232 bus_dmamap_unload(sc->sc_dmat, map); 1233 error = EFBIG; 1234 } 1235 m_freem(*m_head); 1236 *m_head = NULL; 1237 return (error); 1238 } 1239 } else if (error) { 1240 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 1241 return (error); 1242 } 1243 1244 nsegs = map->dm_nsegs; 1245 1246 if (nsegs == 0) { 1247 m_freem(*m_head); 1248 *m_head = NULL; 1249 return (EIO); 1250 } 1251 1252 /* Check descriptor overrun. */ 1253 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1254 bus_dmamap_unload(sc->sc_dmat, map); 1255 return (ENOBUFS); 1256 } 1257 1258 m = *m_head; 1259 /* Configure Tx IP/TCP/UDP checksum offload. */ 1260 if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1261 cflags |= AGE_TD_CSUM; 1262 if ((m->m_pkthdr.csum_flags & M_CSUM_TCPv4) != 0) 1263 cflags |= AGE_TD_TCPCSUM; 1264 if ((m->m_pkthdr.csum_flags & M_CSUM_UDPv4) != 0) 1265 cflags |= AGE_TD_UDPCSUM; 1266 /* Set checksum start offset. */ 1267 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1268 } 1269 1270 #if NVLAN > 0 1271 /* Configure VLAN hardware tag insertion. */ 1272 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m))) { 1273 vtag = AGE_TX_VLAN_TAG(htons(VLAN_TAG_VALUE(mtag))); 1274 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1275 cflags |= AGE_TD_INSERT_VLAN_TAG; 1276 } 1277 #endif 1278 1279 desc = NULL; 1280 for (i = 0; i < nsegs; i++) { 1281 desc = &sc->age_rdata.age_tx_ring[prod]; 1282 desc->addr = htole64(map->dm_segs[i].ds_addr); 1283 desc->len = 1284 htole32(AGE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 1285 desc->flags = htole32(cflags); 1286 sc->age_cdata.age_tx_cnt++; 1287 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1288 } 1289 1290 /* Update producer index. */ 1291 sc->age_cdata.age_tx_prod = prod; 1292 1293 /* Set EOP on the last descriptor. */ 1294 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1295 desc = &sc->age_rdata.age_tx_ring[prod]; 1296 desc->flags |= htole32(AGE_TD_EOP); 1297 1298 /* Swap dmamap of the first and the last. */ 1299 txd = &sc->age_cdata.age_txdesc[prod]; 1300 map = txd_last->tx_dmamap; 1301 txd_last->tx_dmamap = txd->tx_dmamap; 1302 txd->tx_dmamap = map; 1303 txd->tx_m = m; 1304 1305 /* Sync descriptors. */ 1306 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1307 BUS_DMASYNC_PREWRITE); 1308 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1309 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1310 1311 return (0); 1312 } 1313 1314 static void 1315 age_txintr(struct age_softc *sc, int tpd_cons) 1316 { 1317 struct ifnet *ifp = &sc->sc_ec.ec_if; 1318 struct age_txdesc *txd; 1319 int cons, prog; 1320 1321 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1322 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1323 1324 /* 1325 * Go through our Tx list and free mbufs for those 1326 * frames which have been transmitted. 1327 */ 1328 cons = sc->age_cdata.age_tx_cons; 1329 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 1330 if (sc->age_cdata.age_tx_cnt <= 0) 1331 break; 1332 prog++; 1333 ifp->if_flags &= ~IFF_OACTIVE; 1334 sc->age_cdata.age_tx_cnt--; 1335 txd = &sc->age_cdata.age_txdesc[cons]; 1336 /* 1337 * Clear Tx descriptors, it's not required but would 1338 * help debugging in case of Tx issues. 1339 */ 1340 txd->tx_desc->addr = 0; 1341 txd->tx_desc->len = 0; 1342 txd->tx_desc->flags = 0; 1343 1344 if (txd->tx_m == NULL) 1345 continue; 1346 /* Reclaim transmitted mbufs. */ 1347 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1348 m_freem(txd->tx_m); 1349 txd->tx_m = NULL; 1350 } 1351 1352 if (prog > 0) { 1353 sc->age_cdata.age_tx_cons = cons; 1354 1355 /* 1356 * Unarm watchdog timer only when there are no pending 1357 * Tx descriptors in queue. 1358 */ 1359 if (sc->age_cdata.age_tx_cnt == 0) 1360 ifp->if_timer = 0; 1361 1362 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1363 sc->age_cdata.age_tx_ring_map->dm_mapsize, 1364 BUS_DMASYNC_PREWRITE); 1365 } 1366 } 1367 1368 /* Receive a frame. */ 1369 static void 1370 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 1371 { 1372 struct ifnet *ifp = &sc->sc_ec.ec_if; 1373 struct age_rxdesc *rxd; 1374 struct rx_desc *desc; 1375 struct mbuf *mp, *m; 1376 uint32_t status, index, vtag; 1377 int count, nsegs, pktlen; 1378 int rx_cons; 1379 1380 status = le32toh(rxrd->flags); 1381 index = le32toh(rxrd->index); 1382 rx_cons = AGE_RX_CONS(index); 1383 nsegs = AGE_RX_NSEGS(index); 1384 1385 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 1386 if ((status & AGE_RRD_ERROR) != 0 && 1387 (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 1388 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) { 1389 /* 1390 * We want to pass the following frames to upper 1391 * layer regardless of error status of Rx return 1392 * ring. 1393 * 1394 * o IP/TCP/UDP checksum is bad. 1395 * o frame length and protocol specific length 1396 * does not match. 1397 */ 1398 sc->age_cdata.age_rx_cons += nsegs; 1399 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1400 return; 1401 } 1402 1403 pktlen = 0; 1404 for (count = 0; count < nsegs; count++, 1405 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 1406 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 1407 mp = rxd->rx_m; 1408 desc = rxd->rx_desc; 1409 /* Add a new receive buffer to the ring. */ 1410 if (age_newbuf(sc, rxd, 0) != 0) { 1411 ifp->if_iqdrops++; 1412 /* Reuse Rx buffers. */ 1413 if (sc->age_cdata.age_rxhead != NULL) { 1414 m_freem(sc->age_cdata.age_rxhead); 1415 AGE_RXCHAIN_RESET(sc); 1416 } 1417 break; 1418 } 1419 1420 /* The length of the first mbuf is computed last. */ 1421 if (count != 0) { 1422 mp->m_len = AGE_RX_BYTES(le32toh(desc->len)); 1423 pktlen += mp->m_len; 1424 } 1425 1426 /* Chain received mbufs. */ 1427 if (sc->age_cdata.age_rxhead == NULL) { 1428 sc->age_cdata.age_rxhead = mp; 1429 sc->age_cdata.age_rxtail = mp; 1430 } else { 1431 mp->m_flags &= ~M_PKTHDR; 1432 sc->age_cdata.age_rxprev_tail = 1433 sc->age_cdata.age_rxtail; 1434 sc->age_cdata.age_rxtail->m_next = mp; 1435 sc->age_cdata.age_rxtail = mp; 1436 } 1437 1438 if (count == nsegs - 1) { 1439 /* 1440 * It seems that L1 controller has no way 1441 * to tell hardware to strip CRC bytes. 1442 */ 1443 sc->age_cdata.age_rxlen -= ETHER_CRC_LEN; 1444 if (nsegs > 1) { 1445 /* Remove the CRC bytes in chained mbufs. */ 1446 pktlen -= ETHER_CRC_LEN; 1447 if (mp->m_len <= ETHER_CRC_LEN) { 1448 sc->age_cdata.age_rxtail = 1449 sc->age_cdata.age_rxprev_tail; 1450 sc->age_cdata.age_rxtail->m_len -= 1451 (ETHER_CRC_LEN - mp->m_len); 1452 sc->age_cdata.age_rxtail->m_next = NULL; 1453 m_freem(mp); 1454 } else { 1455 mp->m_len -= ETHER_CRC_LEN; 1456 } 1457 } 1458 1459 m = sc->age_cdata.age_rxhead; 1460 m->m_flags |= M_PKTHDR; 1461 m->m_pkthdr.rcvif = ifp; 1462 m->m_pkthdr.len = sc->age_cdata.age_rxlen; 1463 /* Set the first mbuf length. */ 1464 m->m_len = sc->age_cdata.age_rxlen - pktlen; 1465 1466 /* 1467 * Set checksum information. 1468 * It seems that L1 controller can compute partial 1469 * checksum. The partial checksum value can be used 1470 * to accelerate checksum computation for fragmented 1471 * TCP/UDP packets. Upper network stack already 1472 * takes advantage of the partial checksum value in 1473 * IP reassembly stage. But I'm not sure the 1474 * correctness of the partial hardware checksum 1475 * assistance due to lack of data sheet. If it is 1476 * proven to work on L1 I'll enable it. 1477 */ 1478 if (status & AGE_RRD_IPV4) { 1479 if (!(status & AGE_RRD_IPCSUM_NOK)) 1480 m->m_pkthdr.csum_flags |= 1481 M_CSUM_IPv4_BAD; 1482 if (!((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 1483 (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0)) { 1484 m->m_pkthdr.csum_flags |= 1485 M_CSUM_TCP_UDP_BAD; 1486 } 1487 /* 1488 * Don't mark bad checksum for TCP/UDP frames 1489 * as fragmented frames may always have set 1490 * bad checksummed bit of descriptor status. 1491 */ 1492 } 1493 #if NVLAN > 0 1494 /* Check for VLAN tagged frames. */ 1495 if (status & AGE_RRD_VLAN) { 1496 vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 1497 VLAN_INPUT_TAG(ifp, m, AGE_RX_VLAN_TAG(vtag), 1498 continue); 1499 } 1500 #endif 1501 1502 #if NBPFILTER > 0 1503 if (ifp->if_bpf) 1504 bpf_mtap(ifp->if_bpf, m); 1505 #endif 1506 /* Pass it on. */ 1507 ether_input(ifp, m); 1508 1509 /* Reset mbuf chains. */ 1510 AGE_RXCHAIN_RESET(sc); 1511 } 1512 } 1513 1514 if (count != nsegs) { 1515 sc->age_cdata.age_rx_cons += nsegs; 1516 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1517 } else 1518 sc->age_cdata.age_rx_cons = rx_cons; 1519 } 1520 1521 static void 1522 age_rxintr(struct age_softc *sc, int rr_prod) 1523 { 1524 struct rx_rdesc *rxrd; 1525 int rr_cons, nsegs, pktlen, prog; 1526 1527 rr_cons = sc->age_cdata.age_rr_cons; 1528 if (rr_cons == rr_prod) 1529 return; 1530 1531 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1532 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1533 BUS_DMASYNC_POSTREAD); 1534 1535 for (prog = 0; rr_cons != rr_prod; prog++) { 1536 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 1537 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 1538 if (nsegs == 0) 1539 break; 1540 /* 1541 * Check number of segments against received bytes 1542 * Non-matching value would indicate that hardware 1543 * is still trying to update Rx return descriptors. 1544 * I'm not sure whether this check is really needed. 1545 */ 1546 pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 1547 if (nsegs != ((pktlen + (MCLBYTES - ETHER_HDR_LEN - ETHER_CRC_LEN)) / 1548 (MCLBYTES - ETHER_HDR_LEN))) 1549 break; 1550 1551 /* Received a frame. */ 1552 age_rxeof(sc, rxrd); 1553 1554 /* Clear return ring. */ 1555 rxrd->index = 0; 1556 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 1557 } 1558 1559 if (prog > 0) { 1560 /* Update the consumer index. */ 1561 sc->age_cdata.age_rr_cons = rr_cons; 1562 1563 /* Sync descriptors. */ 1564 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1565 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1566 BUS_DMASYNC_PREWRITE); 1567 1568 /* Notify hardware availability of new Rx buffers. */ 1569 AGE_COMMIT_MBOX(sc); 1570 } 1571 } 1572 1573 static void 1574 age_tick(void *xsc) 1575 { 1576 struct age_softc *sc = xsc; 1577 struct mii_data *mii = &sc->sc_miibus; 1578 int s; 1579 1580 s = splnet(); 1581 mii_tick(mii); 1582 splx(s); 1583 1584 callout_schedule(&sc->sc_tick_ch, hz); 1585 } 1586 1587 static void 1588 age_reset(struct age_softc *sc) 1589 { 1590 uint32_t reg; 1591 int i; 1592 1593 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 1594 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1595 DELAY(1); 1596 if ((CSR_READ_4(sc, AGE_MASTER_CFG) & MASTER_RESET) == 0) 1597 break; 1598 } 1599 if (i == 0) 1600 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 1601 1602 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1603 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1604 break; 1605 DELAY(10); 1606 } 1607 1608 if (i == 0) 1609 printf("%s: reset timeout(0x%08x)!\n", device_xname(sc->sc_dev), 1610 reg); 1611 1612 /* Initialize PCIe module. From Linux. */ 1613 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1614 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1615 } 1616 1617 static int 1618 age_init(struct ifnet *ifp) 1619 { 1620 struct age_softc *sc = ifp->if_softc; 1621 struct mii_data *mii; 1622 uint8_t eaddr[ETHER_ADDR_LEN]; 1623 bus_addr_t paddr; 1624 uint32_t reg, fsize; 1625 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 1626 int error; 1627 1628 /* 1629 * Cancel any pending I/O. 1630 */ 1631 age_stop(sc); 1632 1633 /* 1634 * Reset the chip to a known state. 1635 */ 1636 age_reset(sc); 1637 1638 /* Initialize descriptors. */ 1639 error = age_init_rx_ring(sc); 1640 if (error != 0) { 1641 printf("%s: no memory for Rx buffers.\n", device_xname(sc->sc_dev)); 1642 age_stop(sc); 1643 return (error); 1644 } 1645 age_init_rr_ring(sc); 1646 age_init_tx_ring(sc); 1647 age_init_cmb_block(sc); 1648 age_init_smb_block(sc); 1649 1650 /* Reprogram the station address. */ 1651 memcpy(eaddr, CLLADDR(ifp->if_sadl), sizeof(eaddr)); 1652 CSR_WRITE_4(sc, AGE_PAR0, 1653 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1654 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 1655 1656 /* Set descriptor base addresses. */ 1657 paddr = sc->age_rdata.age_tx_ring_paddr; 1658 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 1659 paddr = sc->age_rdata.age_rx_ring_paddr; 1660 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 1661 paddr = sc->age_rdata.age_rr_ring_paddr; 1662 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 1663 paddr = sc->age_rdata.age_tx_ring_paddr; 1664 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 1665 paddr = sc->age_rdata.age_cmb_block_paddr; 1666 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1667 paddr = sc->age_rdata.age_smb_block_paddr; 1668 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1669 1670 /* Set Rx/Rx return descriptor counter. */ 1671 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 1672 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 1673 DESC_RRD_CNT_MASK) | 1674 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 1675 1676 /* Set Tx descriptor counter. */ 1677 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 1678 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 1679 1680 /* Tell hardware that we're ready to load descriptors. */ 1681 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 1682 1683 /* 1684 * Initialize mailbox register. 1685 * Updated producer/consumer index information is exchanged 1686 * through this mailbox register. However Tx producer and 1687 * Rx return consumer/Rx producer are all shared such that 1688 * it's hard to separate code path between Tx and Rx without 1689 * locking. If L1 hardware have a separate mail box register 1690 * for Tx and Rx consumer/producer management we could have 1691 * indepent Tx/Rx handler which in turn Rx handler could have 1692 * been run without any locking. 1693 */ 1694 AGE_COMMIT_MBOX(sc); 1695 1696 /* Configure IPG/IFG parameters. */ 1697 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 1698 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 1699 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1700 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1701 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 1702 1703 /* Set parameters for half-duplex media. */ 1704 CSR_WRITE_4(sc, AGE_HDPX_CFG, 1705 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1706 HDPX_CFG_LCOL_MASK) | 1707 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1708 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1709 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1710 HDPX_CFG_ABEBT_MASK) | 1711 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1712 HDPX_CFG_JAMIPG_MASK)); 1713 1714 /* Configure interrupt moderation timer. */ 1715 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 1716 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 1717 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 1718 reg &= ~MASTER_MTIMER_ENB; 1719 if (AGE_USECS(sc->age_int_mod) == 0) 1720 reg &= ~MASTER_ITIMER_ENB; 1721 else 1722 reg |= MASTER_ITIMER_ENB; 1723 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 1724 if (agedebug) 1725 printf("%s: interrupt moderation is %d us.\n", 1726 device_xname(sc->sc_dev), sc->age_int_mod); 1727 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 1728 1729 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 1730 if (ifp->if_mtu < ETHERMTU) 1731 sc->age_max_frame_size = ETHERMTU; 1732 else 1733 sc->age_max_frame_size = ifp->if_mtu; 1734 sc->age_max_frame_size += ETHER_HDR_LEN + 1735 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 1736 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 1737 1738 /* Configure jumbo frame. */ 1739 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 1740 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 1741 (((fsize / sizeof(uint64_t)) << 1742 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 1743 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 1744 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 1745 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 1746 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 1747 1748 /* Configure flow-control parameters. From Linux. */ 1749 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 1750 /* 1751 * Magic workaround for old-L1. 1752 * Don't know which hw revision requires this magic. 1753 */ 1754 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1755 /* 1756 * Another magic workaround for flow-control mode 1757 * change. From Linux. 1758 */ 1759 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1760 } 1761 /* 1762 * TODO 1763 * Should understand pause parameter relationships between FIFO 1764 * size and number of Rx descriptors and Rx return descriptors. 1765 * 1766 * Magic parameters came from Linux. 1767 */ 1768 switch (sc->age_chip_rev) { 1769 case 0x8001: 1770 case 0x9001: 1771 case 0x9002: 1772 case 0x9003: 1773 rxf_hi = AGE_RX_RING_CNT / 16; 1774 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 1775 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 1776 rrd_lo = AGE_RR_RING_CNT / 16; 1777 break; 1778 default: 1779 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 1780 rxf_lo = reg / 16; 1781 if (rxf_lo < 192) 1782 rxf_lo = 192; 1783 rxf_hi = (reg * 7) / 8; 1784 if (rxf_hi < rxf_lo) 1785 rxf_hi = rxf_lo + 16; 1786 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 1787 rrd_lo = reg / 8; 1788 rrd_hi = (reg * 7) / 8; 1789 if (rrd_lo < 2) 1790 rrd_lo = 2; 1791 if (rrd_hi < rrd_lo) 1792 rrd_hi = rrd_lo + 3; 1793 break; 1794 } 1795 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 1796 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 1797 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 1798 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 1799 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 1800 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 1801 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 1802 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 1803 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 1804 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 1805 1806 /* Configure RxQ. */ 1807 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1808 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 1809 RXQ_CFG_RD_BURST_MASK) | 1810 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 1811 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 1812 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 1813 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 1814 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1815 1816 /* Configure TxQ. */ 1817 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1818 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1819 TXQ_CFG_TPD_BURST_MASK) | 1820 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 1821 TXQ_CFG_TX_FIFO_BURST_MASK) | 1822 ((TXQ_CFG_TPD_FETCH_DEFAULT << 1823 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 1824 TXQ_CFG_ENB); 1825 1826 /* Configure DMA parameters. */ 1827 CSR_WRITE_4(sc, AGE_DMA_CFG, 1828 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 1829 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 1830 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 1831 1832 /* Configure CMB DMA write threshold. */ 1833 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 1834 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 1835 CMB_WR_THRESH_RRD_MASK) | 1836 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 1837 CMB_WR_THRESH_TPD_MASK)); 1838 1839 /* Set CMB/SMB timer and enable them. */ 1840 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 1841 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 1842 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 1843 1844 /* Request SMB updates for every seconds. */ 1845 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 1846 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 1847 1848 /* 1849 * Disable all WOL bits as WOL can interfere normal Rx 1850 * operation. 1851 */ 1852 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1853 1854 /* 1855 * Configure Tx/Rx MACs. 1856 * - Auto-padding for short frames. 1857 * - Enable CRC generation. 1858 * Start with full-duplex/1000Mbps media. Actual reconfiguration 1859 * of MAC is followed after link establishment. 1860 */ 1861 CSR_WRITE_4(sc, AGE_MAC_CFG, 1862 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 1863 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 1864 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1865 MAC_CFG_PREAMBLE_MASK)); 1866 1867 /* Set up the receive filter. */ 1868 age_rxfilter(sc); 1869 age_rxvlan(sc); 1870 1871 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1872 reg |= MAC_CFG_RXCSUM_ENB; 1873 1874 /* Ack all pending interrupts and clear it. */ 1875 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 1876 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 1877 1878 /* Finally enable Tx/Rx MAC. */ 1879 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 1880 1881 sc->age_flags &= ~AGE_FLAG_LINK; 1882 1883 /* Switch to the current media. */ 1884 mii = &sc->sc_miibus; 1885 mii_mediachg(mii); 1886 1887 callout_schedule(&sc->sc_tick_ch, hz); 1888 1889 ifp->if_flags |= IFF_RUNNING; 1890 ifp->if_flags &= ~IFF_OACTIVE; 1891 1892 return (0); 1893 } 1894 1895 static void 1896 age_stop(struct age_softc *sc) 1897 { 1898 struct ifnet *ifp = &sc->sc_ec.ec_if; 1899 struct age_txdesc *txd; 1900 struct age_rxdesc *rxd; 1901 uint32_t reg; 1902 int i; 1903 1904 callout_stop(&sc->sc_tick_ch); 1905 1906 /* 1907 * Mark the interface down and cancel the watchdog timer. 1908 */ 1909 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1910 ifp->if_timer = 0; 1911 1912 sc->age_flags &= ~AGE_FLAG_LINK; 1913 1914 /* 1915 * Disable interrupts. 1916 */ 1917 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 1918 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 1919 1920 /* Stop CMB/SMB updates. */ 1921 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 1922 1923 /* Stop Rx/Tx MAC. */ 1924 age_stop_rxmac(sc); 1925 age_stop_txmac(sc); 1926 1927 /* Stop DMA. */ 1928 CSR_WRITE_4(sc, AGE_DMA_CFG, 1929 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 1930 1931 /* Stop TxQ/RxQ. */ 1932 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1933 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 1934 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1935 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 1936 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1937 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1938 break; 1939 DELAY(10); 1940 } 1941 if (i == 0) 1942 printf("%s: stopping Rx/Tx MACs timed out(0x%08x)!\n", 1943 device_xname(sc->sc_dev), reg); 1944 1945 /* Reclaim Rx buffers that have been processed. */ 1946 if (sc->age_cdata.age_rxhead != NULL) 1947 m_freem(sc->age_cdata.age_rxhead); 1948 AGE_RXCHAIN_RESET(sc); 1949 1950 /* 1951 * Free RX and TX mbufs still in the queues. 1952 */ 1953 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1954 rxd = &sc->age_cdata.age_rxdesc[i]; 1955 if (rxd->rx_m != NULL) { 1956 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1957 m_freem(rxd->rx_m); 1958 rxd->rx_m = NULL; 1959 } 1960 } 1961 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1962 txd = &sc->age_cdata.age_txdesc[i]; 1963 if (txd->tx_m != NULL) { 1964 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1965 m_freem(txd->tx_m); 1966 txd->tx_m = NULL; 1967 } 1968 } 1969 } 1970 1971 static void 1972 age_stats_update(struct age_softc *sc) 1973 { 1974 struct ifnet *ifp = &sc->sc_ec.ec_if; 1975 struct age_stats *stat; 1976 struct smb *smb; 1977 1978 stat = &sc->age_stat; 1979 1980 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 1981 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1982 1983 smb = sc->age_rdata.age_smb_block; 1984 if (smb->updated == 0) 1985 return; 1986 1987 /* Rx stats. */ 1988 stat->rx_frames += smb->rx_frames; 1989 stat->rx_bcast_frames += smb->rx_bcast_frames; 1990 stat->rx_mcast_frames += smb->rx_mcast_frames; 1991 stat->rx_pause_frames += smb->rx_pause_frames; 1992 stat->rx_control_frames += smb->rx_control_frames; 1993 stat->rx_crcerrs += smb->rx_crcerrs; 1994 stat->rx_lenerrs += smb->rx_lenerrs; 1995 stat->rx_bytes += smb->rx_bytes; 1996 stat->rx_runts += smb->rx_runts; 1997 stat->rx_fragments += smb->rx_fragments; 1998 stat->rx_pkts_64 += smb->rx_pkts_64; 1999 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2000 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2001 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2002 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2003 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2004 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2005 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2006 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2007 stat->rx_desc_oflows += smb->rx_desc_oflows; 2008 stat->rx_alignerrs += smb->rx_alignerrs; 2009 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2010 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2011 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2012 2013 /* Tx stats. */ 2014 stat->tx_frames += smb->tx_frames; 2015 stat->tx_bcast_frames += smb->tx_bcast_frames; 2016 stat->tx_mcast_frames += smb->tx_mcast_frames; 2017 stat->tx_pause_frames += smb->tx_pause_frames; 2018 stat->tx_excess_defer += smb->tx_excess_defer; 2019 stat->tx_control_frames += smb->tx_control_frames; 2020 stat->tx_deferred += smb->tx_deferred; 2021 stat->tx_bytes += smb->tx_bytes; 2022 stat->tx_pkts_64 += smb->tx_pkts_64; 2023 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2024 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2025 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2026 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2027 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2028 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2029 stat->tx_single_colls += smb->tx_single_colls; 2030 stat->tx_multi_colls += smb->tx_multi_colls; 2031 stat->tx_late_colls += smb->tx_late_colls; 2032 stat->tx_excess_colls += smb->tx_excess_colls; 2033 stat->tx_underrun += smb->tx_underrun; 2034 stat->tx_desc_underrun += smb->tx_desc_underrun; 2035 stat->tx_lenerrs += smb->tx_lenerrs; 2036 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2037 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2038 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2039 2040 /* Update counters in ifnet. */ 2041 ifp->if_opackets += smb->tx_frames; 2042 2043 ifp->if_collisions += smb->tx_single_colls + 2044 smb->tx_multi_colls + smb->tx_late_colls + 2045 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 2046 2047 ifp->if_oerrors += smb->tx_excess_colls + 2048 smb->tx_late_colls + smb->tx_underrun + 2049 smb->tx_pkts_truncated; 2050 2051 ifp->if_ipackets += smb->rx_frames; 2052 2053 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2054 smb->rx_runts + smb->rx_pkts_truncated + 2055 smb->rx_fifo_oflows + smb->rx_desc_oflows + 2056 smb->rx_alignerrs; 2057 2058 /* Update done, clear. */ 2059 smb->updated = 0; 2060 2061 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2062 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2063 } 2064 2065 static void 2066 age_stop_txmac(struct age_softc *sc) 2067 { 2068 uint32_t reg; 2069 int i; 2070 2071 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2072 if ((reg & MAC_CFG_TX_ENB) != 0) { 2073 reg &= ~MAC_CFG_TX_ENB; 2074 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2075 } 2076 /* Stop Tx DMA engine. */ 2077 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2078 if ((reg & DMA_CFG_RD_ENB) != 0) { 2079 reg &= ~DMA_CFG_RD_ENB; 2080 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2081 } 2082 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2083 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2084 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2085 break; 2086 DELAY(10); 2087 } 2088 if (i == 0) 2089 printf("%s: stopping TxMAC timeout!\n", device_xname(sc->sc_dev)); 2090 } 2091 2092 static void 2093 age_stop_rxmac(struct age_softc *sc) 2094 { 2095 uint32_t reg; 2096 int i; 2097 2098 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2099 if ((reg & MAC_CFG_RX_ENB) != 0) { 2100 reg &= ~MAC_CFG_RX_ENB; 2101 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2102 } 2103 /* Stop Rx DMA engine. */ 2104 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2105 if ((reg & DMA_CFG_WR_ENB) != 0) { 2106 reg &= ~DMA_CFG_WR_ENB; 2107 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2108 } 2109 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2110 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2111 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2112 break; 2113 DELAY(10); 2114 } 2115 if (i == 0) 2116 printf("%s: stopping RxMAC timeout!\n", device_xname(sc->sc_dev)); 2117 } 2118 2119 static void 2120 age_init_tx_ring(struct age_softc *sc) 2121 { 2122 struct age_ring_data *rd; 2123 struct age_txdesc *txd; 2124 int i; 2125 2126 sc->age_cdata.age_tx_prod = 0; 2127 sc->age_cdata.age_tx_cons = 0; 2128 sc->age_cdata.age_tx_cnt = 0; 2129 2130 rd = &sc->age_rdata; 2131 memset(rd->age_tx_ring, 0, AGE_TX_RING_SZ); 2132 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2133 txd = &sc->age_cdata.age_txdesc[i]; 2134 txd->tx_desc = &rd->age_tx_ring[i]; 2135 txd->tx_m = NULL; 2136 } 2137 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 2138 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2139 } 2140 2141 static int 2142 age_init_rx_ring(struct age_softc *sc) 2143 { 2144 struct age_ring_data *rd; 2145 struct age_rxdesc *rxd; 2146 int i; 2147 2148 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 2149 rd = &sc->age_rdata; 2150 memset(rd->age_rx_ring, 0, AGE_RX_RING_SZ); 2151 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2152 rxd = &sc->age_cdata.age_rxdesc[i]; 2153 rxd->rx_m = NULL; 2154 rxd->rx_desc = &rd->age_rx_ring[i]; 2155 if (age_newbuf(sc, rxd, 1) != 0) 2156 return (ENOBUFS); 2157 } 2158 2159 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 0, 2160 sc->age_cdata.age_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2161 2162 return (0); 2163 } 2164 2165 static void 2166 age_init_rr_ring(struct age_softc *sc) 2167 { 2168 struct age_ring_data *rd; 2169 2170 sc->age_cdata.age_rr_cons = 0; 2171 AGE_RXCHAIN_RESET(sc); 2172 2173 rd = &sc->age_rdata; 2174 memset(rd->age_rr_ring, 0, AGE_RR_RING_SZ); 2175 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 2176 sc->age_cdata.age_rr_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2177 } 2178 2179 static void 2180 age_init_cmb_block(struct age_softc *sc) 2181 { 2182 struct age_ring_data *rd; 2183 2184 rd = &sc->age_rdata; 2185 memset(rd->age_cmb_block, 0, AGE_CMB_BLOCK_SZ); 2186 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 2187 sc->age_cdata.age_cmb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2188 } 2189 2190 static void 2191 age_init_smb_block(struct age_softc *sc) 2192 { 2193 struct age_ring_data *rd; 2194 2195 rd = &sc->age_rdata; 2196 memset(rd->age_smb_block, 0, AGE_SMB_BLOCK_SZ); 2197 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2198 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2199 } 2200 2201 static int 2202 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd, int init) 2203 { 2204 struct rx_desc *desc; 2205 struct mbuf *m; 2206 bus_dmamap_t map; 2207 int error; 2208 2209 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 2210 if (m == NULL) 2211 return (ENOBUFS); 2212 MCLGET(m, init ? M_WAITOK : M_DONTWAIT); 2213 if (!(m->m_flags & M_EXT)) { 2214 m_freem(m); 2215 return (ENOBUFS); 2216 } 2217 2218 m->m_len = m->m_pkthdr.len = MCLBYTES; 2219 m_adj(m, PAGE_SIZE); 2220 2221 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2222 sc->age_cdata.age_rx_sparemap, m, BUS_DMA_NOWAIT); 2223 2224 if (error != 0) { 2225 if (!error) { 2226 bus_dmamap_unload(sc->sc_dmat, 2227 sc->age_cdata.age_rx_sparemap); 2228 error = EFBIG; 2229 printf("%s: too many segments?!\n", 2230 device_xname(sc->sc_dev)); 2231 } 2232 m_freem(m); 2233 2234 if (init) 2235 printf("%s: can't load RX mbuf\n", device_xname(sc->sc_dev)); 2236 return (error); 2237 } 2238 2239 if (rxd->rx_m != NULL) { 2240 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2241 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2242 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2243 } 2244 map = rxd->rx_dmamap; 2245 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 2246 sc->age_cdata.age_rx_sparemap = map; 2247 rxd->rx_m = m; 2248 2249 desc = rxd->rx_desc; 2250 desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 2251 desc->len = 2252 htole32((rxd->rx_dmamap->dm_segs[0].ds_len & AGE_RD_LEN_MASK) << 2253 AGE_RD_LEN_SHIFT); 2254 2255 return (0); 2256 } 2257 2258 static void 2259 age_rxvlan(struct age_softc *sc) 2260 { 2261 uint32_t reg; 2262 2263 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2264 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2265 if (sc->sc_ec.ec_capabilities & ETHERCAP_VLAN_HWTAGGING) 2266 reg |= MAC_CFG_VLAN_TAG_STRIP; 2267 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2268 } 2269 2270 static void 2271 age_rxfilter(struct age_softc *sc) 2272 { 2273 struct ethercom *ec = &sc->sc_ec; 2274 struct ifnet *ifp = &sc->sc_ec.ec_if; 2275 struct ether_multi *enm; 2276 struct ether_multistep step; 2277 uint32_t crc; 2278 uint32_t mchash[2]; 2279 uint32_t rxcfg; 2280 2281 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 2282 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2283 2284 if (ifp->if_flags & IFF_BROADCAST) 2285 rxcfg |= MAC_CFG_BCAST; 2286 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 2287 if (ifp->if_flags & IFF_PROMISC) 2288 rxcfg |= MAC_CFG_PROMISC; 2289 if (ifp->if_flags & IFF_ALLMULTI) 2290 rxcfg |= MAC_CFG_ALLMULTI; 2291 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF); 2292 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF); 2293 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 2294 return; 2295 } 2296 2297 /* Program new filter. */ 2298 memset(mchash, 0, sizeof(mchash)); 2299 2300 ETHER_FIRST_MULTI(step, ec, enm); 2301 while (enm != NULL) { 2302 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 2303 enm->enm_addrlo), ETHER_ADDR_LEN); 2304 2305 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2306 ETHER_NEXT_MULTI(step, enm); 2307 } 2308 2309 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 2310 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 2311 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 2312 } 2313
Indexes created Mon Sep 29 21:09:56 GMT 2025