if_age.c revision 1.21
1 /* $NetBSD: if_age.c,v 1.21 2009/02/11 16:15:59 cegger Exp $ */ 2 /* $OpenBSD: if_age.c,v 1.1 2009/01/16 05:00:34 kevlo Exp $ */ 3 4 /*- 5 * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: if_age.c,v 1.21 2009/02/11 16:15:59 cegger Exp $"); 35 36 #include "bpfilter.h" 37 #include "vlan.h" 38 39 #include <sys/param.h> 40 #include <sys/proc.h> 41 #include <sys/endian.h> 42 #include <sys/systm.h> 43 #include <sys/types.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/queue.h> 47 #include <sys/kernel.h> 48 #include <sys/device.h> 49 #include <sys/callout.h> 50 #include <sys/socket.h> 51 52 #include <net/if.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #ifdef INET 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/in_var.h> 61 #include <netinet/ip.h> 62 #endif 63 64 #include <net/if_types.h> 65 #include <net/if_vlanvar.h> 66 67 #if NBPFILTER > 0 68 #include <net/bpf.h> 69 #endif 70 71 #include <sys/rnd.h> 72 73 #include <dev/mii/mii.h> 74 #include <dev/mii/miivar.h> 75 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/pcidevs.h> 79 80 #include <dev/pci/if_agereg.h> 81 82 static int age_match(device_t, cfdata_t, void *); 83 static void age_attach(device_t, device_t, void *); 84 static int age_detach(device_t, int); 85 86 static bool age_resume(device_t PMF_FN_PROTO); 87 88 static int age_miibus_readreg(device_t, int, int); 89 static void age_miibus_writereg(device_t, int, int, int); 90 static void age_miibus_statchg(device_t); 91 92 static int age_init(struct ifnet *); 93 static int age_ioctl(struct ifnet *, u_long, void *); 94 static void age_start(struct ifnet *); 95 static void age_watchdog(struct ifnet *); 96 static void age_mediastatus(struct ifnet *, struct ifmediareq *); 97 static int age_mediachange(struct ifnet *); 98 99 static int age_intr(void *); 100 static int age_read_vpd_word(struct age_softc *, uint32_t, uint32_t, uint32_t *); 101 static int age_dma_alloc(struct age_softc *); 102 static void age_dma_free(struct age_softc *); 103 static void age_get_macaddr(struct age_softc *, uint8_t[]); 104 static void age_phy_reset(struct age_softc *); 105 106 static int age_encap(struct age_softc *, struct mbuf **); 107 static void age_init_tx_ring(struct age_softc *); 108 static int age_init_rx_ring(struct age_softc *); 109 static void age_init_rr_ring(struct age_softc *); 110 static void age_init_cmb_block(struct age_softc *); 111 static void age_init_smb_block(struct age_softc *); 112 static int age_newbuf(struct age_softc *, struct age_rxdesc *, int); 113 static void age_mac_config(struct age_softc *); 114 static void age_txintr(struct age_softc *, int); 115 static void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 116 static void age_rxintr(struct age_softc *, int); 117 static void age_tick(void *); 118 static void age_reset(struct age_softc *); 119 static void age_stop(struct ifnet *, int); 120 static void age_stats_update(struct age_softc *); 121 static void age_stop_txmac(struct age_softc *); 122 static void age_stop_rxmac(struct age_softc *); 123 static void age_rxvlan(struct age_softc *sc); 124 static void age_rxfilter(struct age_softc *); 125 126 CFATTACH_DECL_NEW(age, sizeof(struct age_softc), 127 age_match, age_attach, age_detach, NULL); 128 129 int agedebug = 0; 130 #define DPRINTF(x) do { if (agedebug) printf x; } while (0) 131 132 #define ETHER_ALIGN 2 133 #define AGE_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 134 135 static int 136 age_match(device_t dev, cfdata_t match, void *aux) 137 { 138 struct pci_attach_args *pa = aux; 139 140 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && 141 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_GIGA); 142 } 143 144 static void 145 age_attach(device_t parent, device_t self, void *aux) 146 { 147 struct age_softc *sc = device_private(self); 148 struct pci_attach_args *pa = aux; 149 pci_intr_handle_t ih; 150 const char *intrstr; 151 struct ifnet *ifp = &sc->sc_ec.ec_if; 152 pcireg_t memtype; 153 int error = 0; 154 155 aprint_naive("\n"); 156 aprint_normal(": Attansic/Atheros L1 Gigabit Ethernet\n"); 157 158 sc->sc_dev = self; 159 sc->sc_dmat = pa->pa_dmat; 160 sc->sc_pct = pa->pa_pc; 161 sc->sc_pcitag = pa->pa_tag; 162 163 /* 164 * Allocate IO memory 165 */ 166 memtype = pci_mapreg_type(sc->sc_pct, sc->sc_pcitag, AGE_PCIR_BAR); 167 switch (memtype) { 168 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 169 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 170 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 171 break; 172 default: 173 aprint_error_dev(self, "invalid base address register\n"); 174 break; 175 } 176 177 if (pci_mapreg_map(pa, AGE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 178 &sc->sc_mem_bh, NULL, &sc->sc_mem_size) != 0) { 179 aprint_error_dev(self, "could not map mem space\n"); 180 return; 181 } 182 183 if (pci_intr_map(pa, &ih) != 0) { 184 aprint_error_dev(self, "could not map interrupt\n"); 185 return; 186 } 187 188 /* 189 * Allocate IRQ 190 */ 191 intrstr = pci_intr_string(sc->sc_pct, ih); 192 sc->sc_irq_handle = pci_intr_establish(sc->sc_pct, ih, IPL_NET, 193 age_intr, sc); 194 if (sc->sc_irq_handle == NULL) { 195 aprint_error_dev(self, "could not establish interrupt"); 196 if (intrstr != NULL) 197 aprint_error(" at %s", intrstr); 198 aprint_error("\n"); 199 return; 200 } 201 aprint_normal_dev(self, "%s\n", intrstr); 202 203 /* Set PHY address. */ 204 sc->age_phyaddr = AGE_PHY_ADDR; 205 206 /* Reset PHY. */ 207 age_phy_reset(sc); 208 209 /* Reset the ethernet controller. */ 210 age_reset(sc); 211 212 /* Get PCI and chip id/revision. */ 213 sc->age_rev = PCI_REVISION(pa->pa_class); 214 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 215 MASTER_CHIP_REV_SHIFT; 216 217 aprint_debug_dev(self, "PCI device revision : 0x%04x\n", sc->age_rev); 218 aprint_debug_dev(self, "Chip id/revision : 0x%04x\n", sc->age_chip_rev); 219 220 if (agedebug) { 221 aprint_debug_dev(self, "%d Tx FIFO, %d Rx FIFO\n", 222 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 223 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 224 } 225 226 /* Set max allowable DMA size. */ 227 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 228 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 229 230 /* Allocate DMA stuffs */ 231 error = age_dma_alloc(sc); 232 if (error) 233 goto fail; 234 235 callout_init(&sc->sc_tick_ch, 0); 236 callout_setfunc(&sc->sc_tick_ch, age_tick, sc); 237 238 /* Load station address. */ 239 age_get_macaddr(sc, sc->sc_enaddr); 240 241 aprint_normal_dev(self, "Ethernet address %s\n", 242 ether_sprintf(sc->sc_enaddr)); 243 244 ifp->if_softc = sc; 245 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 246 ifp->if_init = age_init; 247 ifp->if_ioctl = age_ioctl; 248 ifp->if_start = age_start; 249 ifp->if_stop = age_stop; 250 ifp->if_watchdog = age_watchdog; 251 ifp->if_baudrate = IF_Gbps(1); 252 IFQ_SET_MAXLEN(&ifp->if_snd, AGE_TX_RING_CNT - 1); 253 IFQ_SET_READY(&ifp->if_snd); 254 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 255 256 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 257 258 #ifdef AGE_CHECKSUM 259 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 260 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 261 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 262 #endif 263 264 #if NVLAN > 0 265 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 266 #endif 267 268 /* Set up MII bus. */ 269 sc->sc_miibus.mii_ifp = ifp; 270 sc->sc_miibus.mii_readreg = age_miibus_readreg; 271 sc->sc_miibus.mii_writereg = age_miibus_writereg; 272 sc->sc_miibus.mii_statchg = age_miibus_statchg; 273 274 sc->sc_ec.ec_mii = &sc->sc_miibus; 275 ifmedia_init(&sc->sc_miibus.mii_media, 0, age_mediachange, 276 age_mediastatus); 277 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 278 MII_OFFSET_ANY, 0); 279 280 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 281 aprint_error_dev(self, "no PHY found!\n"); 282 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 283 0, NULL); 284 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 285 } else 286 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 287 288 if_attach(ifp); 289 ether_ifattach(ifp, sc->sc_enaddr); 290 291 if (!pmf_device_register(self, NULL, age_resume)) 292 aprint_error_dev(self, "couldn't establish power handler\n"); 293 else 294 pmf_class_network_register(self, ifp); 295 296 return; 297 298 fail: 299 if (sc->sc_irq_handle != NULL) { 300 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 301 sc->sc_irq_handle = NULL; 302 } 303 } 304 305 static int 306 age_detach(device_t self, int flags) 307 { 308 struct age_softc *sc = device_private(self); 309 struct ifnet *ifp = &sc->sc_ec.ec_if; 310 int s; 311 312 s = splnet(); 313 age_stop(ifp, 0); 314 splx(s); 315 316 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 317 318 /* Delete all remaining media. */ 319 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 320 321 ether_ifdetach(ifp); 322 if_detach(ifp); 323 age_dma_free(sc); 324 325 if (sc->sc_irq_handle != NULL) { 326 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 327 sc->sc_irq_handle = NULL; 328 } 329 330 return 0; 331 } 332 333 /* 334 * Read a PHY register on the MII of the L1. 335 */ 336 static int 337 age_miibus_readreg(device_t dev, int phy, int reg) 338 { 339 struct age_softc *sc = device_private(dev); 340 uint32_t v; 341 int i; 342 343 if (phy != sc->age_phyaddr) 344 return 0; 345 346 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 347 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 348 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 349 DELAY(1); 350 v = CSR_READ_4(sc, AGE_MDIO); 351 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 352 break; 353 } 354 355 if (i == 0) { 356 printf("%s: phy read timeout: phy %d, reg %d\n", 357 device_xname(sc->sc_dev), phy, reg); 358 return 0; 359 } 360 361 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 362 } 363 364 /* 365 * Write a PHY register on the MII of the L1. 366 */ 367 static void 368 age_miibus_writereg(device_t dev, int phy, int reg, int val) 369 { 370 struct age_softc *sc = device_private(dev); 371 uint32_t v; 372 int i; 373 374 if (phy != sc->age_phyaddr) 375 return; 376 377 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 378 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 379 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 380 381 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 382 DELAY(1); 383 v = CSR_READ_4(sc, AGE_MDIO); 384 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 385 break; 386 } 387 388 if (i == 0) { 389 printf("%s: phy write timeout: phy %d, reg %d\n", 390 device_xname(sc->sc_dev), phy, reg); 391 } 392 } 393 394 /* 395 * Callback from MII layer when media changes. 396 */ 397 static void 398 age_miibus_statchg(device_t dev) 399 { 400 struct age_softc *sc = device_private(dev); 401 struct ifnet *ifp = &sc->sc_ec.ec_if; 402 struct mii_data *mii; 403 404 if ((ifp->if_flags & IFF_RUNNING) == 0) 405 return; 406 407 mii = &sc->sc_miibus; 408 409 sc->age_flags &= ~AGE_FLAG_LINK; 410 if ((mii->mii_media_status & IFM_AVALID) != 0) { 411 switch (IFM_SUBTYPE(mii->mii_media_active)) { 412 case IFM_10_T: 413 case IFM_100_TX: 414 case IFM_1000_T: 415 sc->age_flags |= AGE_FLAG_LINK; 416 break; 417 default: 418 break; 419 } 420 } 421 422 /* Stop Rx/Tx MACs. */ 423 age_stop_rxmac(sc); 424 age_stop_txmac(sc); 425 426 /* Program MACs with resolved speed/duplex/flow-control. */ 427 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 428 uint32_t reg; 429 430 age_mac_config(sc); 431 reg = CSR_READ_4(sc, AGE_MAC_CFG); 432 /* Restart DMA engine and Tx/Rx MAC. */ 433 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 434 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 435 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 436 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 437 } 438 } 439 440 /* 441 * Get the current interface media status. 442 */ 443 static void 444 age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 445 { 446 struct age_softc *sc = ifp->if_softc; 447 struct mii_data *mii = &sc->sc_miibus; 448 449 mii_pollstat(mii); 450 ifmr->ifm_status = mii->mii_media_status; 451 ifmr->ifm_active = mii->mii_media_active; 452 } 453 454 /* 455 * Set hardware to newly-selected media. 456 */ 457 static int 458 age_mediachange(struct ifnet *ifp) 459 { 460 struct age_softc *sc = ifp->if_softc; 461 struct mii_data *mii = &sc->sc_miibus; 462 int error; 463 464 if (mii->mii_instance != 0) { 465 struct mii_softc *miisc; 466 467 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 468 mii_phy_reset(miisc); 469 } 470 error = mii_mediachg(mii); 471 472 return error; 473 } 474 475 static int 476 age_intr(void *arg) 477 { 478 struct age_softc *sc = arg; 479 struct ifnet *ifp = &sc->sc_ec.ec_if; 480 struct cmb *cmb; 481 uint32_t status; 482 483 status = CSR_READ_4(sc, AGE_INTR_STATUS); 484 if (status == 0 || (status & AGE_INTRS) == 0) 485 return 0; 486 487 cmb = sc->age_rdata.age_cmb_block; 488 if (cmb == NULL) 489 return 0; 490 491 /* Disable interrupts. */ 492 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 493 494 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 495 sc->age_cdata.age_cmb_block_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 496 status = le32toh(cmb->intr_status); 497 if ((status & AGE_INTRS) == 0) 498 goto back; 499 500 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 501 TPD_CONS_SHIFT; 502 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 503 RRD_PROD_SHIFT; 504 505 /* Let hardware know CMB was served. */ 506 cmb->intr_status = 0; 507 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 508 sc->age_cdata.age_cmb_block_map->dm_mapsize, 509 BUS_DMASYNC_PREWRITE); 510 511 if (ifp->if_flags & IFF_RUNNING) { 512 if (status & INTR_CMB_RX) 513 age_rxintr(sc, sc->age_rr_prod); 514 515 if (status & INTR_CMB_TX) 516 age_txintr(sc, sc->age_tpd_cons); 517 518 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 519 if (status & INTR_DMA_RD_TO_RST) 520 printf("%s: DMA read error! -- resetting\n", 521 device_xname(sc->sc_dev)); 522 if (status & INTR_DMA_WR_TO_RST) 523 printf("%s: DMA write error! -- resetting\n", 524 device_xname(sc->sc_dev)); 525 age_init(ifp); 526 } 527 528 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 529 age_start(ifp); 530 531 if (status & INTR_SMB) 532 age_stats_update(sc); 533 } 534 535 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 536 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 537 sc->age_cdata.age_cmb_block_map->dm_mapsize, 538 BUS_DMASYNC_POSTREAD); 539 540 back: 541 /* Re-enable interrupts. */ 542 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 543 544 return 1; 545 } 546 547 static int 548 age_read_vpd_word(struct age_softc *sc, uint32_t vpdc, uint32_t offset, 549 uint32_t *word) 550 { 551 int i; 552 pcireg_t rv; 553 554 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_VPD_ADDRESS(vpdc), 555 offset << PCI_VPD_ADDRESS_SHIFT); 556 for (i = AGE_TIMEOUT; i > 0; i--) { 557 DELAY(10); 558 rv = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 559 PCI_VPD_ADDRESS(vpdc)); 560 if ((rv & PCI_VPD_OPFLAG) == PCI_VPD_OPFLAG) 561 break; 562 } 563 if (i == 0) { 564 printf("%s: VPD read timeout!\n", device_xname(sc->sc_dev)); 565 *word = 0; 566 return ETIMEDOUT; 567 } 568 569 *word = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_VPD_DATAREG(vpdc)); 570 return 0; 571 } 572 573 static void 574 age_get_macaddr(struct age_softc *sc, uint8_t eaddr[]) 575 { 576 uint32_t ea[2], off, reg, word; 577 int vpd_error, match, vpdc; 578 579 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 580 if ((reg & SPI_VPD_ENB) != 0) { 581 /* Get VPD stored in TWSI EEPROM. */ 582 reg &= ~SPI_VPD_ENB; 583 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 584 } 585 586 vpd_error = 0; 587 ea[0] = ea[1] = 0; 588 if ((vpd_error = pci_get_capability(sc->sc_pct, sc->sc_pcitag, 589 PCI_CAP_VPD, &vpdc, NULL))) { 590 /* 591 * PCI VPD capability exists, but it seems that it's 592 * not in the standard form as stated in PCI VPD 593 * specification such that driver could not use 594 * pci_get_vpd_readonly(9) with keyword 'NA'. 595 * Search VPD data starting at address 0x0100. The data 596 * should be used as initializers to set AGE_PAR0, 597 * AGE_PAR1 register including other PCI configuration 598 * registers. 599 */ 600 word = 0; 601 match = 0; 602 reg = 0; 603 for (off = AGE_VPD_REG_CONF_START; off < AGE_VPD_REG_CONF_END; 604 off += sizeof(uint32_t)) { 605 vpd_error = age_read_vpd_word(sc, vpdc, off, &word); 606 if (vpd_error != 0) 607 break; 608 if (match != 0) { 609 switch (reg) { 610 case AGE_PAR0: 611 ea[0] = word; 612 break; 613 case AGE_PAR1: 614 ea[1] = word; 615 break; 616 default: 617 break; 618 } 619 match = 0; 620 } else if ((word & 0xFF) == AGE_VPD_REG_CONF_SIG) { 621 match = 1; 622 reg = word >> 16; 623 } else 624 break; 625 } 626 if (off >= AGE_VPD_REG_CONF_END) 627 vpd_error = ENOENT; 628 if (vpd_error == 0) { 629 /* 630 * Don't blindly trust ethernet address obtained 631 * from VPD. Check whether ethernet address is 632 * valid one. Otherwise fall-back to reading 633 * PAR register. 634 */ 635 ea[1] &= 0xFFFF; 636 if ((ea[0] == 0 && ea[1] == 0) || 637 (ea[0] == 0xFFFFFFFF && ea[1] == 0xFFFF)) { 638 if (agedebug) 639 printf("%s: invalid ethernet address " 640 "returned from VPD.\n", 641 device_xname(sc->sc_dev)); 642 vpd_error = EINVAL; 643 } 644 } 645 if (vpd_error != 0 && (agedebug)) 646 printf("%s: VPD access failure!\n", 647 device_xname(sc->sc_dev)); 648 } else { 649 if (agedebug) 650 printf("%s: PCI VPD capability not found!\n", 651 device_xname(sc->sc_dev)); 652 } 653 654 /* 655 * It seems that L1 also provides a way to extract ethernet 656 * address via SPI flash interface. Because SPI flash memory 657 * device of different vendors vary in their instruction 658 * codes for read ID instruction, it's very hard to get 659 * instructions codes without detailed information for the 660 * flash memory device used on ethernet controller. To simplify 661 * code, just read AGE_PAR0/AGE_PAR1 register to get ethernet 662 * address which is supposed to be set by hardware during 663 * power on reset. 664 */ 665 if (vpd_error != 0) { 666 /* 667 * VPD is mapped to SPI flash memory or BIOS set it. 668 */ 669 ea[0] = CSR_READ_4(sc, AGE_PAR0); 670 ea[1] = CSR_READ_4(sc, AGE_PAR1); 671 } 672 673 ea[1] &= 0xFFFF; 674 eaddr[0] = (ea[1] >> 8) & 0xFF; 675 eaddr[1] = (ea[1] >> 0) & 0xFF; 676 eaddr[2] = (ea[0] >> 24) & 0xFF; 677 eaddr[3] = (ea[0] >> 16) & 0xFF; 678 eaddr[4] = (ea[0] >> 8) & 0xFF; 679 eaddr[5] = (ea[0] >> 0) & 0xFF; 680 } 681 682 static void 683 age_phy_reset(struct age_softc *sc) 684 { 685 /* Reset PHY. */ 686 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 687 DELAY(1000); 688 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 689 DELAY(1000); 690 } 691 692 static int 693 age_dma_alloc(struct age_softc *sc) 694 { 695 struct age_txdesc *txd; 696 struct age_rxdesc *rxd; 697 int nsegs, error, i; 698 699 /* 700 * Create DMA stuffs for TX ring 701 */ 702 error = bus_dmamap_create(sc->sc_dmat, AGE_TX_RING_SZ, 1, 703 AGE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_tx_ring_map); 704 if (error) 705 return ENOBUFS; 706 707 /* Allocate DMA'able memory for TX ring */ 708 error = bus_dmamem_alloc(sc->sc_dmat, AGE_TX_RING_SZ, 709 ETHER_ALIGN, 0, &sc->age_rdata.age_tx_ring_seg, 1, 710 &nsegs, BUS_DMA_WAITOK); 711 if (error) { 712 printf("%s: could not allocate DMA'able memory for Tx ring, " 713 "error = %i\n", device_xname(sc->sc_dev), error); 714 return error; 715 } 716 717 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_tx_ring_seg, 718 nsegs, AGE_TX_RING_SZ, (void **)&sc->age_rdata.age_tx_ring, 719 BUS_DMA_NOWAIT); 720 if (error) 721 return ENOBUFS; 722 723 memset(sc->age_rdata.age_tx_ring, 0, AGE_TX_RING_SZ); 724 725 /* Load the DMA map for Tx ring. */ 726 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 727 sc->age_rdata.age_tx_ring, AGE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 728 if (error) { 729 printf("%s: could not load DMA'able memory for Tx ring, " 730 "error = %i\n", device_xname(sc->sc_dev), error); 731 bus_dmamem_free(sc->sc_dmat, 732 (bus_dma_segment_t *)&sc->age_rdata.age_tx_ring, 1); 733 return error; 734 } 735 736 sc->age_rdata.age_tx_ring_paddr = 737 sc->age_cdata.age_tx_ring_map->dm_segs[0].ds_addr; 738 739 /* 740 * Create DMA stuffs for RX ring 741 */ 742 error = bus_dmamap_create(sc->sc_dmat, AGE_RX_RING_SZ, 1, 743 AGE_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_ring_map); 744 if (error) 745 return ENOBUFS; 746 747 /* Allocate DMA'able memory for RX ring */ 748 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RX_RING_SZ, 749 ETHER_ALIGN, 0, &sc->age_rdata.age_rx_ring_seg, 1, 750 &nsegs, BUS_DMA_WAITOK); 751 if (error) { 752 printf("%s: could not allocate DMA'able memory for Rx ring, " 753 "error = %i.\n", device_xname(sc->sc_dev), error); 754 return error; 755 } 756 757 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rx_ring_seg, 758 nsegs, AGE_RX_RING_SZ, (void **)&sc->age_rdata.age_rx_ring, 759 BUS_DMA_NOWAIT); 760 if (error) 761 return ENOBUFS; 762 763 memset(sc->age_rdata.age_rx_ring, 0, AGE_RX_RING_SZ); 764 765 /* Load the DMA map for Rx ring. */ 766 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 767 sc->age_rdata.age_rx_ring, AGE_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 768 if (error) { 769 printf("%s: could not load DMA'able memory for Rx ring, " 770 "error = %i.\n", device_xname(sc->sc_dev), error); 771 bus_dmamem_free(sc->sc_dmat, 772 (bus_dma_segment_t *)sc->age_rdata.age_rx_ring, 1); 773 return error; 774 } 775 776 sc->age_rdata.age_rx_ring_paddr = 777 sc->age_cdata.age_rx_ring_map->dm_segs[0].ds_addr; 778 779 /* 780 * Create DMA stuffs for RX return ring 781 */ 782 error = bus_dmamap_create(sc->sc_dmat, AGE_RR_RING_SZ, 1, 783 AGE_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rr_ring_map); 784 if (error) 785 return ENOBUFS; 786 787 /* Allocate DMA'able memory for RX return ring */ 788 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RR_RING_SZ, 789 ETHER_ALIGN, 0, &sc->age_rdata.age_rr_ring_seg, 1, 790 &nsegs, BUS_DMA_WAITOK); 791 if (error) { 792 printf("%s: could not allocate DMA'able memory for Rx " 793 "return ring, error = %i.\n", 794 device_xname(sc->sc_dev), error); 795 return error; 796 } 797 798 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rr_ring_seg, 799 nsegs, AGE_RR_RING_SZ, (void **)&sc->age_rdata.age_rr_ring, 800 BUS_DMA_NOWAIT); 801 if (error) 802 return ENOBUFS; 803 804 memset(sc->age_rdata.age_rr_ring, 0, AGE_RR_RING_SZ); 805 806 /* Load the DMA map for Rx return ring. */ 807 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 808 sc->age_rdata.age_rr_ring, AGE_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 809 if (error) { 810 printf("%s: could not load DMA'able memory for Rx return ring, " 811 "error = %i\n", device_xname(sc->sc_dev), error); 812 bus_dmamem_free(sc->sc_dmat, 813 (bus_dma_segment_t *)&sc->age_rdata.age_rr_ring, 1); 814 return error; 815 } 816 817 sc->age_rdata.age_rr_ring_paddr = 818 sc->age_cdata.age_rr_ring_map->dm_segs[0].ds_addr; 819 820 /* 821 * Create DMA stuffs for CMB block 822 */ 823 error = bus_dmamap_create(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 1, 824 AGE_CMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 825 &sc->age_cdata.age_cmb_block_map); 826 if (error) 827 return ENOBUFS; 828 829 /* Allocate DMA'able memory for CMB block */ 830 error = bus_dmamem_alloc(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 831 ETHER_ALIGN, 0, &sc->age_rdata.age_cmb_block_seg, 1, 832 &nsegs, BUS_DMA_WAITOK); 833 if (error) { 834 printf("%s: could not allocate DMA'able memory for " 835 "CMB block, error = %i\n", device_xname(sc->sc_dev), error); 836 return error; 837 } 838 839 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_cmb_block_seg, 840 nsegs, AGE_CMB_BLOCK_SZ, (void **)&sc->age_rdata.age_cmb_block, 841 BUS_DMA_NOWAIT); 842 if (error) 843 return ENOBUFS; 844 845 memset(sc->age_rdata.age_cmb_block, 0, AGE_CMB_BLOCK_SZ); 846 847 /* Load the DMA map for CMB block. */ 848 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 849 sc->age_rdata.age_cmb_block, AGE_CMB_BLOCK_SZ, NULL, 850 BUS_DMA_WAITOK); 851 if (error) { 852 printf("%s: could not load DMA'able memory for CMB block, " 853 "error = %i\n", device_xname(sc->sc_dev), error); 854 bus_dmamem_free(sc->sc_dmat, 855 (bus_dma_segment_t *)&sc->age_rdata.age_cmb_block, 1); 856 return error; 857 } 858 859 sc->age_rdata.age_cmb_block_paddr = 860 sc->age_cdata.age_cmb_block_map->dm_segs[0].ds_addr; 861 862 /* 863 * Create DMA stuffs for SMB block 864 */ 865 error = bus_dmamap_create(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 1, 866 AGE_SMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 867 &sc->age_cdata.age_smb_block_map); 868 if (error) 869 return ENOBUFS; 870 871 /* Allocate DMA'able memory for SMB block */ 872 error = bus_dmamem_alloc(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 873 ETHER_ALIGN, 0, &sc->age_rdata.age_smb_block_seg, 1, 874 &nsegs, BUS_DMA_WAITOK); 875 if (error) { 876 printf("%s: could not allocate DMA'able memory for " 877 "SMB block, error = %i\n", device_xname(sc->sc_dev), error); 878 return error; 879 } 880 881 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_smb_block_seg, 882 nsegs, AGE_SMB_BLOCK_SZ, (void **)&sc->age_rdata.age_smb_block, 883 BUS_DMA_NOWAIT); 884 if (error) 885 return ENOBUFS; 886 887 memset(sc->age_rdata.age_smb_block, 0, AGE_SMB_BLOCK_SZ); 888 889 /* Load the DMA map for SMB block */ 890 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 891 sc->age_rdata.age_smb_block, AGE_SMB_BLOCK_SZ, NULL, 892 BUS_DMA_WAITOK); 893 if (error) { 894 printf("%s: could not load DMA'able memory for SMB block, " 895 "error = %i\n", device_xname(sc->sc_dev), error); 896 bus_dmamem_free(sc->sc_dmat, 897 (bus_dma_segment_t *)&sc->age_rdata.age_smb_block, 1); 898 return error; 899 } 900 901 sc->age_rdata.age_smb_block_paddr = 902 sc->age_cdata.age_smb_block_map->dm_segs[0].ds_addr; 903 904 /* Create DMA maps for Tx buffers. */ 905 for (i = 0; i < AGE_TX_RING_CNT; i++) { 906 txd = &sc->age_cdata.age_txdesc[i]; 907 txd->tx_m = NULL; 908 txd->tx_dmamap = NULL; 909 error = bus_dmamap_create(sc->sc_dmat, AGE_TSO_MAXSIZE, 910 AGE_MAXTXSEGS, AGE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 911 &txd->tx_dmamap); 912 if (error) { 913 printf("%s: could not create Tx dmamap, error = %i.\n", 914 device_xname(sc->sc_dev), error); 915 return error; 916 } 917 } 918 919 /* Create DMA maps for Rx buffers. */ 920 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 921 BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_sparemap); 922 if (error) { 923 printf("%s: could not create spare Rx dmamap, error = %i.\n", 924 device_xname(sc->sc_dev), error); 925 return error; 926 } 927 for (i = 0; i < AGE_RX_RING_CNT; i++) { 928 rxd = &sc->age_cdata.age_rxdesc[i]; 929 rxd->rx_m = NULL; 930 rxd->rx_dmamap = NULL; 931 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 932 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 933 if (error) { 934 printf("%s: could not create Rx dmamap, error = %i.\n", 935 device_xname(sc->sc_dev), error); 936 return error; 937 } 938 } 939 940 return 0; 941 } 942 943 static void 944 age_dma_free(struct age_softc *sc) 945 { 946 struct age_txdesc *txd; 947 struct age_rxdesc *rxd; 948 int i; 949 950 /* Tx buffers */ 951 for (i = 0; i < AGE_TX_RING_CNT; i++) { 952 txd = &sc->age_cdata.age_txdesc[i]; 953 if (txd->tx_dmamap != NULL) { 954 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 955 txd->tx_dmamap = NULL; 956 } 957 } 958 /* Rx buffers */ 959 for (i = 0; i < AGE_RX_RING_CNT; i++) { 960 rxd = &sc->age_cdata.age_rxdesc[i]; 961 if (rxd->rx_dmamap != NULL) { 962 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 963 rxd->rx_dmamap = NULL; 964 } 965 } 966 if (sc->age_cdata.age_rx_sparemap != NULL) { 967 bus_dmamap_destroy(sc->sc_dmat, sc->age_cdata.age_rx_sparemap); 968 sc->age_cdata.age_rx_sparemap = NULL; 969 } 970 971 /* Tx ring. */ 972 if (sc->age_cdata.age_tx_ring_map != NULL) 973 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_tx_ring_map); 974 if (sc->age_cdata.age_tx_ring_map != NULL && 975 sc->age_rdata.age_tx_ring != NULL) 976 bus_dmamem_free(sc->sc_dmat, 977 (bus_dma_segment_t *)sc->age_rdata.age_tx_ring, 1); 978 sc->age_rdata.age_tx_ring = NULL; 979 sc->age_cdata.age_tx_ring_map = NULL; 980 981 /* Rx ring. */ 982 if (sc->age_cdata.age_rx_ring_map != NULL) 983 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rx_ring_map); 984 if (sc->age_cdata.age_rx_ring_map != NULL && 985 sc->age_rdata.age_rx_ring != NULL) 986 bus_dmamem_free(sc->sc_dmat, 987 (bus_dma_segment_t *)sc->age_rdata.age_rx_ring, 1); 988 sc->age_rdata.age_rx_ring = NULL; 989 sc->age_cdata.age_rx_ring_map = NULL; 990 991 /* Rx return ring. */ 992 if (sc->age_cdata.age_rr_ring_map != NULL) 993 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rr_ring_map); 994 if (sc->age_cdata.age_rr_ring_map != NULL && 995 sc->age_rdata.age_rr_ring != NULL) 996 bus_dmamem_free(sc->sc_dmat, 997 (bus_dma_segment_t *)sc->age_rdata.age_rr_ring, 1); 998 sc->age_rdata.age_rr_ring = NULL; 999 sc->age_cdata.age_rr_ring_map = NULL; 1000 1001 /* CMB block */ 1002 if (sc->age_cdata.age_cmb_block_map != NULL) 1003 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_cmb_block_map); 1004 if (sc->age_cdata.age_cmb_block_map != NULL && 1005 sc->age_rdata.age_cmb_block != NULL) 1006 bus_dmamem_free(sc->sc_dmat, 1007 (bus_dma_segment_t *)sc->age_rdata.age_cmb_block, 1); 1008 sc->age_rdata.age_cmb_block = NULL; 1009 sc->age_cdata.age_cmb_block_map = NULL; 1010 1011 /* SMB block */ 1012 if (sc->age_cdata.age_smb_block_map != NULL) 1013 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_smb_block_map); 1014 if (sc->age_cdata.age_smb_block_map != NULL && 1015 sc->age_rdata.age_smb_block != NULL) 1016 bus_dmamem_free(sc->sc_dmat, 1017 (bus_dma_segment_t *)sc->age_rdata.age_smb_block, 1); 1018 sc->age_rdata.age_smb_block = NULL; 1019 sc->age_cdata.age_smb_block_map = NULL; 1020 } 1021 1022 static void 1023 age_start(struct ifnet *ifp) 1024 { 1025 struct age_softc *sc = ifp->if_softc; 1026 struct mbuf *m_head; 1027 int enq; 1028 1029 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1030 return; 1031 1032 enq = 0; 1033 for (;;) { 1034 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1035 if (m_head == NULL) 1036 break; 1037 1038 /* 1039 * Pack the data into the transmit ring. If we 1040 * don't have room, set the OACTIVE flag and wait 1041 * for the NIC to drain the ring. 1042 */ 1043 if (age_encap(sc, &m_head)) { 1044 if (m_head == NULL) 1045 break; 1046 ifp->if_flags |= IFF_OACTIVE; 1047 break; 1048 } 1049 enq = 1; 1050 1051 #if NBPFILTER > 0 1052 /* 1053 * If there's a BPF listener, bounce a copy of this frame 1054 * to him. 1055 */ 1056 if (ifp->if_bpf != NULL) 1057 bpf_mtap(ifp->if_bpf, m_head); 1058 #endif 1059 } 1060 1061 if (enq) { 1062 /* Update mbox. */ 1063 AGE_COMMIT_MBOX(sc); 1064 /* Set a timeout in case the chip goes out to lunch. */ 1065 ifp->if_timer = AGE_TX_TIMEOUT; 1066 } 1067 } 1068 1069 static void 1070 age_watchdog(struct ifnet *ifp) 1071 { 1072 struct age_softc *sc = ifp->if_softc; 1073 1074 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1075 printf("%s: watchdog timeout (missed link)\n", 1076 device_xname(sc->sc_dev)); 1077 ifp->if_oerrors++; 1078 age_init(ifp); 1079 return; 1080 } 1081 1082 if (sc->age_cdata.age_tx_cnt == 0) { 1083 printf("%s: watchdog timeout (missed Tx interrupts) " 1084 "-- recovering\n", device_xname(sc->sc_dev)); 1085 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1086 age_start(ifp); 1087 return; 1088 } 1089 1090 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1091 ifp->if_oerrors++; 1092 age_init(ifp); 1093 1094 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1095 age_start(ifp); 1096 } 1097 1098 static int 1099 age_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1100 { 1101 struct age_softc *sc = ifp->if_softc; 1102 int s, error; 1103 1104 s = splnet(); 1105 1106 error = ether_ioctl(ifp, cmd, data); 1107 if (error == ENETRESET) { 1108 if (ifp->if_flags & IFF_RUNNING) 1109 age_rxfilter(sc); 1110 error = 0; 1111 } 1112 1113 splx(s); 1114 return error; 1115 } 1116 1117 static void 1118 age_mac_config(struct age_softc *sc) 1119 { 1120 struct mii_data *mii; 1121 uint32_t reg; 1122 1123 mii = &sc->sc_miibus; 1124 1125 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1126 reg &= ~MAC_CFG_FULL_DUPLEX; 1127 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1128 reg &= ~MAC_CFG_SPEED_MASK; 1129 1130 /* Reprogram MAC with resolved speed/duplex. */ 1131 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1132 case IFM_10_T: 1133 case IFM_100_TX: 1134 reg |= MAC_CFG_SPEED_10_100; 1135 break; 1136 case IFM_1000_T: 1137 reg |= MAC_CFG_SPEED_1000; 1138 break; 1139 } 1140 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1141 reg |= MAC_CFG_FULL_DUPLEX; 1142 #ifdef notyet 1143 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1144 reg |= MAC_CFG_TX_FC; 1145 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1146 reg |= MAC_CFG_RX_FC; 1147 #endif 1148 } 1149 1150 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1151 } 1152 1153 static bool 1154 age_resume(device_t dv PMF_FN_ARGS) 1155 { 1156 struct age_softc *sc = device_private(dv); 1157 uint16_t cmd; 1158 1159 /* 1160 * Clear INTx emulation disable for hardware that 1161 * is set in resume event. From Linux. 1162 */ 1163 cmd = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 1164 if ((cmd & PCI_COMMAND_INTERRUPT_DISABLE) != 0) { 1165 cmd &= ~PCI_COMMAND_INTERRUPT_DISABLE; 1166 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 1167 PCI_COMMAND_STATUS_REG, cmd); 1168 } 1169 1170 return true; 1171 } 1172 1173 static int 1174 age_encap(struct age_softc *sc, struct mbuf **m_head) 1175 { 1176 struct age_txdesc *txd, *txd_last; 1177 struct tx_desc *desc; 1178 struct mbuf *m; 1179 bus_dmamap_t map; 1180 uint32_t cflags, poff, vtag; 1181 int error, i, nsegs, prod; 1182 struct m_tag *mtag; 1183 1184 m = *m_head; 1185 cflags = vtag = 0; 1186 poff = 0; 1187 1188 prod = sc->age_cdata.age_tx_prod; 1189 txd = &sc->age_cdata.age_txdesc[prod]; 1190 txd_last = txd; 1191 map = txd->tx_dmamap; 1192 1193 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1194 1195 if (error == EFBIG) { 1196 error = 0; 1197 1198 MGETHDR(m, M_DONTWAIT, MT_DATA); 1199 if (m == NULL) { 1200 printf("%s: can't defrag TX mbuf\n", 1201 device_xname(sc->sc_dev)); 1202 m_freem(*m_head); 1203 *m_head = NULL; 1204 return ENOBUFS; 1205 } 1206 1207 M_COPY_PKTHDR(m, *m_head); 1208 if ((*m_head)->m_pkthdr.len > MHLEN) { 1209 MCLGET(m, M_DONTWAIT); 1210 if (!(m->m_flags & M_EXT)) { 1211 m_freem(*m_head); 1212 m_freem(m); 1213 *m_head = NULL; 1214 return ENOBUFS; 1215 } 1216 } 1217 m_copydata(*m_head, 0, (*m_head)->m_pkthdr.len, 1218 mtod(m, void *)); 1219 m_freem(*m_head); 1220 m->m_len = m->m_pkthdr.len; 1221 *m_head = m; 1222 1223 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1224 BUS_DMA_NOWAIT); 1225 1226 if (error != 0) { 1227 printf("%s: could not load defragged TX mbuf\n", 1228 device_xname(sc->sc_dev)); 1229 if (!error) { 1230 bus_dmamap_unload(sc->sc_dmat, map); 1231 error = EFBIG; 1232 } 1233 m_freem(*m_head); 1234 *m_head = NULL; 1235 return error; 1236 } 1237 } else if (error) { 1238 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 1239 return error; 1240 } 1241 1242 nsegs = map->dm_nsegs; 1243 1244 if (nsegs == 0) { 1245 m_freem(*m_head); 1246 *m_head = NULL; 1247 return EIO; 1248 } 1249 1250 /* Check descriptor overrun. */ 1251 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1252 bus_dmamap_unload(sc->sc_dmat, map); 1253 return ENOBUFS; 1254 } 1255 1256 m = *m_head; 1257 /* Configure Tx IP/TCP/UDP checksum offload. */ 1258 if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1259 cflags |= AGE_TD_CSUM; 1260 if ((m->m_pkthdr.csum_flags & M_CSUM_TCPv4) != 0) 1261 cflags |= AGE_TD_TCPCSUM; 1262 if ((m->m_pkthdr.csum_flags & M_CSUM_UDPv4) != 0) 1263 cflags |= AGE_TD_UDPCSUM; 1264 /* Set checksum start offset. */ 1265 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1266 } 1267 1268 #if NVLAN > 0 1269 /* Configure VLAN hardware tag insertion. */ 1270 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m))) { 1271 vtag = AGE_TX_VLAN_TAG(htons(VLAN_TAG_VALUE(mtag))); 1272 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1273 cflags |= AGE_TD_INSERT_VLAN_TAG; 1274 } 1275 #endif 1276 1277 desc = NULL; 1278 for (i = 0; i < nsegs; i++) { 1279 desc = &sc->age_rdata.age_tx_ring[prod]; 1280 desc->addr = htole64(map->dm_segs[i].ds_addr); 1281 desc->len = 1282 htole32(AGE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 1283 desc->flags = htole32(cflags); 1284 sc->age_cdata.age_tx_cnt++; 1285 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1286 } 1287 1288 /* Update producer index. */ 1289 sc->age_cdata.age_tx_prod = prod; 1290 1291 /* Set EOP on the last descriptor. */ 1292 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1293 desc = &sc->age_rdata.age_tx_ring[prod]; 1294 desc->flags |= htole32(AGE_TD_EOP); 1295 1296 /* Swap dmamap of the first and the last. */ 1297 txd = &sc->age_cdata.age_txdesc[prod]; 1298 map = txd_last->tx_dmamap; 1299 txd_last->tx_dmamap = txd->tx_dmamap; 1300 txd->tx_dmamap = map; 1301 txd->tx_m = m; 1302 1303 /* Sync descriptors. */ 1304 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1305 BUS_DMASYNC_PREWRITE); 1306 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1307 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1308 1309 return 0; 1310 } 1311 1312 static void 1313 age_txintr(struct age_softc *sc, int tpd_cons) 1314 { 1315 struct ifnet *ifp = &sc->sc_ec.ec_if; 1316 struct age_txdesc *txd; 1317 int cons, prog; 1318 1319 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1320 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1321 1322 /* 1323 * Go through our Tx list and free mbufs for those 1324 * frames which have been transmitted. 1325 */ 1326 cons = sc->age_cdata.age_tx_cons; 1327 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 1328 if (sc->age_cdata.age_tx_cnt <= 0) 1329 break; 1330 prog++; 1331 ifp->if_flags &= ~IFF_OACTIVE; 1332 sc->age_cdata.age_tx_cnt--; 1333 txd = &sc->age_cdata.age_txdesc[cons]; 1334 /* 1335 * Clear Tx descriptors, it's not required but would 1336 * help debugging in case of Tx issues. 1337 */ 1338 txd->tx_desc->addr = 0; 1339 txd->tx_desc->len = 0; 1340 txd->tx_desc->flags = 0; 1341 1342 if (txd->tx_m == NULL) 1343 continue; 1344 /* Reclaim transmitted mbufs. */ 1345 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1346 m_freem(txd->tx_m); 1347 txd->tx_m = NULL; 1348 } 1349 1350 if (prog > 0) { 1351 sc->age_cdata.age_tx_cons = cons; 1352 1353 /* 1354 * Unarm watchdog timer only when there are no pending 1355 * Tx descriptors in queue. 1356 */ 1357 if (sc->age_cdata.age_tx_cnt == 0) 1358 ifp->if_timer = 0; 1359 1360 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1361 sc->age_cdata.age_tx_ring_map->dm_mapsize, 1362 BUS_DMASYNC_PREWRITE); 1363 } 1364 } 1365 1366 /* Receive a frame. */ 1367 static void 1368 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 1369 { 1370 struct ifnet *ifp = &sc->sc_ec.ec_if; 1371 struct age_rxdesc *rxd; 1372 struct rx_desc *desc; 1373 struct mbuf *mp, *m; 1374 uint32_t status, index, vtag; 1375 int count, nsegs, pktlen; 1376 int rx_cons; 1377 1378 status = le32toh(rxrd->flags); 1379 index = le32toh(rxrd->index); 1380 rx_cons = AGE_RX_CONS(index); 1381 nsegs = AGE_RX_NSEGS(index); 1382 1383 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 1384 if ((status & AGE_RRD_ERROR) != 0 && 1385 (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 1386 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) { 1387 /* 1388 * We want to pass the following frames to upper 1389 * layer regardless of error status of Rx return 1390 * ring. 1391 * 1392 * o IP/TCP/UDP checksum is bad. 1393 * o frame length and protocol specific length 1394 * does not match. 1395 */ 1396 sc->age_cdata.age_rx_cons += nsegs; 1397 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1398 return; 1399 } 1400 1401 pktlen = 0; 1402 for (count = 0; count < nsegs; count++, 1403 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 1404 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 1405 mp = rxd->rx_m; 1406 desc = rxd->rx_desc; 1407 /* Add a new receive buffer to the ring. */ 1408 if (age_newbuf(sc, rxd, 0) != 0) { 1409 ifp->if_iqdrops++; 1410 /* Reuse Rx buffers. */ 1411 if (sc->age_cdata.age_rxhead != NULL) { 1412 m_freem(sc->age_cdata.age_rxhead); 1413 AGE_RXCHAIN_RESET(sc); 1414 } 1415 break; 1416 } 1417 1418 /* The length of the first mbuf is computed last. */ 1419 if (count != 0) { 1420 mp->m_len = AGE_RX_BYTES(le32toh(desc->len)); 1421 pktlen += mp->m_len; 1422 } 1423 1424 /* Chain received mbufs. */ 1425 if (sc->age_cdata.age_rxhead == NULL) { 1426 sc->age_cdata.age_rxhead = mp; 1427 sc->age_cdata.age_rxtail = mp; 1428 } else { 1429 mp->m_flags &= ~M_PKTHDR; 1430 sc->age_cdata.age_rxprev_tail = 1431 sc->age_cdata.age_rxtail; 1432 sc->age_cdata.age_rxtail->m_next = mp; 1433 sc->age_cdata.age_rxtail = mp; 1434 } 1435 1436 if (count == nsegs - 1) { 1437 /* 1438 * It seems that L1 controller has no way 1439 * to tell hardware to strip CRC bytes. 1440 */ 1441 sc->age_cdata.age_rxlen -= ETHER_CRC_LEN; 1442 if (nsegs > 1) { 1443 /* Remove the CRC bytes in chained mbufs. */ 1444 pktlen -= ETHER_CRC_LEN; 1445 if (mp->m_len <= ETHER_CRC_LEN) { 1446 sc->age_cdata.age_rxtail = 1447 sc->age_cdata.age_rxprev_tail; 1448 sc->age_cdata.age_rxtail->m_len -= 1449 (ETHER_CRC_LEN - mp->m_len); 1450 sc->age_cdata.age_rxtail->m_next = NULL; 1451 m_freem(mp); 1452 } else { 1453 mp->m_len -= ETHER_CRC_LEN; 1454 } 1455 } 1456 1457 m = sc->age_cdata.age_rxhead; 1458 m->m_flags |= M_PKTHDR; 1459 m->m_pkthdr.rcvif = ifp; 1460 m->m_pkthdr.len = sc->age_cdata.age_rxlen; 1461 /* Set the first mbuf length. */ 1462 m->m_len = sc->age_cdata.age_rxlen - pktlen; 1463 1464 /* 1465 * Set checksum information. 1466 * It seems that L1 controller can compute partial 1467 * checksum. The partial checksum value can be used 1468 * to accelerate checksum computation for fragmented 1469 * TCP/UDP packets. Upper network stack already 1470 * takes advantage of the partial checksum value in 1471 * IP reassembly stage. But I'm not sure the 1472 * correctness of the partial hardware checksum 1473 * assistance due to lack of data sheet. If it is 1474 * proven to work on L1 I'll enable it. 1475 */ 1476 if (status & AGE_RRD_IPV4) { 1477 if (status & AGE_RRD_IPCSUM_NOK) 1478 m->m_pkthdr.csum_flags |= 1479 M_CSUM_IPv4_BAD; 1480 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 1481 (status & AGE_RRD_TCP_UDPCSUM_NOK)) { 1482 m->m_pkthdr.csum_flags |= 1483 M_CSUM_TCP_UDP_BAD; 1484 } 1485 /* 1486 * Don't mark bad checksum for TCP/UDP frames 1487 * as fragmented frames may always have set 1488 * bad checksummed bit of descriptor status. 1489 */ 1490 } 1491 #if NVLAN > 0 1492 /* Check for VLAN tagged frames. */ 1493 if (status & AGE_RRD_VLAN) { 1494 vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 1495 VLAN_INPUT_TAG(ifp, m, AGE_RX_VLAN_TAG(vtag), 1496 continue); 1497 } 1498 #endif 1499 1500 #if NBPFILTER > 0 1501 if (ifp->if_bpf) 1502 bpf_mtap(ifp->if_bpf, m); 1503 #endif 1504 /* Pass it on. */ 1505 ether_input(ifp, m); 1506 1507 /* Reset mbuf chains. */ 1508 AGE_RXCHAIN_RESET(sc); 1509 } 1510 } 1511 1512 if (count != nsegs) { 1513 sc->age_cdata.age_rx_cons += nsegs; 1514 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1515 } else 1516 sc->age_cdata.age_rx_cons = rx_cons; 1517 } 1518 1519 static void 1520 age_rxintr(struct age_softc *sc, int rr_prod) 1521 { 1522 struct rx_rdesc *rxrd; 1523 int rr_cons, nsegs, pktlen, prog; 1524 1525 rr_cons = sc->age_cdata.age_rr_cons; 1526 if (rr_cons == rr_prod) 1527 return; 1528 1529 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1530 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1531 BUS_DMASYNC_POSTREAD); 1532 1533 for (prog = 0; rr_cons != rr_prod; prog++) { 1534 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 1535 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 1536 if (nsegs == 0) 1537 break; 1538 /* 1539 * Check number of segments against received bytes 1540 * Non-matching value would indicate that hardware 1541 * is still trying to update Rx return descriptors. 1542 * I'm not sure whether this check is really needed. 1543 */ 1544 pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 1545 if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) / 1546 (MCLBYTES - ETHER_ALIGN))) 1547 break; 1548 1549 /* Received a frame. */ 1550 age_rxeof(sc, rxrd); 1551 1552 /* Clear return ring. */ 1553 rxrd->index = 0; 1554 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 1555 } 1556 1557 if (prog > 0) { 1558 /* Update the consumer index. */ 1559 sc->age_cdata.age_rr_cons = rr_cons; 1560 1561 /* Sync descriptors. */ 1562 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1563 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1564 BUS_DMASYNC_PREWRITE); 1565 1566 /* Notify hardware availability of new Rx buffers. */ 1567 AGE_COMMIT_MBOX(sc); 1568 } 1569 } 1570 1571 static void 1572 age_tick(void *xsc) 1573 { 1574 struct age_softc *sc = xsc; 1575 struct mii_data *mii = &sc->sc_miibus; 1576 int s; 1577 1578 s = splnet(); 1579 mii_tick(mii); 1580 splx(s); 1581 1582 callout_schedule(&sc->sc_tick_ch, hz); 1583 } 1584 1585 static void 1586 age_reset(struct age_softc *sc) 1587 { 1588 uint32_t reg; 1589 int i; 1590 1591 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 1592 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1593 DELAY(1); 1594 if ((CSR_READ_4(sc, AGE_MASTER_CFG) & MASTER_RESET) == 0) 1595 break; 1596 } 1597 if (i == 0) 1598 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 1599 1600 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1601 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1602 break; 1603 DELAY(10); 1604 } 1605 1606 if (i == 0) 1607 printf("%s: reset timeout(0x%08x)!\n", device_xname(sc->sc_dev), 1608 reg); 1609 1610 /* Initialize PCIe module. From Linux. */ 1611 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1612 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1613 } 1614 1615 static int 1616 age_init(struct ifnet *ifp) 1617 { 1618 struct age_softc *sc = ifp->if_softc; 1619 struct mii_data *mii; 1620 uint8_t eaddr[ETHER_ADDR_LEN]; 1621 bus_addr_t paddr; 1622 uint32_t reg, fsize; 1623 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 1624 int error; 1625 1626 /* 1627 * Cancel any pending I/O. 1628 */ 1629 age_stop(ifp, 0); 1630 1631 /* 1632 * Reset the chip to a known state. 1633 */ 1634 age_reset(sc); 1635 1636 /* Initialize descriptors. */ 1637 error = age_init_rx_ring(sc); 1638 if (error != 0) { 1639 printf("%s: no memory for Rx buffers.\n", device_xname(sc->sc_dev)); 1640 age_stop(ifp, 0); 1641 return error; 1642 } 1643 age_init_rr_ring(sc); 1644 age_init_tx_ring(sc); 1645 age_init_cmb_block(sc); 1646 age_init_smb_block(sc); 1647 1648 /* Reprogram the station address. */ 1649 memcpy(eaddr, CLLADDR(ifp->if_sadl), sizeof(eaddr)); 1650 CSR_WRITE_4(sc, AGE_PAR0, 1651 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1652 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 1653 1654 /* Set descriptor base addresses. */ 1655 paddr = sc->age_rdata.age_tx_ring_paddr; 1656 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 1657 paddr = sc->age_rdata.age_rx_ring_paddr; 1658 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 1659 paddr = sc->age_rdata.age_rr_ring_paddr; 1660 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 1661 paddr = sc->age_rdata.age_tx_ring_paddr; 1662 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 1663 paddr = sc->age_rdata.age_cmb_block_paddr; 1664 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1665 paddr = sc->age_rdata.age_smb_block_paddr; 1666 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1667 1668 /* Set Rx/Rx return descriptor counter. */ 1669 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 1670 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 1671 DESC_RRD_CNT_MASK) | 1672 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 1673 1674 /* Set Tx descriptor counter. */ 1675 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 1676 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 1677 1678 /* Tell hardware that we're ready to load descriptors. */ 1679 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 1680 1681 /* 1682 * Initialize mailbox register. 1683 * Updated producer/consumer index information is exchanged 1684 * through this mailbox register. However Tx producer and 1685 * Rx return consumer/Rx producer are all shared such that 1686 * it's hard to separate code path between Tx and Rx without 1687 * locking. If L1 hardware have a separate mail box register 1688 * for Tx and Rx consumer/producer management we could have 1689 * indepent Tx/Rx handler which in turn Rx handler could have 1690 * been run without any locking. 1691 */ 1692 AGE_COMMIT_MBOX(sc); 1693 1694 /* Configure IPG/IFG parameters. */ 1695 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 1696 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 1697 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1698 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1699 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 1700 1701 /* Set parameters for half-duplex media. */ 1702 CSR_WRITE_4(sc, AGE_HDPX_CFG, 1703 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1704 HDPX_CFG_LCOL_MASK) | 1705 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1706 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1707 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1708 HDPX_CFG_ABEBT_MASK) | 1709 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1710 HDPX_CFG_JAMIPG_MASK)); 1711 1712 /* Configure interrupt moderation timer. */ 1713 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 1714 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 1715 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 1716 reg &= ~MASTER_MTIMER_ENB; 1717 if (AGE_USECS(sc->age_int_mod) == 0) 1718 reg &= ~MASTER_ITIMER_ENB; 1719 else 1720 reg |= MASTER_ITIMER_ENB; 1721 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 1722 if (agedebug) 1723 printf("%s: interrupt moderation is %d us.\n", 1724 device_xname(sc->sc_dev), sc->age_int_mod); 1725 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 1726 1727 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 1728 if (ifp->if_mtu < ETHERMTU) 1729 sc->age_max_frame_size = ETHERMTU; 1730 else 1731 sc->age_max_frame_size = ifp->if_mtu; 1732 sc->age_max_frame_size += ETHER_HDR_LEN + 1733 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 1734 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 1735 1736 /* Configure jumbo frame. */ 1737 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 1738 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 1739 (((fsize / sizeof(uint64_t)) << 1740 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 1741 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 1742 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 1743 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 1744 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 1745 1746 /* Configure flow-control parameters. From Linux. */ 1747 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 1748 /* 1749 * Magic workaround for old-L1. 1750 * Don't know which hw revision requires this magic. 1751 */ 1752 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1753 /* 1754 * Another magic workaround for flow-control mode 1755 * change. From Linux. 1756 */ 1757 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1758 } 1759 /* 1760 * TODO 1761 * Should understand pause parameter relationships between FIFO 1762 * size and number of Rx descriptors and Rx return descriptors. 1763 * 1764 * Magic parameters came from Linux. 1765 */ 1766 switch (sc->age_chip_rev) { 1767 case 0x8001: 1768 case 0x9001: 1769 case 0x9002: 1770 case 0x9003: 1771 rxf_hi = AGE_RX_RING_CNT / 16; 1772 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 1773 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 1774 rrd_lo = AGE_RR_RING_CNT / 16; 1775 break; 1776 default: 1777 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 1778 rxf_lo = reg / 16; 1779 if (rxf_lo < 192) 1780 rxf_lo = 192; 1781 rxf_hi = (reg * 7) / 8; 1782 if (rxf_hi < rxf_lo) 1783 rxf_hi = rxf_lo + 16; 1784 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 1785 rrd_lo = reg / 8; 1786 rrd_hi = (reg * 7) / 8; 1787 if (rrd_lo < 2) 1788 rrd_lo = 2; 1789 if (rrd_hi < rrd_lo) 1790 rrd_hi = rrd_lo + 3; 1791 break; 1792 } 1793 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 1794 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 1795 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 1796 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 1797 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 1798 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 1799 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 1800 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 1801 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 1802 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 1803 1804 /* Configure RxQ. */ 1805 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1806 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 1807 RXQ_CFG_RD_BURST_MASK) | 1808 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 1809 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 1810 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 1811 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 1812 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1813 1814 /* Configure TxQ. */ 1815 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1816 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1817 TXQ_CFG_TPD_BURST_MASK) | 1818 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 1819 TXQ_CFG_TX_FIFO_BURST_MASK) | 1820 ((TXQ_CFG_TPD_FETCH_DEFAULT << 1821 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 1822 TXQ_CFG_ENB); 1823 1824 /* Configure DMA parameters. */ 1825 CSR_WRITE_4(sc, AGE_DMA_CFG, 1826 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 1827 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 1828 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 1829 1830 /* Configure CMB DMA write threshold. */ 1831 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 1832 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 1833 CMB_WR_THRESH_RRD_MASK) | 1834 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 1835 CMB_WR_THRESH_TPD_MASK)); 1836 1837 /* Set CMB/SMB timer and enable them. */ 1838 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 1839 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 1840 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 1841 1842 /* Request SMB updates for every seconds. */ 1843 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 1844 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 1845 1846 /* 1847 * Disable all WOL bits as WOL can interfere normal Rx 1848 * operation. 1849 */ 1850 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1851 1852 /* 1853 * Configure Tx/Rx MACs. 1854 * - Auto-padding for short frames. 1855 * - Enable CRC generation. 1856 * Start with full-duplex/1000Mbps media. Actual reconfiguration 1857 * of MAC is followed after link establishment. 1858 */ 1859 CSR_WRITE_4(sc, AGE_MAC_CFG, 1860 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 1861 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 1862 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1863 MAC_CFG_PREAMBLE_MASK)); 1864 1865 /* Set up the receive filter. */ 1866 age_rxfilter(sc); 1867 age_rxvlan(sc); 1868 1869 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1870 reg |= MAC_CFG_RXCSUM_ENB; 1871 1872 /* Ack all pending interrupts and clear it. */ 1873 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 1874 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 1875 1876 /* Finally enable Tx/Rx MAC. */ 1877 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 1878 1879 sc->age_flags &= ~AGE_FLAG_LINK; 1880 1881 /* Switch to the current media. */ 1882 mii = &sc->sc_miibus; 1883 mii_mediachg(mii); 1884 1885 callout_schedule(&sc->sc_tick_ch, hz); 1886 1887 ifp->if_flags |= IFF_RUNNING; 1888 ifp->if_flags &= ~IFF_OACTIVE; 1889 1890 return 0; 1891 } 1892 1893 static void 1894 age_stop(struct ifnet *ifp, int disable) 1895 { 1896 struct age_softc *sc = ifp->if_softc; 1897 struct age_txdesc *txd; 1898 struct age_rxdesc *rxd; 1899 uint32_t reg; 1900 int i; 1901 1902 callout_stop(&sc->sc_tick_ch); 1903 1904 /* 1905 * Mark the interface down and cancel the watchdog timer. 1906 */ 1907 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1908 ifp->if_timer = 0; 1909 1910 sc->age_flags &= ~AGE_FLAG_LINK; 1911 1912 mii_down(&sc->sc_miibus); 1913 1914 /* 1915 * Disable interrupts. 1916 */ 1917 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 1918 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 1919 1920 /* Stop CMB/SMB updates. */ 1921 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 1922 1923 /* Stop Rx/Tx MAC. */ 1924 age_stop_rxmac(sc); 1925 age_stop_txmac(sc); 1926 1927 /* Stop DMA. */ 1928 CSR_WRITE_4(sc, AGE_DMA_CFG, 1929 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 1930 1931 /* Stop TxQ/RxQ. */ 1932 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1933 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 1934 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1935 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 1936 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1937 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1938 break; 1939 DELAY(10); 1940 } 1941 if (i == 0) 1942 printf("%s: stopping Rx/Tx MACs timed out(0x%08x)!\n", 1943 device_xname(sc->sc_dev), reg); 1944 1945 /* Reclaim Rx buffers that have been processed. */ 1946 if (sc->age_cdata.age_rxhead != NULL) 1947 m_freem(sc->age_cdata.age_rxhead); 1948 AGE_RXCHAIN_RESET(sc); 1949 1950 /* 1951 * Free RX and TX mbufs still in the queues. 1952 */ 1953 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1954 rxd = &sc->age_cdata.age_rxdesc[i]; 1955 if (rxd->rx_m != NULL) { 1956 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1957 m_freem(rxd->rx_m); 1958 rxd->rx_m = NULL; 1959 } 1960 } 1961 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1962 txd = &sc->age_cdata.age_txdesc[i]; 1963 if (txd->tx_m != NULL) { 1964 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1965 m_freem(txd->tx_m); 1966 txd->tx_m = NULL; 1967 } 1968 } 1969 } 1970 1971 static void 1972 age_stats_update(struct age_softc *sc) 1973 { 1974 struct ifnet *ifp = &sc->sc_ec.ec_if; 1975 struct age_stats *stat; 1976 struct smb *smb; 1977 1978 stat = &sc->age_stat; 1979 1980 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 1981 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1982 1983 smb = sc->age_rdata.age_smb_block; 1984 if (smb->updated == 0) 1985 return; 1986 1987 /* Rx stats. */ 1988 stat->rx_frames += smb->rx_frames; 1989 stat->rx_bcast_frames += smb->rx_bcast_frames; 1990 stat->rx_mcast_frames += smb->rx_mcast_frames; 1991 stat->rx_pause_frames += smb->rx_pause_frames; 1992 stat->rx_control_frames += smb->rx_control_frames; 1993 stat->rx_crcerrs += smb->rx_crcerrs; 1994 stat->rx_lenerrs += smb->rx_lenerrs; 1995 stat->rx_bytes += smb->rx_bytes; 1996 stat->rx_runts += smb->rx_runts; 1997 stat->rx_fragments += smb->rx_fragments; 1998 stat->rx_pkts_64 += smb->rx_pkts_64; 1999 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2000 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2001 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2002 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2003 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2004 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2005 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2006 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2007 stat->rx_desc_oflows += smb->rx_desc_oflows; 2008 stat->rx_alignerrs += smb->rx_alignerrs; 2009 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2010 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2011 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2012 2013 /* Tx stats. */ 2014 stat->tx_frames += smb->tx_frames; 2015 stat->tx_bcast_frames += smb->tx_bcast_frames; 2016 stat->tx_mcast_frames += smb->tx_mcast_frames; 2017 stat->tx_pause_frames += smb->tx_pause_frames; 2018 stat->tx_excess_defer += smb->tx_excess_defer; 2019 stat->tx_control_frames += smb->tx_control_frames; 2020 stat->tx_deferred += smb->tx_deferred; 2021 stat->tx_bytes += smb->tx_bytes; 2022 stat->tx_pkts_64 += smb->tx_pkts_64; 2023 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2024 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2025 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2026 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2027 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2028 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2029 stat->tx_single_colls += smb->tx_single_colls; 2030 stat->tx_multi_colls += smb->tx_multi_colls; 2031 stat->tx_late_colls += smb->tx_late_colls; 2032 stat->tx_excess_colls += smb->tx_excess_colls; 2033 stat->tx_underrun += smb->tx_underrun; 2034 stat->tx_desc_underrun += smb->tx_desc_underrun; 2035 stat->tx_lenerrs += smb->tx_lenerrs; 2036 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2037 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2038 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2039 2040 /* Update counters in ifnet. */ 2041 ifp->if_opackets += smb->tx_frames; 2042 2043 ifp->if_collisions += smb->tx_single_colls + 2044 smb->tx_multi_colls + smb->tx_late_colls + 2045 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 2046 2047 ifp->if_oerrors += smb->tx_excess_colls + 2048 smb->tx_late_colls + smb->tx_underrun + 2049 smb->tx_pkts_truncated; 2050 2051 ifp->if_ipackets += smb->rx_frames; 2052 2053 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2054 smb->rx_runts + smb->rx_pkts_truncated + 2055 smb->rx_fifo_oflows + smb->rx_desc_oflows + 2056 smb->rx_alignerrs; 2057 2058 /* Update done, clear. */ 2059 smb->updated = 0; 2060 2061 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2062 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2063 } 2064 2065 static void 2066 age_stop_txmac(struct age_softc *sc) 2067 { 2068 uint32_t reg; 2069 int i; 2070 2071 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2072 if ((reg & MAC_CFG_TX_ENB) != 0) { 2073 reg &= ~MAC_CFG_TX_ENB; 2074 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2075 } 2076 /* Stop Tx DMA engine. */ 2077 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2078 if ((reg & DMA_CFG_RD_ENB) != 0) { 2079 reg &= ~DMA_CFG_RD_ENB; 2080 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2081 } 2082 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2083 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2084 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2085 break; 2086 DELAY(10); 2087 } 2088 if (i == 0) 2089 printf("%s: stopping TxMAC timeout!\n", device_xname(sc->sc_dev)); 2090 } 2091 2092 static void 2093 age_stop_rxmac(struct age_softc *sc) 2094 { 2095 uint32_t reg; 2096 int i; 2097 2098 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2099 if ((reg & MAC_CFG_RX_ENB) != 0) { 2100 reg &= ~MAC_CFG_RX_ENB; 2101 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2102 } 2103 /* Stop Rx DMA engine. */ 2104 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2105 if ((reg & DMA_CFG_WR_ENB) != 0) { 2106 reg &= ~DMA_CFG_WR_ENB; 2107 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2108 } 2109 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2110 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2111 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2112 break; 2113 DELAY(10); 2114 } 2115 if (i == 0) 2116 printf("%s: stopping RxMAC timeout!\n", device_xname(sc->sc_dev)); 2117 } 2118 2119 static void 2120 age_init_tx_ring(struct age_softc *sc) 2121 { 2122 struct age_ring_data *rd; 2123 struct age_txdesc *txd; 2124 int i; 2125 2126 sc->age_cdata.age_tx_prod = 0; 2127 sc->age_cdata.age_tx_cons = 0; 2128 sc->age_cdata.age_tx_cnt = 0; 2129 2130 rd = &sc->age_rdata; 2131 memset(rd->age_tx_ring, 0, AGE_TX_RING_SZ); 2132 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2133 txd = &sc->age_cdata.age_txdesc[i]; 2134 txd->tx_desc = &rd->age_tx_ring[i]; 2135 txd->tx_m = NULL; 2136 } 2137 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 2138 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2139 } 2140 2141 static int 2142 age_init_rx_ring(struct age_softc *sc) 2143 { 2144 struct age_ring_data *rd; 2145 struct age_rxdesc *rxd; 2146 int i; 2147 2148 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 2149 rd = &sc->age_rdata; 2150 memset(rd->age_rx_ring, 0, AGE_RX_RING_SZ); 2151 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2152 rxd = &sc->age_cdata.age_rxdesc[i]; 2153 rxd->rx_m = NULL; 2154 rxd->rx_desc = &rd->age_rx_ring[i]; 2155 if (age_newbuf(sc, rxd, 1) != 0) 2156 return ENOBUFS; 2157 } 2158 2159 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 0, 2160 sc->age_cdata.age_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2161 2162 return 0; 2163 } 2164 2165 static void 2166 age_init_rr_ring(struct age_softc *sc) 2167 { 2168 struct age_ring_data *rd; 2169 2170 sc->age_cdata.age_rr_cons = 0; 2171 AGE_RXCHAIN_RESET(sc); 2172 2173 rd = &sc->age_rdata; 2174 memset(rd->age_rr_ring, 0, AGE_RR_RING_SZ); 2175 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 2176 sc->age_cdata.age_rr_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2177 } 2178 2179 static void 2180 age_init_cmb_block(struct age_softc *sc) 2181 { 2182 struct age_ring_data *rd; 2183 2184 rd = &sc->age_rdata; 2185 memset(rd->age_cmb_block, 0, AGE_CMB_BLOCK_SZ); 2186 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 2187 sc->age_cdata.age_cmb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2188 } 2189 2190 static void 2191 age_init_smb_block(struct age_softc *sc) 2192 { 2193 struct age_ring_data *rd; 2194 2195 rd = &sc->age_rdata; 2196 memset(rd->age_smb_block, 0, AGE_SMB_BLOCK_SZ); 2197 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2198 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2199 } 2200 2201 static int 2202 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd, int init) 2203 { 2204 struct rx_desc *desc; 2205 struct mbuf *m; 2206 bus_dmamap_t map; 2207 int error; 2208 2209 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 2210 if (m == NULL) 2211 return ENOBUFS; 2212 MCLGET(m, init ? M_WAITOK : M_DONTWAIT); 2213 if (!(m->m_flags & M_EXT)) { 2214 m_freem(m); 2215 return ENOBUFS; 2216 } 2217 2218 m->m_len = m->m_pkthdr.len = MCLBYTES; 2219 m_adj(m, ETHER_ALIGN); 2220 2221 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2222 sc->age_cdata.age_rx_sparemap, m, BUS_DMA_NOWAIT); 2223 2224 if (error != 0) { 2225 if (!error) { 2226 bus_dmamap_unload(sc->sc_dmat, 2227 sc->age_cdata.age_rx_sparemap); 2228 error = EFBIG; 2229 printf("%s: too many segments?!\n", 2230 device_xname(sc->sc_dev)); 2231 } 2232 m_freem(m); 2233 2234 if (init) 2235 printf("%s: can't load RX mbuf\n", device_xname(sc->sc_dev)); 2236 return error; 2237 } 2238 2239 if (rxd->rx_m != NULL) { 2240 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2241 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2242 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2243 } 2244 map = rxd->rx_dmamap; 2245 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 2246 sc->age_cdata.age_rx_sparemap = map; 2247 rxd->rx_m = m; 2248 2249 desc = rxd->rx_desc; 2250 desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 2251 desc->len = 2252 htole32((rxd->rx_dmamap->dm_segs[0].ds_len & AGE_RD_LEN_MASK) << 2253 AGE_RD_LEN_SHIFT); 2254 2255 return 0; 2256 } 2257 2258 static void 2259 age_rxvlan(struct age_softc *sc) 2260 { 2261 uint32_t reg; 2262 2263 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2264 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2265 if (sc->sc_ec.ec_capabilities & ETHERCAP_VLAN_HWTAGGING) 2266 reg |= MAC_CFG_VLAN_TAG_STRIP; 2267 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2268 } 2269 2270 static void 2271 age_rxfilter(struct age_softc *sc) 2272 { 2273 struct ethercom *ec = &sc->sc_ec; 2274 struct ifnet *ifp = &sc->sc_ec.ec_if; 2275 struct ether_multi *enm; 2276 struct ether_multistep step; 2277 uint32_t crc; 2278 uint32_t mchash[2]; 2279 uint32_t rxcfg; 2280 2281 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 2282 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2283 2284 if (ifp->if_flags & IFF_BROADCAST) 2285 rxcfg |= MAC_CFG_BCAST; 2286 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 2287 if (ifp->if_flags & IFF_PROMISC) 2288 rxcfg |= MAC_CFG_PROMISC; 2289 if (ifp->if_flags & IFF_ALLMULTI) 2290 rxcfg |= MAC_CFG_ALLMULTI; 2291 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF); 2292 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF); 2293 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 2294 return; 2295 } 2296 2297 /* Program new filter. */ 2298 memset(mchash, 0, sizeof(mchash)); 2299 2300 ETHER_FIRST_MULTI(step, ec, enm); 2301 while (enm != NULL) { 2302 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 2303 enm->enm_addrlo), ETHER_ADDR_LEN); 2304 2305 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2306 ETHER_NEXT_MULTI(step, enm); 2307 } 2308 2309 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 2310 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 2311 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 2312 } 2313
Indexes created Mon Sep 29 21:09:56 GMT 2025