if_age.c revision 1.22
1 /* $NetBSD: if_age.c,v 1.22 2009/02/16 09:38:41 cegger Exp $ */ 2 /* $OpenBSD: if_age.c,v 1.1 2009/01/16 05:00:34 kevlo Exp $ */ 3 4 /*- 5 * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: if_age.c,v 1.22 2009/02/16 09:38:41 cegger Exp $"); 35 36 #include "bpfilter.h" 37 #include "vlan.h" 38 39 #include <sys/param.h> 40 #include <sys/proc.h> 41 #include <sys/endian.h> 42 #include <sys/systm.h> 43 #include <sys/types.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/queue.h> 47 #include <sys/kernel.h> 48 #include <sys/device.h> 49 #include <sys/callout.h> 50 #include <sys/socket.h> 51 52 #include <net/if.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #ifdef INET 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/in_var.h> 61 #include <netinet/ip.h> 62 #endif 63 64 #include <net/if_types.h> 65 #include <net/if_vlanvar.h> 66 67 #if NBPFILTER > 0 68 #include <net/bpf.h> 69 #endif 70 71 #include <sys/rnd.h> 72 73 #include <dev/mii/mii.h> 74 #include <dev/mii/miivar.h> 75 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/pcidevs.h> 79 80 #include <dev/pci/if_agereg.h> 81 82 static int age_match(device_t, cfdata_t, void *); 83 static void age_attach(device_t, device_t, void *); 84 static int age_detach(device_t, int); 85 86 static bool age_resume(device_t PMF_FN_PROTO); 87 88 static int age_miibus_readreg(device_t, int, int); 89 static void age_miibus_writereg(device_t, int, int, int); 90 static void age_miibus_statchg(device_t); 91 92 static int age_init(struct ifnet *); 93 static int age_ioctl(struct ifnet *, u_long, void *); 94 static void age_start(struct ifnet *); 95 static void age_watchdog(struct ifnet *); 96 static void age_mediastatus(struct ifnet *, struct ifmediareq *); 97 static int age_mediachange(struct ifnet *); 98 99 static int age_intr(void *); 100 static int age_read_vpd_word(struct age_softc *, uint32_t, uint32_t, uint32_t *); 101 static int age_dma_alloc(struct age_softc *); 102 static void age_dma_free(struct age_softc *); 103 static void age_get_macaddr(struct age_softc *, uint8_t[]); 104 static void age_phy_reset(struct age_softc *); 105 106 static int age_encap(struct age_softc *, struct mbuf **); 107 static void age_init_tx_ring(struct age_softc *); 108 static int age_init_rx_ring(struct age_softc *); 109 static void age_init_rr_ring(struct age_softc *); 110 static void age_init_cmb_block(struct age_softc *); 111 static void age_init_smb_block(struct age_softc *); 112 static int age_newbuf(struct age_softc *, struct age_rxdesc *, int); 113 static void age_mac_config(struct age_softc *); 114 static void age_txintr(struct age_softc *, int); 115 static void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 116 static void age_rxintr(struct age_softc *, int); 117 static void age_tick(void *); 118 static void age_reset(struct age_softc *); 119 static void age_stop(struct ifnet *, int); 120 static void age_stats_update(struct age_softc *); 121 static void age_stop_txmac(struct age_softc *); 122 static void age_stop_rxmac(struct age_softc *); 123 static void age_rxvlan(struct age_softc *sc); 124 static void age_rxfilter(struct age_softc *); 125 126 CFATTACH_DECL_NEW(age, sizeof(struct age_softc), 127 age_match, age_attach, age_detach, NULL); 128 129 int agedebug = 0; 130 #define DPRINTF(x) do { if (agedebug) printf x; } while (0) 131 132 #define ETHER_ALIGN 2 133 #define AGE_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 134 135 static int 136 age_match(device_t dev, cfdata_t match, void *aux) 137 { 138 struct pci_attach_args *pa = aux; 139 140 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && 141 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_GIGA); 142 } 143 144 static void 145 age_attach(device_t parent, device_t self, void *aux) 146 { 147 struct age_softc *sc = device_private(self); 148 struct pci_attach_args *pa = aux; 149 pci_intr_handle_t ih; 150 const char *intrstr; 151 struct ifnet *ifp = &sc->sc_ec.ec_if; 152 pcireg_t memtype; 153 int error = 0; 154 155 aprint_naive("\n"); 156 aprint_normal(": Attansic/Atheros L1 Gigabit Ethernet\n"); 157 158 sc->sc_dev = self; 159 sc->sc_dmat = pa->pa_dmat; 160 sc->sc_pct = pa->pa_pc; 161 sc->sc_pcitag = pa->pa_tag; 162 163 /* 164 * Allocate IO memory 165 */ 166 memtype = pci_mapreg_type(sc->sc_pct, sc->sc_pcitag, AGE_PCIR_BAR); 167 switch (memtype) { 168 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 169 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 170 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 171 break; 172 default: 173 aprint_error_dev(self, "invalid base address register\n"); 174 break; 175 } 176 177 if (pci_mapreg_map(pa, AGE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 178 &sc->sc_mem_bh, NULL, &sc->sc_mem_size) != 0) { 179 aprint_error_dev(self, "could not map mem space\n"); 180 return; 181 } 182 183 if (pci_intr_map(pa, &ih) != 0) { 184 aprint_error_dev(self, "could not map interrupt\n"); 185 return; 186 } 187 188 /* 189 * Allocate IRQ 190 */ 191 intrstr = pci_intr_string(sc->sc_pct, ih); 192 sc->sc_irq_handle = pci_intr_establish(sc->sc_pct, ih, IPL_NET, 193 age_intr, sc); 194 if (sc->sc_irq_handle == NULL) { 195 aprint_error_dev(self, "could not establish interrupt"); 196 if (intrstr != NULL) 197 aprint_error(" at %s", intrstr); 198 aprint_error("\n"); 199 return; 200 } 201 aprint_normal_dev(self, "%s\n", intrstr); 202 203 /* Set PHY address. */ 204 sc->age_phyaddr = AGE_PHY_ADDR; 205 206 /* Reset PHY. */ 207 age_phy_reset(sc); 208 209 /* Reset the ethernet controller. */ 210 age_reset(sc); 211 212 /* Get PCI and chip id/revision. */ 213 sc->age_rev = PCI_REVISION(pa->pa_class); 214 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 215 MASTER_CHIP_REV_SHIFT; 216 217 aprint_debug_dev(self, "PCI device revision : 0x%04x\n", sc->age_rev); 218 aprint_debug_dev(self, "Chip id/revision : 0x%04x\n", sc->age_chip_rev); 219 220 if (agedebug) { 221 aprint_debug_dev(self, "%d Tx FIFO, %d Rx FIFO\n", 222 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 223 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 224 } 225 226 /* Set max allowable DMA size. */ 227 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 228 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 229 230 /* Allocate DMA stuffs */ 231 error = age_dma_alloc(sc); 232 if (error) 233 goto fail; 234 235 callout_init(&sc->sc_tick_ch, 0); 236 callout_setfunc(&sc->sc_tick_ch, age_tick, sc); 237 238 /* Load station address. */ 239 age_get_macaddr(sc, sc->sc_enaddr); 240 241 aprint_normal_dev(self, "Ethernet address %s\n", 242 ether_sprintf(sc->sc_enaddr)); 243 244 ifp->if_softc = sc; 245 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 246 ifp->if_init = age_init; 247 ifp->if_ioctl = age_ioctl; 248 ifp->if_start = age_start; 249 ifp->if_stop = age_stop; 250 ifp->if_watchdog = age_watchdog; 251 ifp->if_baudrate = IF_Gbps(1); 252 IFQ_SET_MAXLEN(&ifp->if_snd, AGE_TX_RING_CNT - 1); 253 IFQ_SET_READY(&ifp->if_snd); 254 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 255 256 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 257 258 #ifdef AGE_CHECKSUM 259 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 260 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 261 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 262 #endif 263 264 #if NVLAN > 0 265 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 266 #endif 267 268 /* Set up MII bus. */ 269 sc->sc_miibus.mii_ifp = ifp; 270 sc->sc_miibus.mii_readreg = age_miibus_readreg; 271 sc->sc_miibus.mii_writereg = age_miibus_writereg; 272 sc->sc_miibus.mii_statchg = age_miibus_statchg; 273 274 sc->sc_ec.ec_mii = &sc->sc_miibus; 275 ifmedia_init(&sc->sc_miibus.mii_media, 0, age_mediachange, 276 age_mediastatus); 277 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 278 MII_OFFSET_ANY, 0); 279 280 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 281 aprint_error_dev(self, "no PHY found!\n"); 282 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 283 0, NULL); 284 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 285 } else 286 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 287 288 if_attach(ifp); 289 ether_ifattach(ifp, sc->sc_enaddr); 290 291 if (!pmf_device_register(self, NULL, age_resume)) 292 aprint_error_dev(self, "couldn't establish power handler\n"); 293 else 294 pmf_class_network_register(self, ifp); 295 296 return; 297 298 fail: 299 if (sc->sc_irq_handle != NULL) { 300 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 301 sc->sc_irq_handle = NULL; 302 } 303 } 304 305 static int 306 age_detach(device_t self, int flags) 307 { 308 struct age_softc *sc = device_private(self); 309 struct ifnet *ifp = &sc->sc_ec.ec_if; 310 int s; 311 312 s = splnet(); 313 age_stop(ifp, 0); 314 splx(s); 315 316 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 317 318 /* Delete all remaining media. */ 319 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 320 321 ether_ifdetach(ifp); 322 if_detach(ifp); 323 age_dma_free(sc); 324 325 if (sc->sc_irq_handle != NULL) { 326 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 327 sc->sc_irq_handle = NULL; 328 } 329 330 return 0; 331 } 332 333 /* 334 * Read a PHY register on the MII of the L1. 335 */ 336 static int 337 age_miibus_readreg(device_t dev, int phy, int reg) 338 { 339 struct age_softc *sc = device_private(dev); 340 uint32_t v; 341 int i; 342 343 if (phy != sc->age_phyaddr) 344 return 0; 345 346 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 347 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 348 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 349 DELAY(1); 350 v = CSR_READ_4(sc, AGE_MDIO); 351 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 352 break; 353 } 354 355 if (i == 0) { 356 printf("%s: phy read timeout: phy %d, reg %d\n", 357 device_xname(sc->sc_dev), phy, reg); 358 return 0; 359 } 360 361 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 362 } 363 364 /* 365 * Write a PHY register on the MII of the L1. 366 */ 367 static void 368 age_miibus_writereg(device_t dev, int phy, int reg, int val) 369 { 370 struct age_softc *sc = device_private(dev); 371 uint32_t v; 372 int i; 373 374 if (phy != sc->age_phyaddr) 375 return; 376 377 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 378 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 379 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 380 381 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 382 DELAY(1); 383 v = CSR_READ_4(sc, AGE_MDIO); 384 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 385 break; 386 } 387 388 if (i == 0) { 389 printf("%s: phy write timeout: phy %d, reg %d\n", 390 device_xname(sc->sc_dev), phy, reg); 391 } 392 } 393 394 /* 395 * Callback from MII layer when media changes. 396 */ 397 static void 398 age_miibus_statchg(device_t dev) 399 { 400 struct age_softc *sc = device_private(dev); 401 struct ifnet *ifp = &sc->sc_ec.ec_if; 402 struct mii_data *mii; 403 404 if ((ifp->if_flags & IFF_RUNNING) == 0) 405 return; 406 407 mii = &sc->sc_miibus; 408 409 sc->age_flags &= ~AGE_FLAG_LINK; 410 if ((mii->mii_media_status & IFM_AVALID) != 0) { 411 switch (IFM_SUBTYPE(mii->mii_media_active)) { 412 case IFM_10_T: 413 case IFM_100_TX: 414 case IFM_1000_T: 415 sc->age_flags |= AGE_FLAG_LINK; 416 break; 417 default: 418 break; 419 } 420 } 421 422 /* Stop Rx/Tx MACs. */ 423 age_stop_rxmac(sc); 424 age_stop_txmac(sc); 425 426 /* Program MACs with resolved speed/duplex/flow-control. */ 427 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 428 uint32_t reg; 429 430 age_mac_config(sc); 431 reg = CSR_READ_4(sc, AGE_MAC_CFG); 432 /* Restart DMA engine and Tx/Rx MAC. */ 433 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 434 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 435 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 436 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 437 } 438 } 439 440 /* 441 * Get the current interface media status. 442 */ 443 static void 444 age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 445 { 446 struct age_softc *sc = ifp->if_softc; 447 struct mii_data *mii = &sc->sc_miibus; 448 449 mii_pollstat(mii); 450 ifmr->ifm_status = mii->mii_media_status; 451 ifmr->ifm_active = mii->mii_media_active; 452 } 453 454 /* 455 * Set hardware to newly-selected media. 456 */ 457 static int 458 age_mediachange(struct ifnet *ifp) 459 { 460 struct age_softc *sc = ifp->if_softc; 461 struct mii_data *mii = &sc->sc_miibus; 462 int error; 463 464 if (mii->mii_instance != 0) { 465 struct mii_softc *miisc; 466 467 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 468 mii_phy_reset(miisc); 469 } 470 error = mii_mediachg(mii); 471 472 return error; 473 } 474 475 static int 476 age_intr(void *arg) 477 { 478 struct age_softc *sc = arg; 479 struct ifnet *ifp = &sc->sc_ec.ec_if; 480 struct cmb *cmb; 481 uint32_t status; 482 483 status = CSR_READ_4(sc, AGE_INTR_STATUS); 484 if (status == 0 || (status & AGE_INTRS) == 0) 485 return 0; 486 487 cmb = sc->age_rdata.age_cmb_block; 488 if (cmb == NULL) 489 return 0; 490 491 /* Disable interrupts. */ 492 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 493 494 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 495 sc->age_cdata.age_cmb_block_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 496 status = le32toh(cmb->intr_status); 497 if ((status & AGE_INTRS) == 0) 498 goto back; 499 500 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 501 TPD_CONS_SHIFT; 502 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 503 RRD_PROD_SHIFT; 504 505 /* Let hardware know CMB was served. */ 506 cmb->intr_status = 0; 507 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 508 sc->age_cdata.age_cmb_block_map->dm_mapsize, 509 BUS_DMASYNC_PREWRITE); 510 511 if (ifp->if_flags & IFF_RUNNING) { 512 if (status & INTR_CMB_RX) 513 age_rxintr(sc, sc->age_rr_prod); 514 515 if (status & INTR_CMB_TX) 516 age_txintr(sc, sc->age_tpd_cons); 517 518 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 519 if (status & INTR_DMA_RD_TO_RST) 520 printf("%s: DMA read error! -- resetting\n", 521 device_xname(sc->sc_dev)); 522 if (status & INTR_DMA_WR_TO_RST) 523 printf("%s: DMA write error! -- resetting\n", 524 device_xname(sc->sc_dev)); 525 age_init(ifp); 526 } 527 528 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 529 age_start(ifp); 530 531 if (status & INTR_SMB) 532 age_stats_update(sc); 533 } 534 535 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 536 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 537 sc->age_cdata.age_cmb_block_map->dm_mapsize, 538 BUS_DMASYNC_POSTREAD); 539 540 back: 541 /* Re-enable interrupts. */ 542 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 543 544 return 1; 545 } 546 547 static int 548 age_read_vpd_word(struct age_softc *sc, uint32_t vpdc, uint32_t offset, 549 uint32_t *word) 550 { 551 int i; 552 pcireg_t rv; 553 554 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_VPD_ADDRESS(vpdc), 555 offset << PCI_VPD_ADDRESS_SHIFT); 556 for (i = AGE_TIMEOUT; i > 0; i--) { 557 DELAY(10); 558 rv = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 559 PCI_VPD_ADDRESS(vpdc)); 560 if ((rv & PCI_VPD_OPFLAG) == PCI_VPD_OPFLAG) 561 break; 562 } 563 if (i == 0) { 564 printf("%s: VPD read timeout!\n", device_xname(sc->sc_dev)); 565 *word = 0; 566 return ETIMEDOUT; 567 } 568 569 *word = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_VPD_DATAREG(vpdc)); 570 return 0; 571 } 572 573 static void 574 age_get_macaddr(struct age_softc *sc, uint8_t eaddr[]) 575 { 576 uint32_t ea[2], off, reg, word; 577 int vpd_error, match, vpdc; 578 579 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 580 if ((reg & SPI_VPD_ENB) != 0) { 581 /* Get VPD stored in TWSI EEPROM. */ 582 reg &= ~SPI_VPD_ENB; 583 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 584 } 585 586 vpd_error = 0; 587 ea[0] = ea[1] = 0; 588 if ((vpd_error = pci_get_capability(sc->sc_pct, sc->sc_pcitag, 589 PCI_CAP_VPD, &vpdc, NULL))) { 590 /* 591 * PCI VPD capability exists, but it seems that it's 592 * not in the standard form as stated in PCI VPD 593 * specification such that driver could not use 594 * pci_get_vpd_readonly(9) with keyword 'NA'. 595 * Search VPD data starting at address 0x0100. The data 596 * should be used as initializers to set AGE_PAR0, 597 * AGE_PAR1 register including other PCI configuration 598 * registers. 599 */ 600 word = 0; 601 match = 0; 602 reg = 0; 603 for (off = AGE_VPD_REG_CONF_START; off < AGE_VPD_REG_CONF_END; 604 off += sizeof(uint32_t)) { 605 vpd_error = age_read_vpd_word(sc, vpdc, off, &word); 606 if (vpd_error != 0) 607 break; 608 if (match != 0) { 609 switch (reg) { 610 case AGE_PAR0: 611 ea[0] = word; 612 break; 613 case AGE_PAR1: 614 ea[1] = word; 615 break; 616 default: 617 break; 618 } 619 match = 0; 620 } else if ((word & 0xFF) == AGE_VPD_REG_CONF_SIG) { 621 match = 1; 622 reg = word >> 16; 623 } else 624 break; 625 } 626 if (off >= AGE_VPD_REG_CONF_END) 627 vpd_error = ENOENT; 628 if (vpd_error == 0) { 629 /* 630 * Don't blindly trust ethernet address obtained 631 * from VPD. Check whether ethernet address is 632 * valid one. Otherwise fall-back to reading 633 * PAR register. 634 */ 635 ea[1] &= 0xFFFF; 636 if ((ea[0] == 0 && ea[1] == 0) || 637 (ea[0] == 0xFFFFFFFF && ea[1] == 0xFFFF)) { 638 if (agedebug) 639 printf("%s: invalid ethernet address " 640 "returned from VPD.\n", 641 device_xname(sc->sc_dev)); 642 vpd_error = EINVAL; 643 } 644 } 645 if (vpd_error != 0 && (agedebug)) 646 printf("%s: VPD access failure!\n", 647 device_xname(sc->sc_dev)); 648 } else { 649 if (agedebug) 650 printf("%s: PCI VPD capability not found!\n", 651 device_xname(sc->sc_dev)); 652 } 653 654 /* 655 * It seems that L1 also provides a way to extract ethernet 656 * address via SPI flash interface. Because SPI flash memory 657 * device of different vendors vary in their instruction 658 * codes for read ID instruction, it's very hard to get 659 * instructions codes without detailed information for the 660 * flash memory device used on ethernet controller. To simplify 661 * code, just read AGE_PAR0/AGE_PAR1 register to get ethernet 662 * address which is supposed to be set by hardware during 663 * power on reset. 664 */ 665 if (vpd_error != 0) { 666 /* 667 * VPD is mapped to SPI flash memory or BIOS set it. 668 */ 669 ea[0] = CSR_READ_4(sc, AGE_PAR0); 670 ea[1] = CSR_READ_4(sc, AGE_PAR1); 671 } 672 673 ea[1] &= 0xFFFF; 674 eaddr[0] = (ea[1] >> 8) & 0xFF; 675 eaddr[1] = (ea[1] >> 0) & 0xFF; 676 eaddr[2] = (ea[0] >> 24) & 0xFF; 677 eaddr[3] = (ea[0] >> 16) & 0xFF; 678 eaddr[4] = (ea[0] >> 8) & 0xFF; 679 eaddr[5] = (ea[0] >> 0) & 0xFF; 680 } 681 682 static void 683 age_phy_reset(struct age_softc *sc) 684 { 685 /* Reset PHY. */ 686 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 687 DELAY(1000); 688 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 689 DELAY(1000); 690 } 691 692 static int 693 age_dma_alloc(struct age_softc *sc) 694 { 695 struct age_txdesc *txd; 696 struct age_rxdesc *rxd; 697 int nsegs, error, i; 698 699 /* 700 * Create DMA stuffs for TX ring 701 */ 702 error = bus_dmamap_create(sc->sc_dmat, AGE_TX_RING_SZ, 1, 703 AGE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_tx_ring_map); 704 if (error) 705 return ENOBUFS; 706 707 /* Allocate DMA'able memory for TX ring */ 708 error = bus_dmamem_alloc(sc->sc_dmat, AGE_TX_RING_SZ, 709 ETHER_ALIGN, 0, &sc->age_rdata.age_tx_ring_seg, 1, 710 &nsegs, BUS_DMA_WAITOK); 711 if (error) { 712 printf("%s: could not allocate DMA'able memory for Tx ring, " 713 "error = %i\n", device_xname(sc->sc_dev), error); 714 return error; 715 } 716 717 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_tx_ring_seg, 718 nsegs, AGE_TX_RING_SZ, (void **)&sc->age_rdata.age_tx_ring, 719 BUS_DMA_NOWAIT); 720 if (error) 721 return ENOBUFS; 722 723 memset(sc->age_rdata.age_tx_ring, 0, AGE_TX_RING_SZ); 724 725 /* Load the DMA map for Tx ring. */ 726 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 727 sc->age_rdata.age_tx_ring, AGE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 728 if (error) { 729 printf("%s: could not load DMA'able memory for Tx ring, " 730 "error = %i\n", device_xname(sc->sc_dev), error); 731 bus_dmamem_free(sc->sc_dmat, 732 (bus_dma_segment_t *)&sc->age_rdata.age_tx_ring, 1); 733 return error; 734 } 735 736 sc->age_rdata.age_tx_ring_paddr = 737 sc->age_cdata.age_tx_ring_map->dm_segs[0].ds_addr; 738 739 /* 740 * Create DMA stuffs for RX ring 741 */ 742 error = bus_dmamap_create(sc->sc_dmat, AGE_RX_RING_SZ, 1, 743 AGE_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_ring_map); 744 if (error) 745 return ENOBUFS; 746 747 /* Allocate DMA'able memory for RX ring */ 748 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RX_RING_SZ, 749 ETHER_ALIGN, 0, &sc->age_rdata.age_rx_ring_seg, 1, 750 &nsegs, BUS_DMA_WAITOK); 751 if (error) { 752 printf("%s: could not allocate DMA'able memory for Rx ring, " 753 "error = %i.\n", device_xname(sc->sc_dev), error); 754 return error; 755 } 756 757 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rx_ring_seg, 758 nsegs, AGE_RX_RING_SZ, (void **)&sc->age_rdata.age_rx_ring, 759 BUS_DMA_NOWAIT); 760 if (error) 761 return ENOBUFS; 762 763 memset(sc->age_rdata.age_rx_ring, 0, AGE_RX_RING_SZ); 764 765 /* Load the DMA map for Rx ring. */ 766 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 767 sc->age_rdata.age_rx_ring, AGE_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 768 if (error) { 769 printf("%s: could not load DMA'able memory for Rx ring, " 770 "error = %i.\n", device_xname(sc->sc_dev), error); 771 bus_dmamem_free(sc->sc_dmat, 772 (bus_dma_segment_t *)sc->age_rdata.age_rx_ring, 1); 773 return error; 774 } 775 776 sc->age_rdata.age_rx_ring_paddr = 777 sc->age_cdata.age_rx_ring_map->dm_segs[0].ds_addr; 778 779 /* 780 * Create DMA stuffs for RX return ring 781 */ 782 error = bus_dmamap_create(sc->sc_dmat, AGE_RR_RING_SZ, 1, 783 AGE_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rr_ring_map); 784 if (error) 785 return ENOBUFS; 786 787 /* Allocate DMA'able memory for RX return ring */ 788 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RR_RING_SZ, 789 ETHER_ALIGN, 0, &sc->age_rdata.age_rr_ring_seg, 1, 790 &nsegs, BUS_DMA_WAITOK); 791 if (error) { 792 printf("%s: could not allocate DMA'able memory for Rx " 793 "return ring, error = %i.\n", 794 device_xname(sc->sc_dev), error); 795 return error; 796 } 797 798 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rr_ring_seg, 799 nsegs, AGE_RR_RING_SZ, (void **)&sc->age_rdata.age_rr_ring, 800 BUS_DMA_NOWAIT); 801 if (error) 802 return ENOBUFS; 803 804 memset(sc->age_rdata.age_rr_ring, 0, AGE_RR_RING_SZ); 805 806 /* Load the DMA map for Rx return ring. */ 807 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 808 sc->age_rdata.age_rr_ring, AGE_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 809 if (error) { 810 printf("%s: could not load DMA'able memory for Rx return ring, " 811 "error = %i\n", device_xname(sc->sc_dev), error); 812 bus_dmamem_free(sc->sc_dmat, 813 (bus_dma_segment_t *)&sc->age_rdata.age_rr_ring, 1); 814 return error; 815 } 816 817 sc->age_rdata.age_rr_ring_paddr = 818 sc->age_cdata.age_rr_ring_map->dm_segs[0].ds_addr; 819 820 /* 821 * Create DMA stuffs for CMB block 822 */ 823 error = bus_dmamap_create(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 1, 824 AGE_CMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 825 &sc->age_cdata.age_cmb_block_map); 826 if (error) 827 return ENOBUFS; 828 829 /* Allocate DMA'able memory for CMB block */ 830 error = bus_dmamem_alloc(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 831 ETHER_ALIGN, 0, &sc->age_rdata.age_cmb_block_seg, 1, 832 &nsegs, BUS_DMA_WAITOK); 833 if (error) { 834 printf("%s: could not allocate DMA'able memory for " 835 "CMB block, error = %i\n", device_xname(sc->sc_dev), error); 836 return error; 837 } 838 839 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_cmb_block_seg, 840 nsegs, AGE_CMB_BLOCK_SZ, (void **)&sc->age_rdata.age_cmb_block, 841 BUS_DMA_NOWAIT); 842 if (error) 843 return ENOBUFS; 844 845 memset(sc->age_rdata.age_cmb_block, 0, AGE_CMB_BLOCK_SZ); 846 847 /* Load the DMA map for CMB block. */ 848 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 849 sc->age_rdata.age_cmb_block, AGE_CMB_BLOCK_SZ, NULL, 850 BUS_DMA_WAITOK); 851 if (error) { 852 printf("%s: could not load DMA'able memory for CMB block, " 853 "error = %i\n", device_xname(sc->sc_dev), error); 854 bus_dmamem_free(sc->sc_dmat, 855 (bus_dma_segment_t *)&sc->age_rdata.age_cmb_block, 1); 856 return error; 857 } 858 859 sc->age_rdata.age_cmb_block_paddr = 860 sc->age_cdata.age_cmb_block_map->dm_segs[0].ds_addr; 861 862 /* 863 * Create DMA stuffs for SMB block 864 */ 865 error = bus_dmamap_create(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 1, 866 AGE_SMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 867 &sc->age_cdata.age_smb_block_map); 868 if (error) 869 return ENOBUFS; 870 871 /* Allocate DMA'able memory for SMB block */ 872 error = bus_dmamem_alloc(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 873 ETHER_ALIGN, 0, &sc->age_rdata.age_smb_block_seg, 1, 874 &nsegs, BUS_DMA_WAITOK); 875 if (error) { 876 printf("%s: could not allocate DMA'able memory for " 877 "SMB block, error = %i\n", device_xname(sc->sc_dev), error); 878 return error; 879 } 880 881 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_smb_block_seg, 882 nsegs, AGE_SMB_BLOCK_SZ, (void **)&sc->age_rdata.age_smb_block, 883 BUS_DMA_NOWAIT); 884 if (error) 885 return ENOBUFS; 886 887 memset(sc->age_rdata.age_smb_block, 0, AGE_SMB_BLOCK_SZ); 888 889 /* Load the DMA map for SMB block */ 890 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 891 sc->age_rdata.age_smb_block, AGE_SMB_BLOCK_SZ, NULL, 892 BUS_DMA_WAITOK); 893 if (error) { 894 printf("%s: could not load DMA'able memory for SMB block, " 895 "error = %i\n", device_xname(sc->sc_dev), error); 896 bus_dmamem_free(sc->sc_dmat, 897 (bus_dma_segment_t *)&sc->age_rdata.age_smb_block, 1); 898 return error; 899 } 900 901 sc->age_rdata.age_smb_block_paddr = 902 sc->age_cdata.age_smb_block_map->dm_segs[0].ds_addr; 903 904 /* Create DMA maps for Tx buffers. */ 905 for (i = 0; i < AGE_TX_RING_CNT; i++) { 906 txd = &sc->age_cdata.age_txdesc[i]; 907 txd->tx_m = NULL; 908 txd->tx_dmamap = NULL; 909 error = bus_dmamap_create(sc->sc_dmat, AGE_TSO_MAXSIZE, 910 AGE_MAXTXSEGS, AGE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 911 &txd->tx_dmamap); 912 if (error) { 913 printf("%s: could not create Tx dmamap, error = %i.\n", 914 device_xname(sc->sc_dev), error); 915 return error; 916 } 917 } 918 919 /* Create DMA maps for Rx buffers. */ 920 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 921 BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_sparemap); 922 if (error) { 923 printf("%s: could not create spare Rx dmamap, error = %i.\n", 924 device_xname(sc->sc_dev), error); 925 return error; 926 } 927 for (i = 0; i < AGE_RX_RING_CNT; i++) { 928 rxd = &sc->age_cdata.age_rxdesc[i]; 929 rxd->rx_m = NULL; 930 rxd->rx_dmamap = NULL; 931 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 932 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 933 if (error) { 934 printf("%s: could not create Rx dmamap, error = %i.\n", 935 device_xname(sc->sc_dev), error); 936 return error; 937 } 938 } 939 940 return 0; 941 } 942 943 static void 944 age_dma_free(struct age_softc *sc) 945 { 946 struct age_txdesc *txd; 947 struct age_rxdesc *rxd; 948 int i; 949 950 /* Tx buffers */ 951 for (i = 0; i < AGE_TX_RING_CNT; i++) { 952 txd = &sc->age_cdata.age_txdesc[i]; 953 if (txd->tx_dmamap != NULL) { 954 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 955 txd->tx_dmamap = NULL; 956 } 957 } 958 /* Rx buffers */ 959 for (i = 0; i < AGE_RX_RING_CNT; i++) { 960 rxd = &sc->age_cdata.age_rxdesc[i]; 961 if (rxd->rx_dmamap != NULL) { 962 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 963 rxd->rx_dmamap = NULL; 964 } 965 } 966 if (sc->age_cdata.age_rx_sparemap != NULL) { 967 bus_dmamap_destroy(sc->sc_dmat, sc->age_cdata.age_rx_sparemap); 968 sc->age_cdata.age_rx_sparemap = NULL; 969 } 970 971 /* Tx ring. */ 972 if (sc->age_cdata.age_tx_ring_map != NULL) 973 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_tx_ring_map); 974 if (sc->age_cdata.age_tx_ring_map != NULL && 975 sc->age_rdata.age_tx_ring != NULL) 976 bus_dmamem_free(sc->sc_dmat, 977 (bus_dma_segment_t *)sc->age_rdata.age_tx_ring, 1); 978 sc->age_rdata.age_tx_ring = NULL; 979 sc->age_cdata.age_tx_ring_map = NULL; 980 981 /* Rx ring. */ 982 if (sc->age_cdata.age_rx_ring_map != NULL) 983 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rx_ring_map); 984 if (sc->age_cdata.age_rx_ring_map != NULL && 985 sc->age_rdata.age_rx_ring != NULL) 986 bus_dmamem_free(sc->sc_dmat, 987 (bus_dma_segment_t *)sc->age_rdata.age_rx_ring, 1); 988 sc->age_rdata.age_rx_ring = NULL; 989 sc->age_cdata.age_rx_ring_map = NULL; 990 991 /* Rx return ring. */ 992 if (sc->age_cdata.age_rr_ring_map != NULL) 993 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rr_ring_map); 994 if (sc->age_cdata.age_rr_ring_map != NULL && 995 sc->age_rdata.age_rr_ring != NULL) 996 bus_dmamem_free(sc->sc_dmat, 997 (bus_dma_segment_t *)sc->age_rdata.age_rr_ring, 1); 998 sc->age_rdata.age_rr_ring = NULL; 999 sc->age_cdata.age_rr_ring_map = NULL; 1000 1001 /* CMB block */ 1002 if (sc->age_cdata.age_cmb_block_map != NULL) 1003 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_cmb_block_map); 1004 if (sc->age_cdata.age_cmb_block_map != NULL && 1005 sc->age_rdata.age_cmb_block != NULL) 1006 bus_dmamem_free(sc->sc_dmat, 1007 (bus_dma_segment_t *)sc->age_rdata.age_cmb_block, 1); 1008 sc->age_rdata.age_cmb_block = NULL; 1009 sc->age_cdata.age_cmb_block_map = NULL; 1010 1011 /* SMB block */ 1012 if (sc->age_cdata.age_smb_block_map != NULL) 1013 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_smb_block_map); 1014 if (sc->age_cdata.age_smb_block_map != NULL && 1015 sc->age_rdata.age_smb_block != NULL) 1016 bus_dmamem_free(sc->sc_dmat, 1017 (bus_dma_segment_t *)sc->age_rdata.age_smb_block, 1); 1018 sc->age_rdata.age_smb_block = NULL; 1019 sc->age_cdata.age_smb_block_map = NULL; 1020 } 1021 1022 static void 1023 age_start(struct ifnet *ifp) 1024 { 1025 struct age_softc *sc = ifp->if_softc; 1026 struct mbuf *m_head; 1027 int enq; 1028 1029 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1030 return; 1031 1032 enq = 0; 1033 for (;;) { 1034 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1035 if (m_head == NULL) 1036 break; 1037 1038 /* 1039 * Pack the data into the transmit ring. If we 1040 * don't have room, set the OACTIVE flag and wait 1041 * for the NIC to drain the ring. 1042 */ 1043 if (age_encap(sc, &m_head)) { 1044 if (m_head == NULL) 1045 break; 1046 ifp->if_flags |= IFF_OACTIVE; 1047 break; 1048 } 1049 enq = 1; 1050 1051 #if NBPFILTER > 0 1052 /* 1053 * If there's a BPF listener, bounce a copy of this frame 1054 * to him. 1055 */ 1056 if (ifp->if_bpf != NULL) 1057 bpf_mtap(ifp->if_bpf, m_head); 1058 #endif 1059 } 1060 1061 if (enq) { 1062 /* Update mbox. */ 1063 AGE_COMMIT_MBOX(sc); 1064 /* Set a timeout in case the chip goes out to lunch. */ 1065 ifp->if_timer = AGE_TX_TIMEOUT; 1066 } 1067 } 1068 1069 static void 1070 age_watchdog(struct ifnet *ifp) 1071 { 1072 struct age_softc *sc = ifp->if_softc; 1073 1074 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1075 printf("%s: watchdog timeout (missed link)\n", 1076 device_xname(sc->sc_dev)); 1077 ifp->if_oerrors++; 1078 age_init(ifp); 1079 return; 1080 } 1081 1082 if (sc->age_cdata.age_tx_cnt == 0) { 1083 printf("%s: watchdog timeout (missed Tx interrupts) " 1084 "-- recovering\n", device_xname(sc->sc_dev)); 1085 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1086 age_start(ifp); 1087 return; 1088 } 1089 1090 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1091 ifp->if_oerrors++; 1092 age_init(ifp); 1093 1094 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1095 age_start(ifp); 1096 } 1097 1098 static int 1099 age_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1100 { 1101 struct age_softc *sc = ifp->if_softc; 1102 int s, error; 1103 1104 s = splnet(); 1105 1106 error = ether_ioctl(ifp, cmd, data); 1107 if (error == ENETRESET) { 1108 if (ifp->if_flags & IFF_RUNNING) 1109 age_rxfilter(sc); 1110 error = 0; 1111 } 1112 1113 splx(s); 1114 return error; 1115 } 1116 1117 static void 1118 age_mac_config(struct age_softc *sc) 1119 { 1120 struct mii_data *mii; 1121 uint32_t reg; 1122 1123 mii = &sc->sc_miibus; 1124 1125 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1126 reg &= ~MAC_CFG_FULL_DUPLEX; 1127 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1128 reg &= ~MAC_CFG_SPEED_MASK; 1129 1130 /* Reprogram MAC with resolved speed/duplex. */ 1131 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1132 case IFM_10_T: 1133 case IFM_100_TX: 1134 reg |= MAC_CFG_SPEED_10_100; 1135 break; 1136 case IFM_1000_T: 1137 reg |= MAC_CFG_SPEED_1000; 1138 break; 1139 } 1140 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1141 reg |= MAC_CFG_FULL_DUPLEX; 1142 #ifdef notyet 1143 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1144 reg |= MAC_CFG_TX_FC; 1145 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1146 reg |= MAC_CFG_RX_FC; 1147 #endif 1148 } 1149 1150 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1151 } 1152 1153 static bool 1154 age_resume(device_t dv PMF_FN_ARGS) 1155 { 1156 struct age_softc *sc = device_private(dv); 1157 uint16_t cmd; 1158 1159 /* 1160 * Clear INTx emulation disable for hardware that 1161 * is set in resume event. From Linux. 1162 */ 1163 cmd = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 1164 if ((cmd & PCI_COMMAND_INTERRUPT_DISABLE) != 0) { 1165 cmd &= ~PCI_COMMAND_INTERRUPT_DISABLE; 1166 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 1167 PCI_COMMAND_STATUS_REG, cmd); 1168 } 1169 1170 return true; 1171 } 1172 1173 static int 1174 age_encap(struct age_softc *sc, struct mbuf **m_head) 1175 { 1176 struct age_txdesc *txd, *txd_last; 1177 struct tx_desc *desc; 1178 struct mbuf *m; 1179 bus_dmamap_t map; 1180 uint32_t cflags, poff, vtag; 1181 int error, i, nsegs, prod; 1182 #if NVLAN > 0 1183 struct m_tag *mtag; 1184 #endif 1185 1186 m = *m_head; 1187 cflags = vtag = 0; 1188 poff = 0; 1189 1190 prod = sc->age_cdata.age_tx_prod; 1191 txd = &sc->age_cdata.age_txdesc[prod]; 1192 txd_last = txd; 1193 map = txd->tx_dmamap; 1194 1195 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1196 1197 if (error == EFBIG) { 1198 error = 0; 1199 1200 MGETHDR(m, M_DONTWAIT, MT_DATA); 1201 if (m == NULL) { 1202 printf("%s: can't defrag TX mbuf\n", 1203 device_xname(sc->sc_dev)); 1204 m_freem(*m_head); 1205 *m_head = NULL; 1206 return ENOBUFS; 1207 } 1208 1209 M_COPY_PKTHDR(m, *m_head); 1210 if ((*m_head)->m_pkthdr.len > MHLEN) { 1211 MCLGET(m, M_DONTWAIT); 1212 if (!(m->m_flags & M_EXT)) { 1213 m_freem(*m_head); 1214 m_freem(m); 1215 *m_head = NULL; 1216 return ENOBUFS; 1217 } 1218 } 1219 m_copydata(*m_head, 0, (*m_head)->m_pkthdr.len, 1220 mtod(m, void *)); 1221 m_freem(*m_head); 1222 m->m_len = m->m_pkthdr.len; 1223 *m_head = m; 1224 1225 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1226 BUS_DMA_NOWAIT); 1227 1228 if (error != 0) { 1229 printf("%s: could not load defragged TX mbuf\n", 1230 device_xname(sc->sc_dev)); 1231 if (!error) { 1232 bus_dmamap_unload(sc->sc_dmat, map); 1233 error = EFBIG; 1234 } 1235 m_freem(*m_head); 1236 *m_head = NULL; 1237 return error; 1238 } 1239 } else if (error) { 1240 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 1241 return error; 1242 } 1243 1244 nsegs = map->dm_nsegs; 1245 1246 if (nsegs == 0) { 1247 m_freem(*m_head); 1248 *m_head = NULL; 1249 return EIO; 1250 } 1251 1252 /* Check descriptor overrun. */ 1253 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1254 bus_dmamap_unload(sc->sc_dmat, map); 1255 return ENOBUFS; 1256 } 1257 1258 m = *m_head; 1259 /* Configure Tx IP/TCP/UDP checksum offload. */ 1260 if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1261 cflags |= AGE_TD_CSUM; 1262 if ((m->m_pkthdr.csum_flags & M_CSUM_TCPv4) != 0) 1263 cflags |= AGE_TD_TCPCSUM; 1264 if ((m->m_pkthdr.csum_flags & M_CSUM_UDPv4) != 0) 1265 cflags |= AGE_TD_UDPCSUM; 1266 /* Set checksum start offset. */ 1267 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1268 } 1269 1270 #if NVLAN > 0 1271 /* Configure VLAN hardware tag insertion. */ 1272 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m))) { 1273 vtag = AGE_TX_VLAN_TAG(htons(VLAN_TAG_VALUE(mtag))); 1274 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1275 cflags |= AGE_TD_INSERT_VLAN_TAG; 1276 } 1277 #endif 1278 1279 desc = NULL; 1280 for (i = 0; i < nsegs; i++) { 1281 desc = &sc->age_rdata.age_tx_ring[prod]; 1282 desc->addr = htole64(map->dm_segs[i].ds_addr); 1283 desc->len = 1284 htole32(AGE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 1285 desc->flags = htole32(cflags); 1286 sc->age_cdata.age_tx_cnt++; 1287 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1288 } 1289 1290 /* Update producer index. */ 1291 sc->age_cdata.age_tx_prod = prod; 1292 1293 /* Set EOP on the last descriptor. */ 1294 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1295 desc = &sc->age_rdata.age_tx_ring[prod]; 1296 desc->flags |= htole32(AGE_TD_EOP); 1297 1298 /* Swap dmamap of the first and the last. */ 1299 txd = &sc->age_cdata.age_txdesc[prod]; 1300 map = txd_last->tx_dmamap; 1301 txd_last->tx_dmamap = txd->tx_dmamap; 1302 txd->tx_dmamap = map; 1303 txd->tx_m = m; 1304 1305 /* Sync descriptors. */ 1306 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1307 BUS_DMASYNC_PREWRITE); 1308 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1309 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1310 1311 return 0; 1312 } 1313 1314 static void 1315 age_txintr(struct age_softc *sc, int tpd_cons) 1316 { 1317 struct ifnet *ifp = &sc->sc_ec.ec_if; 1318 struct age_txdesc *txd; 1319 int cons, prog; 1320 1321 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1322 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1323 1324 /* 1325 * Go through our Tx list and free mbufs for those 1326 * frames which have been transmitted. 1327 */ 1328 cons = sc->age_cdata.age_tx_cons; 1329 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 1330 if (sc->age_cdata.age_tx_cnt <= 0) 1331 break; 1332 prog++; 1333 ifp->if_flags &= ~IFF_OACTIVE; 1334 sc->age_cdata.age_tx_cnt--; 1335 txd = &sc->age_cdata.age_txdesc[cons]; 1336 /* 1337 * Clear Tx descriptors, it's not required but would 1338 * help debugging in case of Tx issues. 1339 */ 1340 txd->tx_desc->addr = 0; 1341 txd->tx_desc->len = 0; 1342 txd->tx_desc->flags = 0; 1343 1344 if (txd->tx_m == NULL) 1345 continue; 1346 /* Reclaim transmitted mbufs. */ 1347 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1348 m_freem(txd->tx_m); 1349 txd->tx_m = NULL; 1350 } 1351 1352 if (prog > 0) { 1353 sc->age_cdata.age_tx_cons = cons; 1354 1355 /* 1356 * Unarm watchdog timer only when there are no pending 1357 * Tx descriptors in queue. 1358 */ 1359 if (sc->age_cdata.age_tx_cnt == 0) 1360 ifp->if_timer = 0; 1361 1362 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1363 sc->age_cdata.age_tx_ring_map->dm_mapsize, 1364 BUS_DMASYNC_PREWRITE); 1365 } 1366 } 1367 1368 /* Receive a frame. */ 1369 static void 1370 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 1371 { 1372 struct ifnet *ifp = &sc->sc_ec.ec_if; 1373 struct age_rxdesc *rxd; 1374 struct rx_desc *desc; 1375 struct mbuf *mp, *m; 1376 uint32_t status, index; 1377 int count, nsegs, pktlen; 1378 int rx_cons; 1379 1380 status = le32toh(rxrd->flags); 1381 index = le32toh(rxrd->index); 1382 rx_cons = AGE_RX_CONS(index); 1383 nsegs = AGE_RX_NSEGS(index); 1384 1385 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 1386 if ((status & AGE_RRD_ERROR) != 0 && 1387 (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 1388 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) { 1389 /* 1390 * We want to pass the following frames to upper 1391 * layer regardless of error status of Rx return 1392 * ring. 1393 * 1394 * o IP/TCP/UDP checksum is bad. 1395 * o frame length and protocol specific length 1396 * does not match. 1397 */ 1398 sc->age_cdata.age_rx_cons += nsegs; 1399 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1400 return; 1401 } 1402 1403 pktlen = 0; 1404 for (count = 0; count < nsegs; count++, 1405 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 1406 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 1407 mp = rxd->rx_m; 1408 desc = rxd->rx_desc; 1409 /* Add a new receive buffer to the ring. */ 1410 if (age_newbuf(sc, rxd, 0) != 0) { 1411 ifp->if_iqdrops++; 1412 /* Reuse Rx buffers. */ 1413 if (sc->age_cdata.age_rxhead != NULL) { 1414 m_freem(sc->age_cdata.age_rxhead); 1415 AGE_RXCHAIN_RESET(sc); 1416 } 1417 break; 1418 } 1419 1420 /* The length of the first mbuf is computed last. */ 1421 if (count != 0) { 1422 mp->m_len = AGE_RX_BYTES(le32toh(desc->len)); 1423 pktlen += mp->m_len; 1424 } 1425 1426 /* Chain received mbufs. */ 1427 if (sc->age_cdata.age_rxhead == NULL) { 1428 sc->age_cdata.age_rxhead = mp; 1429 sc->age_cdata.age_rxtail = mp; 1430 } else { 1431 mp->m_flags &= ~M_PKTHDR; 1432 sc->age_cdata.age_rxprev_tail = 1433 sc->age_cdata.age_rxtail; 1434 sc->age_cdata.age_rxtail->m_next = mp; 1435 sc->age_cdata.age_rxtail = mp; 1436 } 1437 1438 if (count == nsegs - 1) { 1439 /* 1440 * It seems that L1 controller has no way 1441 * to tell hardware to strip CRC bytes. 1442 */ 1443 sc->age_cdata.age_rxlen -= ETHER_CRC_LEN; 1444 if (nsegs > 1) { 1445 /* Remove the CRC bytes in chained mbufs. */ 1446 pktlen -= ETHER_CRC_LEN; 1447 if (mp->m_len <= ETHER_CRC_LEN) { 1448 sc->age_cdata.age_rxtail = 1449 sc->age_cdata.age_rxprev_tail; 1450 sc->age_cdata.age_rxtail->m_len -= 1451 (ETHER_CRC_LEN - mp->m_len); 1452 sc->age_cdata.age_rxtail->m_next = NULL; 1453 m_freem(mp); 1454 } else { 1455 mp->m_len -= ETHER_CRC_LEN; 1456 } 1457 } 1458 1459 m = sc->age_cdata.age_rxhead; 1460 m->m_flags |= M_PKTHDR; 1461 m->m_pkthdr.rcvif = ifp; 1462 m->m_pkthdr.len = sc->age_cdata.age_rxlen; 1463 /* Set the first mbuf length. */ 1464 m->m_len = sc->age_cdata.age_rxlen - pktlen; 1465 1466 /* 1467 * Set checksum information. 1468 * It seems that L1 controller can compute partial 1469 * checksum. The partial checksum value can be used 1470 * to accelerate checksum computation for fragmented 1471 * TCP/UDP packets. Upper network stack already 1472 * takes advantage of the partial checksum value in 1473 * IP reassembly stage. But I'm not sure the 1474 * correctness of the partial hardware checksum 1475 * assistance due to lack of data sheet. If it is 1476 * proven to work on L1 I'll enable it. 1477 */ 1478 if (status & AGE_RRD_IPV4) { 1479 if (status & AGE_RRD_IPCSUM_NOK) 1480 m->m_pkthdr.csum_flags |= 1481 M_CSUM_IPv4_BAD; 1482 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 1483 (status & AGE_RRD_TCP_UDPCSUM_NOK)) { 1484 m->m_pkthdr.csum_flags |= 1485 M_CSUM_TCP_UDP_BAD; 1486 } 1487 /* 1488 * Don't mark bad checksum for TCP/UDP frames 1489 * as fragmented frames may always have set 1490 * bad checksummed bit of descriptor status. 1491 */ 1492 } 1493 #if NVLAN > 0 1494 /* Check for VLAN tagged frames. */ 1495 if (status & AGE_RRD_VLAN) { 1496 uint32_t vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 1497 VLAN_INPUT_TAG(ifp, m, AGE_RX_VLAN_TAG(vtag), 1498 continue); 1499 } 1500 #endif 1501 1502 #if NBPFILTER > 0 1503 if (ifp->if_bpf) 1504 bpf_mtap(ifp->if_bpf, m); 1505 #endif 1506 /* Pass it on. */ 1507 ether_input(ifp, m); 1508 1509 /* Reset mbuf chains. */ 1510 AGE_RXCHAIN_RESET(sc); 1511 } 1512 } 1513 1514 if (count != nsegs) { 1515 sc->age_cdata.age_rx_cons += nsegs; 1516 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1517 } else 1518 sc->age_cdata.age_rx_cons = rx_cons; 1519 } 1520 1521 static void 1522 age_rxintr(struct age_softc *sc, int rr_prod) 1523 { 1524 struct rx_rdesc *rxrd; 1525 int rr_cons, nsegs, pktlen, prog; 1526 1527 rr_cons = sc->age_cdata.age_rr_cons; 1528 if (rr_cons == rr_prod) 1529 return; 1530 1531 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1532 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1533 BUS_DMASYNC_POSTREAD); 1534 1535 for (prog = 0; rr_cons != rr_prod; prog++) { 1536 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 1537 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 1538 if (nsegs == 0) 1539 break; 1540 /* 1541 * Check number of segments against received bytes 1542 * Non-matching value would indicate that hardware 1543 * is still trying to update Rx return descriptors. 1544 * I'm not sure whether this check is really needed. 1545 */ 1546 pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 1547 if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) / 1548 (MCLBYTES - ETHER_ALIGN))) 1549 break; 1550 1551 /* Received a frame. */ 1552 age_rxeof(sc, rxrd); 1553 1554 /* Clear return ring. */ 1555 rxrd->index = 0; 1556 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 1557 } 1558 1559 if (prog > 0) { 1560 /* Update the consumer index. */ 1561 sc->age_cdata.age_rr_cons = rr_cons; 1562 1563 /* Sync descriptors. */ 1564 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1565 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1566 BUS_DMASYNC_PREWRITE); 1567 1568 /* Notify hardware availability of new Rx buffers. */ 1569 AGE_COMMIT_MBOX(sc); 1570 } 1571 } 1572 1573 static void 1574 age_tick(void *xsc) 1575 { 1576 struct age_softc *sc = xsc; 1577 struct mii_data *mii = &sc->sc_miibus; 1578 int s; 1579 1580 s = splnet(); 1581 mii_tick(mii); 1582 splx(s); 1583 1584 callout_schedule(&sc->sc_tick_ch, hz); 1585 } 1586 1587 static void 1588 age_reset(struct age_softc *sc) 1589 { 1590 uint32_t reg; 1591 int i; 1592 1593 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 1594 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1595 DELAY(1); 1596 if ((CSR_READ_4(sc, AGE_MASTER_CFG) & MASTER_RESET) == 0) 1597 break; 1598 } 1599 if (i == 0) 1600 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 1601 1602 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1603 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1604 break; 1605 DELAY(10); 1606 } 1607 1608 if (i == 0) 1609 printf("%s: reset timeout(0x%08x)!\n", device_xname(sc->sc_dev), 1610 reg); 1611 1612 /* Initialize PCIe module. From Linux. */ 1613 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1614 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1615 } 1616 1617 static int 1618 age_init(struct ifnet *ifp) 1619 { 1620 struct age_softc *sc = ifp->if_softc; 1621 struct mii_data *mii; 1622 uint8_t eaddr[ETHER_ADDR_LEN]; 1623 bus_addr_t paddr; 1624 uint32_t reg, fsize; 1625 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 1626 int error; 1627 1628 /* 1629 * Cancel any pending I/O. 1630 */ 1631 age_stop(ifp, 0); 1632 1633 /* 1634 * Reset the chip to a known state. 1635 */ 1636 age_reset(sc); 1637 1638 /* Initialize descriptors. */ 1639 error = age_init_rx_ring(sc); 1640 if (error != 0) { 1641 printf("%s: no memory for Rx buffers.\n", device_xname(sc->sc_dev)); 1642 age_stop(ifp, 0); 1643 return error; 1644 } 1645 age_init_rr_ring(sc); 1646 age_init_tx_ring(sc); 1647 age_init_cmb_block(sc); 1648 age_init_smb_block(sc); 1649 1650 /* Reprogram the station address. */ 1651 memcpy(eaddr, CLLADDR(ifp->if_sadl), sizeof(eaddr)); 1652 CSR_WRITE_4(sc, AGE_PAR0, 1653 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1654 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 1655 1656 /* Set descriptor base addresses. */ 1657 paddr = sc->age_rdata.age_tx_ring_paddr; 1658 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 1659 paddr = sc->age_rdata.age_rx_ring_paddr; 1660 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 1661 paddr = sc->age_rdata.age_rr_ring_paddr; 1662 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 1663 paddr = sc->age_rdata.age_tx_ring_paddr; 1664 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 1665 paddr = sc->age_rdata.age_cmb_block_paddr; 1666 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1667 paddr = sc->age_rdata.age_smb_block_paddr; 1668 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1669 1670 /* Set Rx/Rx return descriptor counter. */ 1671 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 1672 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 1673 DESC_RRD_CNT_MASK) | 1674 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 1675 1676 /* Set Tx descriptor counter. */ 1677 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 1678 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 1679 1680 /* Tell hardware that we're ready to load descriptors. */ 1681 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 1682 1683 /* 1684 * Initialize mailbox register. 1685 * Updated producer/consumer index information is exchanged 1686 * through this mailbox register. However Tx producer and 1687 * Rx return consumer/Rx producer are all shared such that 1688 * it's hard to separate code path between Tx and Rx without 1689 * locking. If L1 hardware have a separate mail box register 1690 * for Tx and Rx consumer/producer management we could have 1691 * indepent Tx/Rx handler which in turn Rx handler could have 1692 * been run without any locking. 1693 */ 1694 AGE_COMMIT_MBOX(sc); 1695 1696 /* Configure IPG/IFG parameters. */ 1697 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 1698 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 1699 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1700 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1701 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 1702 1703 /* Set parameters for half-duplex media. */ 1704 CSR_WRITE_4(sc, AGE_HDPX_CFG, 1705 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1706 HDPX_CFG_LCOL_MASK) | 1707 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1708 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1709 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1710 HDPX_CFG_ABEBT_MASK) | 1711 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1712 HDPX_CFG_JAMIPG_MASK)); 1713 1714 /* Configure interrupt moderation timer. */ 1715 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 1716 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 1717 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 1718 reg &= ~MASTER_MTIMER_ENB; 1719 if (AGE_USECS(sc->age_int_mod) == 0) 1720 reg &= ~MASTER_ITIMER_ENB; 1721 else 1722 reg |= MASTER_ITIMER_ENB; 1723 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 1724 if (agedebug) 1725 printf("%s: interrupt moderation is %d us.\n", 1726 device_xname(sc->sc_dev), sc->age_int_mod); 1727 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 1728 1729 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 1730 if (ifp->if_mtu < ETHERMTU) 1731 sc->age_max_frame_size = ETHERMTU; 1732 else 1733 sc->age_max_frame_size = ifp->if_mtu; 1734 sc->age_max_frame_size += ETHER_HDR_LEN + 1735 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 1736 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 1737 1738 /* Configure jumbo frame. */ 1739 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 1740 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 1741 (((fsize / sizeof(uint64_t)) << 1742 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 1743 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 1744 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 1745 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 1746 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 1747 1748 /* Configure flow-control parameters. From Linux. */ 1749 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 1750 /* 1751 * Magic workaround for old-L1. 1752 * Don't know which hw revision requires this magic. 1753 */ 1754 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1755 /* 1756 * Another magic workaround for flow-control mode 1757 * change. From Linux. 1758 */ 1759 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1760 } 1761 /* 1762 * TODO 1763 * Should understand pause parameter relationships between FIFO 1764 * size and number of Rx descriptors and Rx return descriptors. 1765 * 1766 * Magic parameters came from Linux. 1767 */ 1768 switch (sc->age_chip_rev) { 1769 case 0x8001: 1770 case 0x9001: 1771 case 0x9002: 1772 case 0x9003: 1773 rxf_hi = AGE_RX_RING_CNT / 16; 1774 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 1775 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 1776 rrd_lo = AGE_RR_RING_CNT / 16; 1777 break; 1778 default: 1779 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 1780 rxf_lo = reg / 16; 1781 if (rxf_lo < 192) 1782 rxf_lo = 192; 1783 rxf_hi = (reg * 7) / 8; 1784 if (rxf_hi < rxf_lo) 1785 rxf_hi = rxf_lo + 16; 1786 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 1787 rrd_lo = reg / 8; 1788 rrd_hi = (reg * 7) / 8; 1789 if (rrd_lo < 2) 1790 rrd_lo = 2; 1791 if (rrd_hi < rrd_lo) 1792 rrd_hi = rrd_lo + 3; 1793 break; 1794 } 1795 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 1796 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 1797 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 1798 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 1799 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 1800 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 1801 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 1802 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 1803 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 1804 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 1805 1806 /* Configure RxQ. */ 1807 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1808 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 1809 RXQ_CFG_RD_BURST_MASK) | 1810 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 1811 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 1812 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 1813 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 1814 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1815 1816 /* Configure TxQ. */ 1817 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1818 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1819 TXQ_CFG_TPD_BURST_MASK) | 1820 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 1821 TXQ_CFG_TX_FIFO_BURST_MASK) | 1822 ((TXQ_CFG_TPD_FETCH_DEFAULT << 1823 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 1824 TXQ_CFG_ENB); 1825 1826 /* Configure DMA parameters. */ 1827 CSR_WRITE_4(sc, AGE_DMA_CFG, 1828 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 1829 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 1830 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 1831 1832 /* Configure CMB DMA write threshold. */ 1833 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 1834 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 1835 CMB_WR_THRESH_RRD_MASK) | 1836 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 1837 CMB_WR_THRESH_TPD_MASK)); 1838 1839 /* Set CMB/SMB timer and enable them. */ 1840 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 1841 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 1842 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 1843 1844 /* Request SMB updates for every seconds. */ 1845 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 1846 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 1847 1848 /* 1849 * Disable all WOL bits as WOL can interfere normal Rx 1850 * operation. 1851 */ 1852 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1853 1854 /* 1855 * Configure Tx/Rx MACs. 1856 * - Auto-padding for short frames. 1857 * - Enable CRC generation. 1858 * Start with full-duplex/1000Mbps media. Actual reconfiguration 1859 * of MAC is followed after link establishment. 1860 */ 1861 CSR_WRITE_4(sc, AGE_MAC_CFG, 1862 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 1863 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 1864 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1865 MAC_CFG_PREAMBLE_MASK)); 1866 1867 /* Set up the receive filter. */ 1868 age_rxfilter(sc); 1869 age_rxvlan(sc); 1870 1871 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1872 reg |= MAC_CFG_RXCSUM_ENB; 1873 1874 /* Ack all pending interrupts and clear it. */ 1875 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 1876 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 1877 1878 /* Finally enable Tx/Rx MAC. */ 1879 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 1880 1881 sc->age_flags &= ~AGE_FLAG_LINK; 1882 1883 /* Switch to the current media. */ 1884 mii = &sc->sc_miibus; 1885 mii_mediachg(mii); 1886 1887 callout_schedule(&sc->sc_tick_ch, hz); 1888 1889 ifp->if_flags |= IFF_RUNNING; 1890 ifp->if_flags &= ~IFF_OACTIVE; 1891 1892 return 0; 1893 } 1894 1895 static void 1896 age_stop(struct ifnet *ifp, int disable) 1897 { 1898 struct age_softc *sc = ifp->if_softc; 1899 struct age_txdesc *txd; 1900 struct age_rxdesc *rxd; 1901 uint32_t reg; 1902 int i; 1903 1904 callout_stop(&sc->sc_tick_ch); 1905 1906 /* 1907 * Mark the interface down and cancel the watchdog timer. 1908 */ 1909 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1910 ifp->if_timer = 0; 1911 1912 sc->age_flags &= ~AGE_FLAG_LINK; 1913 1914 mii_down(&sc->sc_miibus); 1915 1916 /* 1917 * Disable interrupts. 1918 */ 1919 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 1920 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 1921 1922 /* Stop CMB/SMB updates. */ 1923 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 1924 1925 /* Stop Rx/Tx MAC. */ 1926 age_stop_rxmac(sc); 1927 age_stop_txmac(sc); 1928 1929 /* Stop DMA. */ 1930 CSR_WRITE_4(sc, AGE_DMA_CFG, 1931 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 1932 1933 /* Stop TxQ/RxQ. */ 1934 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1935 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 1936 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1937 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 1938 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1939 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1940 break; 1941 DELAY(10); 1942 } 1943 if (i == 0) 1944 printf("%s: stopping Rx/Tx MACs timed out(0x%08x)!\n", 1945 device_xname(sc->sc_dev), reg); 1946 1947 /* Reclaim Rx buffers that have been processed. */ 1948 if (sc->age_cdata.age_rxhead != NULL) 1949 m_freem(sc->age_cdata.age_rxhead); 1950 AGE_RXCHAIN_RESET(sc); 1951 1952 /* 1953 * Free RX and TX mbufs still in the queues. 1954 */ 1955 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1956 rxd = &sc->age_cdata.age_rxdesc[i]; 1957 if (rxd->rx_m != NULL) { 1958 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1959 m_freem(rxd->rx_m); 1960 rxd->rx_m = NULL; 1961 } 1962 } 1963 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1964 txd = &sc->age_cdata.age_txdesc[i]; 1965 if (txd->tx_m != NULL) { 1966 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1967 m_freem(txd->tx_m); 1968 txd->tx_m = NULL; 1969 } 1970 } 1971 } 1972 1973 static void 1974 age_stats_update(struct age_softc *sc) 1975 { 1976 struct ifnet *ifp = &sc->sc_ec.ec_if; 1977 struct age_stats *stat; 1978 struct smb *smb; 1979 1980 stat = &sc->age_stat; 1981 1982 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 1983 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1984 1985 smb = sc->age_rdata.age_smb_block; 1986 if (smb->updated == 0) 1987 return; 1988 1989 /* Rx stats. */ 1990 stat->rx_frames += smb->rx_frames; 1991 stat->rx_bcast_frames += smb->rx_bcast_frames; 1992 stat->rx_mcast_frames += smb->rx_mcast_frames; 1993 stat->rx_pause_frames += smb->rx_pause_frames; 1994 stat->rx_control_frames += smb->rx_control_frames; 1995 stat->rx_crcerrs += smb->rx_crcerrs; 1996 stat->rx_lenerrs += smb->rx_lenerrs; 1997 stat->rx_bytes += smb->rx_bytes; 1998 stat->rx_runts += smb->rx_runts; 1999 stat->rx_fragments += smb->rx_fragments; 2000 stat->rx_pkts_64 += smb->rx_pkts_64; 2001 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2002 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2003 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2004 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2005 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2006 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2007 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2008 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2009 stat->rx_desc_oflows += smb->rx_desc_oflows; 2010 stat->rx_alignerrs += smb->rx_alignerrs; 2011 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2012 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2013 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2014 2015 /* Tx stats. */ 2016 stat->tx_frames += smb->tx_frames; 2017 stat->tx_bcast_frames += smb->tx_bcast_frames; 2018 stat->tx_mcast_frames += smb->tx_mcast_frames; 2019 stat->tx_pause_frames += smb->tx_pause_frames; 2020 stat->tx_excess_defer += smb->tx_excess_defer; 2021 stat->tx_control_frames += smb->tx_control_frames; 2022 stat->tx_deferred += smb->tx_deferred; 2023 stat->tx_bytes += smb->tx_bytes; 2024 stat->tx_pkts_64 += smb->tx_pkts_64; 2025 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2026 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2027 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2028 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2029 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2030 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2031 stat->tx_single_colls += smb->tx_single_colls; 2032 stat->tx_multi_colls += smb->tx_multi_colls; 2033 stat->tx_late_colls += smb->tx_late_colls; 2034 stat->tx_excess_colls += smb->tx_excess_colls; 2035 stat->tx_underrun += smb->tx_underrun; 2036 stat->tx_desc_underrun += smb->tx_desc_underrun; 2037 stat->tx_lenerrs += smb->tx_lenerrs; 2038 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2039 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2040 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2041 2042 /* Update counters in ifnet. */ 2043 ifp->if_opackets += smb->tx_frames; 2044 2045 ifp->if_collisions += smb->tx_single_colls + 2046 smb->tx_multi_colls + smb->tx_late_colls + 2047 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 2048 2049 ifp->if_oerrors += smb->tx_excess_colls + 2050 smb->tx_late_colls + smb->tx_underrun + 2051 smb->tx_pkts_truncated; 2052 2053 ifp->if_ipackets += smb->rx_frames; 2054 2055 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2056 smb->rx_runts + smb->rx_pkts_truncated + 2057 smb->rx_fifo_oflows + smb->rx_desc_oflows + 2058 smb->rx_alignerrs; 2059 2060 /* Update done, clear. */ 2061 smb->updated = 0; 2062 2063 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2064 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2065 } 2066 2067 static void 2068 age_stop_txmac(struct age_softc *sc) 2069 { 2070 uint32_t reg; 2071 int i; 2072 2073 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2074 if ((reg & MAC_CFG_TX_ENB) != 0) { 2075 reg &= ~MAC_CFG_TX_ENB; 2076 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2077 } 2078 /* Stop Tx DMA engine. */ 2079 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2080 if ((reg & DMA_CFG_RD_ENB) != 0) { 2081 reg &= ~DMA_CFG_RD_ENB; 2082 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2083 } 2084 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2085 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2086 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2087 break; 2088 DELAY(10); 2089 } 2090 if (i == 0) 2091 printf("%s: stopping TxMAC timeout!\n", device_xname(sc->sc_dev)); 2092 } 2093 2094 static void 2095 age_stop_rxmac(struct age_softc *sc) 2096 { 2097 uint32_t reg; 2098 int i; 2099 2100 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2101 if ((reg & MAC_CFG_RX_ENB) != 0) { 2102 reg &= ~MAC_CFG_RX_ENB; 2103 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2104 } 2105 /* Stop Rx DMA engine. */ 2106 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2107 if ((reg & DMA_CFG_WR_ENB) != 0) { 2108 reg &= ~DMA_CFG_WR_ENB; 2109 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2110 } 2111 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2112 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2113 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2114 break; 2115 DELAY(10); 2116 } 2117 if (i == 0) 2118 printf("%s: stopping RxMAC timeout!\n", device_xname(sc->sc_dev)); 2119 } 2120 2121 static void 2122 age_init_tx_ring(struct age_softc *sc) 2123 { 2124 struct age_ring_data *rd; 2125 struct age_txdesc *txd; 2126 int i; 2127 2128 sc->age_cdata.age_tx_prod = 0; 2129 sc->age_cdata.age_tx_cons = 0; 2130 sc->age_cdata.age_tx_cnt = 0; 2131 2132 rd = &sc->age_rdata; 2133 memset(rd->age_tx_ring, 0, AGE_TX_RING_SZ); 2134 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2135 txd = &sc->age_cdata.age_txdesc[i]; 2136 txd->tx_desc = &rd->age_tx_ring[i]; 2137 txd->tx_m = NULL; 2138 } 2139 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 2140 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2141 } 2142 2143 static int 2144 age_init_rx_ring(struct age_softc *sc) 2145 { 2146 struct age_ring_data *rd; 2147 struct age_rxdesc *rxd; 2148 int i; 2149 2150 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 2151 rd = &sc->age_rdata; 2152 memset(rd->age_rx_ring, 0, AGE_RX_RING_SZ); 2153 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2154 rxd = &sc->age_cdata.age_rxdesc[i]; 2155 rxd->rx_m = NULL; 2156 rxd->rx_desc = &rd->age_rx_ring[i]; 2157 if (age_newbuf(sc, rxd, 1) != 0) 2158 return ENOBUFS; 2159 } 2160 2161 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 0, 2162 sc->age_cdata.age_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2163 2164 return 0; 2165 } 2166 2167 static void 2168 age_init_rr_ring(struct age_softc *sc) 2169 { 2170 struct age_ring_data *rd; 2171 2172 sc->age_cdata.age_rr_cons = 0; 2173 AGE_RXCHAIN_RESET(sc); 2174 2175 rd = &sc->age_rdata; 2176 memset(rd->age_rr_ring, 0, AGE_RR_RING_SZ); 2177 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 2178 sc->age_cdata.age_rr_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2179 } 2180 2181 static void 2182 age_init_cmb_block(struct age_softc *sc) 2183 { 2184 struct age_ring_data *rd; 2185 2186 rd = &sc->age_rdata; 2187 memset(rd->age_cmb_block, 0, AGE_CMB_BLOCK_SZ); 2188 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 2189 sc->age_cdata.age_cmb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2190 } 2191 2192 static void 2193 age_init_smb_block(struct age_softc *sc) 2194 { 2195 struct age_ring_data *rd; 2196 2197 rd = &sc->age_rdata; 2198 memset(rd->age_smb_block, 0, AGE_SMB_BLOCK_SZ); 2199 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2200 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2201 } 2202 2203 static int 2204 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd, int init) 2205 { 2206 struct rx_desc *desc; 2207 struct mbuf *m; 2208 bus_dmamap_t map; 2209 int error; 2210 2211 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 2212 if (m == NULL) 2213 return ENOBUFS; 2214 MCLGET(m, init ? M_WAITOK : M_DONTWAIT); 2215 if (!(m->m_flags & M_EXT)) { 2216 m_freem(m); 2217 return ENOBUFS; 2218 } 2219 2220 m->m_len = m->m_pkthdr.len = MCLBYTES; 2221 m_adj(m, ETHER_ALIGN); 2222 2223 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2224 sc->age_cdata.age_rx_sparemap, m, BUS_DMA_NOWAIT); 2225 2226 if (error != 0) { 2227 if (!error) { 2228 bus_dmamap_unload(sc->sc_dmat, 2229 sc->age_cdata.age_rx_sparemap); 2230 error = EFBIG; 2231 printf("%s: too many segments?!\n", 2232 device_xname(sc->sc_dev)); 2233 } 2234 m_freem(m); 2235 2236 if (init) 2237 printf("%s: can't load RX mbuf\n", device_xname(sc->sc_dev)); 2238 return error; 2239 } 2240 2241 if (rxd->rx_m != NULL) { 2242 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2243 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2244 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2245 } 2246 map = rxd->rx_dmamap; 2247 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 2248 sc->age_cdata.age_rx_sparemap = map; 2249 rxd->rx_m = m; 2250 2251 desc = rxd->rx_desc; 2252 desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 2253 desc->len = 2254 htole32((rxd->rx_dmamap->dm_segs[0].ds_len & AGE_RD_LEN_MASK) << 2255 AGE_RD_LEN_SHIFT); 2256 2257 return 0; 2258 } 2259 2260 static void 2261 age_rxvlan(struct age_softc *sc) 2262 { 2263 uint32_t reg; 2264 2265 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2266 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2267 if (sc->sc_ec.ec_capabilities & ETHERCAP_VLAN_HWTAGGING) 2268 reg |= MAC_CFG_VLAN_TAG_STRIP; 2269 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2270 } 2271 2272 static void 2273 age_rxfilter(struct age_softc *sc) 2274 { 2275 struct ethercom *ec = &sc->sc_ec; 2276 struct ifnet *ifp = &sc->sc_ec.ec_if; 2277 struct ether_multi *enm; 2278 struct ether_multistep step; 2279 uint32_t crc; 2280 uint32_t mchash[2]; 2281 uint32_t rxcfg; 2282 2283 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 2284 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2285 2286 if (ifp->if_flags & IFF_BROADCAST) 2287 rxcfg |= MAC_CFG_BCAST; 2288 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 2289 if (ifp->if_flags & IFF_PROMISC) 2290 rxcfg |= MAC_CFG_PROMISC; 2291 if (ifp->if_flags & IFF_ALLMULTI) 2292 rxcfg |= MAC_CFG_ALLMULTI; 2293 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF); 2294 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF); 2295 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 2296 return; 2297 } 2298 2299 /* Program new filter. */ 2300 memset(mchash, 0, sizeof(mchash)); 2301 2302 ETHER_FIRST_MULTI(step, ec, enm); 2303 while (enm != NULL) { 2304 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 2305 enm->enm_addrlo), ETHER_ADDR_LEN); 2306 2307 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2308 ETHER_NEXT_MULTI(step, enm); 2309 } 2310 2311 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 2312 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 2313 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 2314 } 2315
Indexes created Mon Sep 29 21:09:56 GMT 2025