if_age.c revision 1.28.2.3
1 /* $NetBSD: if_age.c,v 1.28.2.3 2009/11/08 21:55:46 snj Exp $ */ 2 /* $OpenBSD: if_age.c,v 1.1 2009/01/16 05:00:34 kevlo Exp $ */ 3 4 /*- 5 * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: if_age.c,v 1.28.2.3 2009/11/08 21:55:46 snj Exp $"); 35 36 #include "bpfilter.h" 37 #include "vlan.h" 38 39 #include <sys/param.h> 40 #include <sys/proc.h> 41 #include <sys/endian.h> 42 #include <sys/systm.h> 43 #include <sys/types.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/queue.h> 47 #include <sys/kernel.h> 48 #include <sys/device.h> 49 #include <sys/callout.h> 50 #include <sys/socket.h> 51 52 #include <net/if.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #ifdef INET 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/in_var.h> 61 #include <netinet/ip.h> 62 #endif 63 64 #include <net/if_types.h> 65 #include <net/if_vlanvar.h> 66 67 #if NBPFILTER > 0 68 #include <net/bpf.h> 69 #endif 70 71 #include <sys/rnd.h> 72 73 #include <dev/mii/mii.h> 74 #include <dev/mii/miivar.h> 75 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/pcidevs.h> 79 80 #include <dev/pci/if_agereg.h> 81 82 static int age_match(device_t, cfdata_t, void *); 83 static void age_attach(device_t, device_t, void *); 84 static int age_detach(device_t, int); 85 86 static bool age_resume(device_t PMF_FN_PROTO); 87 88 static int age_miibus_readreg(device_t, int, int); 89 static void age_miibus_writereg(device_t, int, int, int); 90 static void age_miibus_statchg(device_t); 91 92 static int age_init(struct ifnet *); 93 static int age_ioctl(struct ifnet *, u_long, void *); 94 static void age_start(struct ifnet *); 95 static void age_watchdog(struct ifnet *); 96 static void age_mediastatus(struct ifnet *, struct ifmediareq *); 97 static int age_mediachange(struct ifnet *); 98 99 static int age_intr(void *); 100 static int age_read_vpd_word(struct age_softc *, uint32_t, uint32_t, uint32_t *); 101 static int age_dma_alloc(struct age_softc *); 102 static void age_dma_free(struct age_softc *); 103 static void age_get_macaddr(struct age_softc *, uint8_t[]); 104 static void age_phy_reset(struct age_softc *); 105 106 static int age_encap(struct age_softc *, struct mbuf **); 107 static void age_init_tx_ring(struct age_softc *); 108 static int age_init_rx_ring(struct age_softc *); 109 static void age_init_rr_ring(struct age_softc *); 110 static void age_init_cmb_block(struct age_softc *); 111 static void age_init_smb_block(struct age_softc *); 112 static int age_newbuf(struct age_softc *, struct age_rxdesc *, int); 113 static void age_mac_config(struct age_softc *); 114 static void age_txintr(struct age_softc *, int); 115 static void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 116 static void age_rxintr(struct age_softc *, int); 117 static void age_tick(void *); 118 static void age_reset(struct age_softc *); 119 static void age_stop(struct ifnet *, int); 120 static void age_stats_update(struct age_softc *); 121 static void age_stop_txmac(struct age_softc *); 122 static void age_stop_rxmac(struct age_softc *); 123 static void age_rxvlan(struct age_softc *sc); 124 static void age_rxfilter(struct age_softc *); 125 126 CFATTACH_DECL_NEW(age, sizeof(struct age_softc), 127 age_match, age_attach, age_detach, NULL); 128 129 int agedebug = 0; 130 #define DPRINTF(x) do { if (agedebug) printf x; } while (0) 131 132 #define ETHER_ALIGN 2 133 #define AGE_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 134 135 static int 136 age_match(device_t dev, cfdata_t match, void *aux) 137 { 138 struct pci_attach_args *pa = aux; 139 140 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && 141 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_GIGA); 142 } 143 144 static void 145 age_attach(device_t parent, device_t self, void *aux) 146 { 147 struct age_softc *sc = device_private(self); 148 struct pci_attach_args *pa = aux; 149 pci_intr_handle_t ih; 150 const char *intrstr; 151 struct ifnet *ifp = &sc->sc_ec.ec_if; 152 pcireg_t memtype; 153 int error = 0; 154 155 aprint_naive("\n"); 156 aprint_normal(": Attansic/Atheros L1 Gigabit Ethernet\n"); 157 158 sc->sc_dev = self; 159 sc->sc_dmat = pa->pa_dmat; 160 sc->sc_pct = pa->pa_pc; 161 sc->sc_pcitag = pa->pa_tag; 162 163 /* 164 * Allocate IO memory 165 */ 166 memtype = pci_mapreg_type(sc->sc_pct, sc->sc_pcitag, AGE_PCIR_BAR); 167 switch (memtype) { 168 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 169 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 170 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 171 break; 172 default: 173 aprint_error_dev(self, "invalid base address register\n"); 174 break; 175 } 176 177 if (pci_mapreg_map(pa, AGE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 178 &sc->sc_mem_bh, NULL, &sc->sc_mem_size) != 0) { 179 aprint_error_dev(self, "could not map mem space\n"); 180 return; 181 } 182 183 if (pci_intr_map(pa, &ih) != 0) { 184 aprint_error_dev(self, "could not map interrupt\n"); 185 goto fail; 186 } 187 188 /* 189 * Allocate IRQ 190 */ 191 intrstr = pci_intr_string(sc->sc_pct, ih); 192 sc->sc_irq_handle = pci_intr_establish(sc->sc_pct, ih, IPL_NET, 193 age_intr, sc); 194 if (sc->sc_irq_handle == NULL) { 195 aprint_error_dev(self, "could not establish interrupt"); 196 if (intrstr != NULL) 197 aprint_error(" at %s", intrstr); 198 aprint_error("\n"); 199 goto fail; 200 } 201 aprint_normal_dev(self, "%s\n", intrstr); 202 203 /* Set PHY address. */ 204 sc->age_phyaddr = AGE_PHY_ADDR; 205 206 /* Reset PHY. */ 207 age_phy_reset(sc); 208 209 /* Reset the ethernet controller. */ 210 age_reset(sc); 211 212 /* Get PCI and chip id/revision. */ 213 sc->age_rev = PCI_REVISION(pa->pa_class); 214 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 215 MASTER_CHIP_REV_SHIFT; 216 217 aprint_debug_dev(self, "PCI device revision : 0x%04x\n", sc->age_rev); 218 aprint_debug_dev(self, "Chip id/revision : 0x%04x\n", sc->age_chip_rev); 219 220 if (agedebug) { 221 aprint_debug_dev(self, "%d Tx FIFO, %d Rx FIFO\n", 222 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 223 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 224 } 225 226 /* Set max allowable DMA size. */ 227 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 228 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 229 230 /* Allocate DMA stuffs */ 231 error = age_dma_alloc(sc); 232 if (error) 233 goto fail; 234 235 callout_init(&sc->sc_tick_ch, 0); 236 callout_setfunc(&sc->sc_tick_ch, age_tick, sc); 237 238 /* Load station address. */ 239 age_get_macaddr(sc, sc->sc_enaddr); 240 241 aprint_normal_dev(self, "Ethernet address %s\n", 242 ether_sprintf(sc->sc_enaddr)); 243 244 ifp->if_softc = sc; 245 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 246 ifp->if_init = age_init; 247 ifp->if_ioctl = age_ioctl; 248 ifp->if_start = age_start; 249 ifp->if_stop = age_stop; 250 ifp->if_watchdog = age_watchdog; 251 ifp->if_baudrate = IF_Gbps(1); 252 IFQ_SET_MAXLEN(&ifp->if_snd, AGE_TX_RING_CNT - 1); 253 IFQ_SET_READY(&ifp->if_snd); 254 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 255 256 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 257 258 #ifdef AGE_CHECKSUM 259 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 260 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 261 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 262 #endif 263 264 #if NVLAN > 0 265 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 266 #endif 267 268 /* Set up MII bus. */ 269 sc->sc_miibus.mii_ifp = ifp; 270 sc->sc_miibus.mii_readreg = age_miibus_readreg; 271 sc->sc_miibus.mii_writereg = age_miibus_writereg; 272 sc->sc_miibus.mii_statchg = age_miibus_statchg; 273 274 sc->sc_ec.ec_mii = &sc->sc_miibus; 275 ifmedia_init(&sc->sc_miibus.mii_media, 0, age_mediachange, 276 age_mediastatus); 277 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 278 MII_OFFSET_ANY, MIIF_DOPAUSE); 279 280 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 281 aprint_error_dev(self, "no PHY found!\n"); 282 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 283 0, NULL); 284 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 285 } else 286 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 287 288 if_attach(ifp); 289 ether_ifattach(ifp, sc->sc_enaddr); 290 291 if (!pmf_device_register(self, NULL, age_resume)) 292 aprint_error_dev(self, "couldn't establish power handler\n"); 293 else 294 pmf_class_network_register(self, ifp); 295 296 return; 297 298 fail: 299 age_dma_free(sc); 300 if (sc->sc_irq_handle != NULL) { 301 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 302 sc->sc_irq_handle = NULL; 303 } 304 if (sc->sc_mem_size) { 305 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 306 sc->sc_mem_size = 0; 307 } 308 } 309 310 static int 311 age_detach(device_t self, int flags) 312 { 313 struct age_softc *sc = device_private(self); 314 struct ifnet *ifp = &sc->sc_ec.ec_if; 315 int s; 316 317 pmf_device_deregister(self); 318 s = splnet(); 319 age_stop(ifp, 0); 320 splx(s); 321 322 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 323 324 /* Delete all remaining media. */ 325 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 326 327 ether_ifdetach(ifp); 328 if_detach(ifp); 329 age_dma_free(sc); 330 331 if (sc->sc_irq_handle != NULL) { 332 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 333 sc->sc_irq_handle = NULL; 334 } 335 if (sc->sc_mem_size) { 336 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 337 sc->sc_mem_size = 0; 338 } 339 return 0; 340 } 341 342 /* 343 * Read a PHY register on the MII of the L1. 344 */ 345 static int 346 age_miibus_readreg(device_t dev, int phy, int reg) 347 { 348 struct age_softc *sc = device_private(dev); 349 uint32_t v; 350 int i; 351 352 if (phy != sc->age_phyaddr) 353 return 0; 354 355 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 356 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 357 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 358 DELAY(1); 359 v = CSR_READ_4(sc, AGE_MDIO); 360 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 361 break; 362 } 363 364 if (i == 0) { 365 printf("%s: phy read timeout: phy %d, reg %d\n", 366 device_xname(sc->sc_dev), phy, reg); 367 return 0; 368 } 369 370 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 371 } 372 373 /* 374 * Write a PHY register on the MII of the L1. 375 */ 376 static void 377 age_miibus_writereg(device_t dev, int phy, int reg, int val) 378 { 379 struct age_softc *sc = device_private(dev); 380 uint32_t v; 381 int i; 382 383 if (phy != sc->age_phyaddr) 384 return; 385 386 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 387 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 388 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 389 390 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 391 DELAY(1); 392 v = CSR_READ_4(sc, AGE_MDIO); 393 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 394 break; 395 } 396 397 if (i == 0) { 398 printf("%s: phy write timeout: phy %d, reg %d\n", 399 device_xname(sc->sc_dev), phy, reg); 400 } 401 } 402 403 /* 404 * Callback from MII layer when media changes. 405 */ 406 static void 407 age_miibus_statchg(device_t dev) 408 { 409 struct age_softc *sc = device_private(dev); 410 struct ifnet *ifp = &sc->sc_ec.ec_if; 411 struct mii_data *mii; 412 413 if ((ifp->if_flags & IFF_RUNNING) == 0) 414 return; 415 416 mii = &sc->sc_miibus; 417 418 sc->age_flags &= ~AGE_FLAG_LINK; 419 if ((mii->mii_media_status & IFM_AVALID) != 0) { 420 switch (IFM_SUBTYPE(mii->mii_media_active)) { 421 case IFM_10_T: 422 case IFM_100_TX: 423 case IFM_1000_T: 424 sc->age_flags |= AGE_FLAG_LINK; 425 break; 426 default: 427 break; 428 } 429 } 430 431 /* Stop Rx/Tx MACs. */ 432 age_stop_rxmac(sc); 433 age_stop_txmac(sc); 434 435 /* Program MACs with resolved speed/duplex/flow-control. */ 436 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 437 uint32_t reg; 438 439 age_mac_config(sc); 440 reg = CSR_READ_4(sc, AGE_MAC_CFG); 441 /* Restart DMA engine and Tx/Rx MAC. */ 442 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 443 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 444 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 445 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 446 } 447 } 448 449 /* 450 * Get the current interface media status. 451 */ 452 static void 453 age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 454 { 455 struct age_softc *sc = ifp->if_softc; 456 struct mii_data *mii = &sc->sc_miibus; 457 458 mii_pollstat(mii); 459 ifmr->ifm_status = mii->mii_media_status; 460 ifmr->ifm_active = mii->mii_media_active; 461 } 462 463 /* 464 * Set hardware to newly-selected media. 465 */ 466 static int 467 age_mediachange(struct ifnet *ifp) 468 { 469 struct age_softc *sc = ifp->if_softc; 470 struct mii_data *mii = &sc->sc_miibus; 471 int error; 472 473 if (mii->mii_instance != 0) { 474 struct mii_softc *miisc; 475 476 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 477 mii_phy_reset(miisc); 478 } 479 error = mii_mediachg(mii); 480 481 return error; 482 } 483 484 static int 485 age_intr(void *arg) 486 { 487 struct age_softc *sc = arg; 488 struct ifnet *ifp = &sc->sc_ec.ec_if; 489 struct cmb *cmb; 490 uint32_t status; 491 492 status = CSR_READ_4(sc, AGE_INTR_STATUS); 493 if (status == 0 || (status & AGE_INTRS) == 0) 494 return 0; 495 496 cmb = sc->age_rdata.age_cmb_block; 497 if (cmb == NULL) { 498 /* Happens when bringing up the interface 499 * w/o having a carrier. Ack. the interrupt. 500 */ 501 CSR_WRITE_4(sc, AGE_INTR_STATUS, status); 502 return 0; 503 } 504 505 /* Disable interrupts. */ 506 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 507 508 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 509 sc->age_cdata.age_cmb_block_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 510 status = le32toh(cmb->intr_status); 511 if ((status & AGE_INTRS) == 0) 512 goto back; 513 514 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 515 TPD_CONS_SHIFT; 516 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 517 RRD_PROD_SHIFT; 518 519 /* Let hardware know CMB was served. */ 520 cmb->intr_status = 0; 521 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 522 sc->age_cdata.age_cmb_block_map->dm_mapsize, 523 BUS_DMASYNC_PREWRITE); 524 525 if (ifp->if_flags & IFF_RUNNING) { 526 if (status & INTR_CMB_RX) 527 age_rxintr(sc, sc->age_rr_prod); 528 529 if (status & INTR_CMB_TX) 530 age_txintr(sc, sc->age_tpd_cons); 531 532 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 533 if (status & INTR_DMA_RD_TO_RST) 534 printf("%s: DMA read error! -- resetting\n", 535 device_xname(sc->sc_dev)); 536 if (status & INTR_DMA_WR_TO_RST) 537 printf("%s: DMA write error! -- resetting\n", 538 device_xname(sc->sc_dev)); 539 age_init(ifp); 540 } 541 542 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 543 age_start(ifp); 544 545 if (status & INTR_SMB) 546 age_stats_update(sc); 547 } 548 549 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 550 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 551 sc->age_cdata.age_cmb_block_map->dm_mapsize, 552 BUS_DMASYNC_POSTREAD); 553 554 back: 555 /* Re-enable interrupts. */ 556 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 557 558 return 1; 559 } 560 561 static int 562 age_read_vpd_word(struct age_softc *sc, uint32_t vpdc, uint32_t offset, 563 uint32_t *word) 564 { 565 int i; 566 pcireg_t rv; 567 568 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_VPD_ADDRESS(vpdc), 569 offset << PCI_VPD_ADDRESS_SHIFT); 570 for (i = AGE_TIMEOUT; i > 0; i--) { 571 DELAY(10); 572 rv = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 573 PCI_VPD_ADDRESS(vpdc)); 574 if ((rv & PCI_VPD_OPFLAG) == PCI_VPD_OPFLAG) 575 break; 576 } 577 if (i == 0) { 578 printf("%s: VPD read timeout!\n", device_xname(sc->sc_dev)); 579 *word = 0; 580 return ETIMEDOUT; 581 } 582 583 *word = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_VPD_DATAREG(vpdc)); 584 return 0; 585 } 586 587 static void 588 age_get_macaddr(struct age_softc *sc, uint8_t eaddr[]) 589 { 590 uint32_t ea[2], off, reg, word; 591 int vpd_error, match, vpdc; 592 593 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 594 if ((reg & SPI_VPD_ENB) != 0) { 595 /* Get VPD stored in TWSI EEPROM. */ 596 reg &= ~SPI_VPD_ENB; 597 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 598 } 599 600 vpd_error = 0; 601 ea[0] = ea[1] = 0; 602 if ((vpd_error = pci_get_capability(sc->sc_pct, sc->sc_pcitag, 603 PCI_CAP_VPD, &vpdc, NULL))) { 604 /* 605 * PCI VPD capability exists, but it seems that it's 606 * not in the standard form as stated in PCI VPD 607 * specification such that driver could not use 608 * pci_get_vpd_readonly(9) with keyword 'NA'. 609 * Search VPD data starting at address 0x0100. The data 610 * should be used as initializers to set AGE_PAR0, 611 * AGE_PAR1 register including other PCI configuration 612 * registers. 613 */ 614 word = 0; 615 match = 0; 616 reg = 0; 617 for (off = AGE_VPD_REG_CONF_START; off < AGE_VPD_REG_CONF_END; 618 off += sizeof(uint32_t)) { 619 vpd_error = age_read_vpd_word(sc, vpdc, off, &word); 620 if (vpd_error != 0) 621 break; 622 if (match != 0) { 623 switch (reg) { 624 case AGE_PAR0: 625 ea[0] = word; 626 break; 627 case AGE_PAR1: 628 ea[1] = word; 629 break; 630 default: 631 break; 632 } 633 match = 0; 634 } else if ((word & 0xFF) == AGE_VPD_REG_CONF_SIG) { 635 match = 1; 636 reg = word >> 16; 637 } else 638 break; 639 } 640 if (off >= AGE_VPD_REG_CONF_END) 641 vpd_error = ENOENT; 642 if (vpd_error == 0) { 643 /* 644 * Don't blindly trust ethernet address obtained 645 * from VPD. Check whether ethernet address is 646 * valid one. Otherwise fall-back to reading 647 * PAR register. 648 */ 649 ea[1] &= 0xFFFF; 650 if ((ea[0] == 0 && ea[1] == 0) || 651 (ea[0] == 0xFFFFFFFF && ea[1] == 0xFFFF)) { 652 if (agedebug) 653 printf("%s: invalid ethernet address " 654 "returned from VPD.\n", 655 device_xname(sc->sc_dev)); 656 vpd_error = EINVAL; 657 } 658 } 659 if (vpd_error != 0 && (agedebug)) 660 printf("%s: VPD access failure!\n", 661 device_xname(sc->sc_dev)); 662 } else { 663 if (agedebug) 664 printf("%s: PCI VPD capability not found!\n", 665 device_xname(sc->sc_dev)); 666 } 667 668 /* 669 * It seems that L1 also provides a way to extract ethernet 670 * address via SPI flash interface. Because SPI flash memory 671 * device of different vendors vary in their instruction 672 * codes for read ID instruction, it's very hard to get 673 * instructions codes without detailed information for the 674 * flash memory device used on ethernet controller. To simplify 675 * code, just read AGE_PAR0/AGE_PAR1 register to get ethernet 676 * address which is supposed to be set by hardware during 677 * power on reset. 678 */ 679 if (vpd_error != 0) { 680 /* 681 * VPD is mapped to SPI flash memory or BIOS set it. 682 */ 683 ea[0] = CSR_READ_4(sc, AGE_PAR0); 684 ea[1] = CSR_READ_4(sc, AGE_PAR1); 685 } 686 687 ea[1] &= 0xFFFF; 688 eaddr[0] = (ea[1] >> 8) & 0xFF; 689 eaddr[1] = (ea[1] >> 0) & 0xFF; 690 eaddr[2] = (ea[0] >> 24) & 0xFF; 691 eaddr[3] = (ea[0] >> 16) & 0xFF; 692 eaddr[4] = (ea[0] >> 8) & 0xFF; 693 eaddr[5] = (ea[0] >> 0) & 0xFF; 694 } 695 696 static void 697 age_phy_reset(struct age_softc *sc) 698 { 699 /* Reset PHY. */ 700 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 701 DELAY(1000); 702 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 703 DELAY(1000); 704 } 705 706 static int 707 age_dma_alloc(struct age_softc *sc) 708 { 709 struct age_txdesc *txd; 710 struct age_rxdesc *rxd; 711 int nsegs, error, i; 712 713 /* 714 * Create DMA stuffs for TX ring 715 */ 716 error = bus_dmamap_create(sc->sc_dmat, AGE_TX_RING_SZ, 1, 717 AGE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_tx_ring_map); 718 if (error) { 719 sc->age_cdata.age_tx_ring_map = NULL; 720 return ENOBUFS; 721 } 722 723 /* Allocate DMA'able memory for TX ring */ 724 error = bus_dmamem_alloc(sc->sc_dmat, AGE_TX_RING_SZ, 725 ETHER_ALIGN, 0, &sc->age_rdata.age_tx_ring_seg, 1, 726 &nsegs, BUS_DMA_WAITOK); 727 if (error) { 728 printf("%s: could not allocate DMA'able memory for Tx ring, " 729 "error = %i\n", device_xname(sc->sc_dev), error); 730 return error; 731 } 732 733 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_tx_ring_seg, 734 nsegs, AGE_TX_RING_SZ, (void **)&sc->age_rdata.age_tx_ring, 735 BUS_DMA_NOWAIT); 736 if (error) 737 return ENOBUFS; 738 739 memset(sc->age_rdata.age_tx_ring, 0, AGE_TX_RING_SZ); 740 741 /* Load the DMA map for Tx ring. */ 742 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 743 sc->age_rdata.age_tx_ring, AGE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 744 if (error) { 745 printf("%s: could not load DMA'able memory for Tx ring, " 746 "error = %i\n", device_xname(sc->sc_dev), error); 747 bus_dmamem_free(sc->sc_dmat, 748 &sc->age_rdata.age_tx_ring_seg, 1); 749 return error; 750 } 751 752 sc->age_rdata.age_tx_ring_paddr = 753 sc->age_cdata.age_tx_ring_map->dm_segs[0].ds_addr; 754 755 /* 756 * Create DMA stuffs for RX ring 757 */ 758 error = bus_dmamap_create(sc->sc_dmat, AGE_RX_RING_SZ, 1, 759 AGE_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_ring_map); 760 if (error) { 761 sc->age_cdata.age_rx_ring_map = NULL; 762 return ENOBUFS; 763 } 764 765 /* Allocate DMA'able memory for RX ring */ 766 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RX_RING_SZ, 767 ETHER_ALIGN, 0, &sc->age_rdata.age_rx_ring_seg, 1, 768 &nsegs, BUS_DMA_WAITOK); 769 if (error) { 770 printf("%s: could not allocate DMA'able memory for Rx ring, " 771 "error = %i.\n", device_xname(sc->sc_dev), error); 772 return error; 773 } 774 775 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rx_ring_seg, 776 nsegs, AGE_RX_RING_SZ, (void **)&sc->age_rdata.age_rx_ring, 777 BUS_DMA_NOWAIT); 778 if (error) 779 return ENOBUFS; 780 781 memset(sc->age_rdata.age_rx_ring, 0, AGE_RX_RING_SZ); 782 783 /* Load the DMA map for Rx ring. */ 784 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 785 sc->age_rdata.age_rx_ring, AGE_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 786 if (error) { 787 printf("%s: could not load DMA'able memory for Rx ring, " 788 "error = %i.\n", device_xname(sc->sc_dev), error); 789 bus_dmamem_free(sc->sc_dmat, 790 &sc->age_rdata.age_rx_ring_seg, 1); 791 return error; 792 } 793 794 sc->age_rdata.age_rx_ring_paddr = 795 sc->age_cdata.age_rx_ring_map->dm_segs[0].ds_addr; 796 797 /* 798 * Create DMA stuffs for RX return ring 799 */ 800 error = bus_dmamap_create(sc->sc_dmat, AGE_RR_RING_SZ, 1, 801 AGE_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rr_ring_map); 802 if (error) { 803 sc->age_cdata.age_rr_ring_map = NULL; 804 return ENOBUFS; 805 } 806 807 /* Allocate DMA'able memory for RX return ring */ 808 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RR_RING_SZ, 809 ETHER_ALIGN, 0, &sc->age_rdata.age_rr_ring_seg, 1, 810 &nsegs, BUS_DMA_WAITOK); 811 if (error) { 812 printf("%s: could not allocate DMA'able memory for Rx " 813 "return ring, error = %i.\n", 814 device_xname(sc->sc_dev), error); 815 return error; 816 } 817 818 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rr_ring_seg, 819 nsegs, AGE_RR_RING_SZ, (void **)&sc->age_rdata.age_rr_ring, 820 BUS_DMA_NOWAIT); 821 if (error) 822 return ENOBUFS; 823 824 memset(sc->age_rdata.age_rr_ring, 0, AGE_RR_RING_SZ); 825 826 /* Load the DMA map for Rx return ring. */ 827 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 828 sc->age_rdata.age_rr_ring, AGE_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 829 if (error) { 830 printf("%s: could not load DMA'able memory for Rx return ring, " 831 "error = %i\n", device_xname(sc->sc_dev), error); 832 bus_dmamem_free(sc->sc_dmat, 833 &sc->age_rdata.age_rr_ring_seg, 1); 834 return error; 835 } 836 837 sc->age_rdata.age_rr_ring_paddr = 838 sc->age_cdata.age_rr_ring_map->dm_segs[0].ds_addr; 839 840 /* 841 * Create DMA stuffs for CMB block 842 */ 843 error = bus_dmamap_create(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 1, 844 AGE_CMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 845 &sc->age_cdata.age_cmb_block_map); 846 if (error) { 847 sc->age_cdata.age_cmb_block_map = NULL; 848 return ENOBUFS; 849 } 850 851 /* Allocate DMA'able memory for CMB block */ 852 error = bus_dmamem_alloc(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 853 ETHER_ALIGN, 0, &sc->age_rdata.age_cmb_block_seg, 1, 854 &nsegs, BUS_DMA_WAITOK); 855 if (error) { 856 printf("%s: could not allocate DMA'able memory for " 857 "CMB block, error = %i\n", device_xname(sc->sc_dev), error); 858 return error; 859 } 860 861 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_cmb_block_seg, 862 nsegs, AGE_CMB_BLOCK_SZ, (void **)&sc->age_rdata.age_cmb_block, 863 BUS_DMA_NOWAIT); 864 if (error) 865 return ENOBUFS; 866 867 memset(sc->age_rdata.age_cmb_block, 0, AGE_CMB_BLOCK_SZ); 868 869 /* Load the DMA map for CMB block. */ 870 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 871 sc->age_rdata.age_cmb_block, AGE_CMB_BLOCK_SZ, NULL, 872 BUS_DMA_WAITOK); 873 if (error) { 874 printf("%s: could not load DMA'able memory for CMB block, " 875 "error = %i\n", device_xname(sc->sc_dev), error); 876 bus_dmamem_free(sc->sc_dmat, 877 &sc->age_rdata.age_cmb_block_seg, 1); 878 return error; 879 } 880 881 sc->age_rdata.age_cmb_block_paddr = 882 sc->age_cdata.age_cmb_block_map->dm_segs[0].ds_addr; 883 884 /* 885 * Create DMA stuffs for SMB block 886 */ 887 error = bus_dmamap_create(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 1, 888 AGE_SMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 889 &sc->age_cdata.age_smb_block_map); 890 if (error) { 891 sc->age_cdata.age_smb_block_map = NULL; 892 return ENOBUFS; 893 } 894 895 /* Allocate DMA'able memory for SMB block */ 896 error = bus_dmamem_alloc(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 897 ETHER_ALIGN, 0, &sc->age_rdata.age_smb_block_seg, 1, 898 &nsegs, BUS_DMA_WAITOK); 899 if (error) { 900 printf("%s: could not allocate DMA'able memory for " 901 "SMB block, error = %i\n", device_xname(sc->sc_dev), error); 902 return error; 903 } 904 905 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_smb_block_seg, 906 nsegs, AGE_SMB_BLOCK_SZ, (void **)&sc->age_rdata.age_smb_block, 907 BUS_DMA_NOWAIT); 908 if (error) 909 return ENOBUFS; 910 911 memset(sc->age_rdata.age_smb_block, 0, AGE_SMB_BLOCK_SZ); 912 913 /* Load the DMA map for SMB block */ 914 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 915 sc->age_rdata.age_smb_block, AGE_SMB_BLOCK_SZ, NULL, 916 BUS_DMA_WAITOK); 917 if (error) { 918 printf("%s: could not load DMA'able memory for SMB block, " 919 "error = %i\n", device_xname(sc->sc_dev), error); 920 bus_dmamem_free(sc->sc_dmat, 921 &sc->age_rdata.age_smb_block_seg, 1); 922 return error; 923 } 924 925 sc->age_rdata.age_smb_block_paddr = 926 sc->age_cdata.age_smb_block_map->dm_segs[0].ds_addr; 927 928 /* Create DMA maps for Tx buffers. */ 929 for (i = 0; i < AGE_TX_RING_CNT; i++) { 930 txd = &sc->age_cdata.age_txdesc[i]; 931 txd->tx_m = NULL; 932 txd->tx_dmamap = NULL; 933 error = bus_dmamap_create(sc->sc_dmat, AGE_TSO_MAXSIZE, 934 AGE_MAXTXSEGS, AGE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 935 &txd->tx_dmamap); 936 if (error) { 937 txd->tx_dmamap = NULL; 938 printf("%s: could not create Tx dmamap, error = %i.\n", 939 device_xname(sc->sc_dev), error); 940 return error; 941 } 942 } 943 944 /* Create DMA maps for Rx buffers. */ 945 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 946 BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_sparemap); 947 if (error) { 948 sc->age_cdata.age_rx_sparemap = NULL; 949 printf("%s: could not create spare Rx dmamap, error = %i.\n", 950 device_xname(sc->sc_dev), error); 951 return error; 952 } 953 for (i = 0; i < AGE_RX_RING_CNT; i++) { 954 rxd = &sc->age_cdata.age_rxdesc[i]; 955 rxd->rx_m = NULL; 956 rxd->rx_dmamap = NULL; 957 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 958 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 959 if (error) { 960 rxd->rx_dmamap = NULL; 961 printf("%s: could not create Rx dmamap, error = %i.\n", 962 device_xname(sc->sc_dev), error); 963 return error; 964 } 965 } 966 967 return 0; 968 } 969 970 static void 971 age_dma_free(struct age_softc *sc) 972 { 973 struct age_txdesc *txd; 974 struct age_rxdesc *rxd; 975 int i; 976 977 /* Tx buffers */ 978 for (i = 0; i < AGE_TX_RING_CNT; i++) { 979 txd = &sc->age_cdata.age_txdesc[i]; 980 if (txd->tx_dmamap != NULL) { 981 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 982 txd->tx_dmamap = NULL; 983 } 984 } 985 /* Rx buffers */ 986 for (i = 0; i < AGE_RX_RING_CNT; i++) { 987 rxd = &sc->age_cdata.age_rxdesc[i]; 988 if (rxd->rx_dmamap != NULL) { 989 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 990 rxd->rx_dmamap = NULL; 991 } 992 } 993 if (sc->age_cdata.age_rx_sparemap != NULL) { 994 bus_dmamap_destroy(sc->sc_dmat, sc->age_cdata.age_rx_sparemap); 995 sc->age_cdata.age_rx_sparemap = NULL; 996 } 997 998 /* Tx ring. */ 999 if (sc->age_cdata.age_tx_ring_map != NULL) 1000 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_tx_ring_map); 1001 if (sc->age_cdata.age_tx_ring_map != NULL && 1002 sc->age_rdata.age_tx_ring != NULL) 1003 bus_dmamem_free(sc->sc_dmat, 1004 &sc->age_rdata.age_tx_ring_seg, 1); 1005 sc->age_rdata.age_tx_ring = NULL; 1006 sc->age_cdata.age_tx_ring_map = NULL; 1007 1008 /* Rx ring. */ 1009 if (sc->age_cdata.age_rx_ring_map != NULL) 1010 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rx_ring_map); 1011 if (sc->age_cdata.age_rx_ring_map != NULL && 1012 sc->age_rdata.age_rx_ring != NULL) 1013 bus_dmamem_free(sc->sc_dmat, 1014 &sc->age_rdata.age_rx_ring_seg, 1); 1015 sc->age_rdata.age_rx_ring = NULL; 1016 sc->age_cdata.age_rx_ring_map = NULL; 1017 1018 /* Rx return ring. */ 1019 if (sc->age_cdata.age_rr_ring_map != NULL) 1020 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rr_ring_map); 1021 if (sc->age_cdata.age_rr_ring_map != NULL && 1022 sc->age_rdata.age_rr_ring != NULL) 1023 bus_dmamem_free(sc->sc_dmat, 1024 &sc->age_rdata.age_rr_ring_seg, 1); 1025 sc->age_rdata.age_rr_ring = NULL; 1026 sc->age_cdata.age_rr_ring_map = NULL; 1027 1028 /* CMB block */ 1029 if (sc->age_cdata.age_cmb_block_map != NULL) 1030 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_cmb_block_map); 1031 if (sc->age_cdata.age_cmb_block_map != NULL && 1032 sc->age_rdata.age_cmb_block != NULL) 1033 bus_dmamem_free(sc->sc_dmat, 1034 &sc->age_rdata.age_cmb_block_seg, 1); 1035 sc->age_rdata.age_cmb_block = NULL; 1036 sc->age_cdata.age_cmb_block_map = NULL; 1037 1038 /* SMB block */ 1039 if (sc->age_cdata.age_smb_block_map != NULL) 1040 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_smb_block_map); 1041 if (sc->age_cdata.age_smb_block_map != NULL && 1042 sc->age_rdata.age_smb_block != NULL) 1043 bus_dmamem_free(sc->sc_dmat, 1044 &sc->age_rdata.age_smb_block_seg, 1); 1045 sc->age_rdata.age_smb_block = NULL; 1046 sc->age_cdata.age_smb_block_map = NULL; 1047 } 1048 1049 static void 1050 age_start(struct ifnet *ifp) 1051 { 1052 struct age_softc *sc = ifp->if_softc; 1053 struct mbuf *m_head; 1054 int enq; 1055 1056 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1057 return; 1058 1059 enq = 0; 1060 for (;;) { 1061 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1062 if (m_head == NULL) 1063 break; 1064 1065 /* 1066 * Pack the data into the transmit ring. If we 1067 * don't have room, set the OACTIVE flag and wait 1068 * for the NIC to drain the ring. 1069 */ 1070 if (age_encap(sc, &m_head)) { 1071 if (m_head == NULL) 1072 break; 1073 ifp->if_flags |= IFF_OACTIVE; 1074 break; 1075 } 1076 enq = 1; 1077 1078 #if NBPFILTER > 0 1079 /* 1080 * If there's a BPF listener, bounce a copy of this frame 1081 * to him. 1082 */ 1083 if (ifp->if_bpf != NULL) 1084 bpf_mtap(ifp->if_bpf, m_head); 1085 #endif 1086 } 1087 1088 if (enq) { 1089 /* Update mbox. */ 1090 AGE_COMMIT_MBOX(sc); 1091 /* Set a timeout in case the chip goes out to lunch. */ 1092 ifp->if_timer = AGE_TX_TIMEOUT; 1093 } 1094 } 1095 1096 static void 1097 age_watchdog(struct ifnet *ifp) 1098 { 1099 struct age_softc *sc = ifp->if_softc; 1100 1101 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1102 printf("%s: watchdog timeout (missed link)\n", 1103 device_xname(sc->sc_dev)); 1104 ifp->if_oerrors++; 1105 age_init(ifp); 1106 return; 1107 } 1108 1109 if (sc->age_cdata.age_tx_cnt == 0) { 1110 printf("%s: watchdog timeout (missed Tx interrupts) " 1111 "-- recovering\n", device_xname(sc->sc_dev)); 1112 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1113 age_start(ifp); 1114 return; 1115 } 1116 1117 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1118 ifp->if_oerrors++; 1119 age_init(ifp); 1120 1121 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1122 age_start(ifp); 1123 } 1124 1125 static int 1126 age_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1127 { 1128 struct age_softc *sc = ifp->if_softc; 1129 int s, error; 1130 1131 s = splnet(); 1132 1133 error = ether_ioctl(ifp, cmd, data); 1134 if (error == ENETRESET) { 1135 if (ifp->if_flags & IFF_RUNNING) 1136 age_rxfilter(sc); 1137 error = 0; 1138 } 1139 1140 splx(s); 1141 return error; 1142 } 1143 1144 static void 1145 age_mac_config(struct age_softc *sc) 1146 { 1147 struct mii_data *mii; 1148 uint32_t reg; 1149 1150 mii = &sc->sc_miibus; 1151 1152 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1153 reg &= ~MAC_CFG_FULL_DUPLEX; 1154 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1155 reg &= ~MAC_CFG_SPEED_MASK; 1156 1157 /* Reprogram MAC with resolved speed/duplex. */ 1158 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1159 case IFM_10_T: 1160 case IFM_100_TX: 1161 reg |= MAC_CFG_SPEED_10_100; 1162 break; 1163 case IFM_1000_T: 1164 reg |= MAC_CFG_SPEED_1000; 1165 break; 1166 } 1167 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1168 reg |= MAC_CFG_FULL_DUPLEX; 1169 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1170 reg |= MAC_CFG_TX_FC; 1171 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1172 reg |= MAC_CFG_RX_FC; 1173 } 1174 1175 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1176 } 1177 1178 static bool 1179 age_resume(device_t dv PMF_FN_ARGS) 1180 { 1181 struct age_softc *sc = device_private(dv); 1182 uint16_t cmd; 1183 1184 /* 1185 * Clear INTx emulation disable for hardware that 1186 * is set in resume event. From Linux. 1187 */ 1188 cmd = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 1189 if ((cmd & PCI_COMMAND_INTERRUPT_DISABLE) != 0) { 1190 cmd &= ~PCI_COMMAND_INTERRUPT_DISABLE; 1191 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 1192 PCI_COMMAND_STATUS_REG, cmd); 1193 } 1194 1195 return true; 1196 } 1197 1198 static int 1199 age_encap(struct age_softc *sc, struct mbuf **m_head) 1200 { 1201 struct age_txdesc *txd, *txd_last; 1202 struct tx_desc *desc; 1203 struct mbuf *m; 1204 bus_dmamap_t map; 1205 uint32_t cflags, poff, vtag; 1206 int error, i, nsegs, prod; 1207 #if NVLAN > 0 1208 struct m_tag *mtag; 1209 #endif 1210 1211 m = *m_head; 1212 cflags = vtag = 0; 1213 poff = 0; 1214 1215 prod = sc->age_cdata.age_tx_prod; 1216 txd = &sc->age_cdata.age_txdesc[prod]; 1217 txd_last = txd; 1218 map = txd->tx_dmamap; 1219 1220 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1221 1222 if (error == EFBIG) { 1223 error = 0; 1224 1225 MGETHDR(m, M_DONTWAIT, MT_DATA); 1226 if (m == NULL) { 1227 printf("%s: can't defrag TX mbuf\n", 1228 device_xname(sc->sc_dev)); 1229 m_freem(*m_head); 1230 *m_head = NULL; 1231 return ENOBUFS; 1232 } 1233 1234 M_COPY_PKTHDR(m, *m_head); 1235 if ((*m_head)->m_pkthdr.len > MHLEN) { 1236 MCLGET(m, M_DONTWAIT); 1237 if (!(m->m_flags & M_EXT)) { 1238 m_freem(*m_head); 1239 m_freem(m); 1240 *m_head = NULL; 1241 return ENOBUFS; 1242 } 1243 } 1244 m_copydata(*m_head, 0, (*m_head)->m_pkthdr.len, 1245 mtod(m, void *)); 1246 m_freem(*m_head); 1247 m->m_len = m->m_pkthdr.len; 1248 *m_head = m; 1249 1250 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1251 BUS_DMA_NOWAIT); 1252 1253 if (error != 0) { 1254 printf("%s: could not load defragged TX mbuf\n", 1255 device_xname(sc->sc_dev)); 1256 if (!error) { 1257 bus_dmamap_unload(sc->sc_dmat, map); 1258 error = EFBIG; 1259 } 1260 m_freem(*m_head); 1261 *m_head = NULL; 1262 return error; 1263 } 1264 } else if (error) { 1265 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 1266 return error; 1267 } 1268 1269 nsegs = map->dm_nsegs; 1270 1271 if (nsegs == 0) { 1272 m_freem(*m_head); 1273 *m_head = NULL; 1274 return EIO; 1275 } 1276 1277 /* Check descriptor overrun. */ 1278 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1279 bus_dmamap_unload(sc->sc_dmat, map); 1280 return ENOBUFS; 1281 } 1282 1283 m = *m_head; 1284 /* Configure Tx IP/TCP/UDP checksum offload. */ 1285 if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1286 cflags |= AGE_TD_CSUM; 1287 if ((m->m_pkthdr.csum_flags & M_CSUM_TCPv4) != 0) 1288 cflags |= AGE_TD_TCPCSUM; 1289 if ((m->m_pkthdr.csum_flags & M_CSUM_UDPv4) != 0) 1290 cflags |= AGE_TD_UDPCSUM; 1291 /* Set checksum start offset. */ 1292 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1293 } 1294 1295 #if NVLAN > 0 1296 /* Configure VLAN hardware tag insertion. */ 1297 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m))) { 1298 vtag = AGE_TX_VLAN_TAG(htons(VLAN_TAG_VALUE(mtag))); 1299 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1300 cflags |= AGE_TD_INSERT_VLAN_TAG; 1301 } 1302 #endif 1303 1304 desc = NULL; 1305 for (i = 0; i < nsegs; i++) { 1306 desc = &sc->age_rdata.age_tx_ring[prod]; 1307 desc->addr = htole64(map->dm_segs[i].ds_addr); 1308 desc->len = 1309 htole32(AGE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 1310 desc->flags = htole32(cflags); 1311 sc->age_cdata.age_tx_cnt++; 1312 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1313 } 1314 1315 /* Update producer index. */ 1316 sc->age_cdata.age_tx_prod = prod; 1317 1318 /* Set EOP on the last descriptor. */ 1319 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1320 desc = &sc->age_rdata.age_tx_ring[prod]; 1321 desc->flags |= htole32(AGE_TD_EOP); 1322 1323 /* Swap dmamap of the first and the last. */ 1324 txd = &sc->age_cdata.age_txdesc[prod]; 1325 map = txd_last->tx_dmamap; 1326 txd_last->tx_dmamap = txd->tx_dmamap; 1327 txd->tx_dmamap = map; 1328 txd->tx_m = m; 1329 1330 /* Sync descriptors. */ 1331 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1332 BUS_DMASYNC_PREWRITE); 1333 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1334 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1335 1336 return 0; 1337 } 1338 1339 static void 1340 age_txintr(struct age_softc *sc, int tpd_cons) 1341 { 1342 struct ifnet *ifp = &sc->sc_ec.ec_if; 1343 struct age_txdesc *txd; 1344 int cons, prog; 1345 1346 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1347 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1348 1349 /* 1350 * Go through our Tx list and free mbufs for those 1351 * frames which have been transmitted. 1352 */ 1353 cons = sc->age_cdata.age_tx_cons; 1354 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 1355 if (sc->age_cdata.age_tx_cnt <= 0) 1356 break; 1357 prog++; 1358 ifp->if_flags &= ~IFF_OACTIVE; 1359 sc->age_cdata.age_tx_cnt--; 1360 txd = &sc->age_cdata.age_txdesc[cons]; 1361 /* 1362 * Clear Tx descriptors, it's not required but would 1363 * help debugging in case of Tx issues. 1364 */ 1365 txd->tx_desc->addr = 0; 1366 txd->tx_desc->len = 0; 1367 txd->tx_desc->flags = 0; 1368 1369 if (txd->tx_m == NULL) 1370 continue; 1371 /* Reclaim transmitted mbufs. */ 1372 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1373 m_freem(txd->tx_m); 1374 txd->tx_m = NULL; 1375 } 1376 1377 if (prog > 0) { 1378 sc->age_cdata.age_tx_cons = cons; 1379 1380 /* 1381 * Unarm watchdog timer only when there are no pending 1382 * Tx descriptors in queue. 1383 */ 1384 if (sc->age_cdata.age_tx_cnt == 0) 1385 ifp->if_timer = 0; 1386 1387 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1388 sc->age_cdata.age_tx_ring_map->dm_mapsize, 1389 BUS_DMASYNC_PREWRITE); 1390 } 1391 } 1392 1393 /* Receive a frame. */ 1394 static void 1395 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 1396 { 1397 struct ifnet *ifp = &sc->sc_ec.ec_if; 1398 struct age_rxdesc *rxd; 1399 struct rx_desc *desc; 1400 struct mbuf *mp, *m; 1401 uint32_t status, index; 1402 int count, nsegs, pktlen; 1403 int rx_cons; 1404 1405 status = le32toh(rxrd->flags); 1406 index = le32toh(rxrd->index); 1407 rx_cons = AGE_RX_CONS(index); 1408 nsegs = AGE_RX_NSEGS(index); 1409 1410 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 1411 if ((status & AGE_RRD_ERROR) != 0 && 1412 (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 1413 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) { 1414 /* 1415 * We want to pass the following frames to upper 1416 * layer regardless of error status of Rx return 1417 * ring. 1418 * 1419 * o IP/TCP/UDP checksum is bad. 1420 * o frame length and protocol specific length 1421 * does not match. 1422 */ 1423 sc->age_cdata.age_rx_cons += nsegs; 1424 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1425 return; 1426 } 1427 1428 pktlen = 0; 1429 for (count = 0; count < nsegs; count++, 1430 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 1431 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 1432 mp = rxd->rx_m; 1433 desc = rxd->rx_desc; 1434 /* Add a new receive buffer to the ring. */ 1435 if (age_newbuf(sc, rxd, 0) != 0) { 1436 ifp->if_iqdrops++; 1437 /* Reuse Rx buffers. */ 1438 if (sc->age_cdata.age_rxhead != NULL) { 1439 m_freem(sc->age_cdata.age_rxhead); 1440 AGE_RXCHAIN_RESET(sc); 1441 } 1442 break; 1443 } 1444 1445 /* The length of the first mbuf is computed last. */ 1446 if (count != 0) { 1447 mp->m_len = AGE_RX_BYTES(le32toh(desc->len)); 1448 pktlen += mp->m_len; 1449 } 1450 1451 /* Chain received mbufs. */ 1452 if (sc->age_cdata.age_rxhead == NULL) { 1453 sc->age_cdata.age_rxhead = mp; 1454 sc->age_cdata.age_rxtail = mp; 1455 } else { 1456 mp->m_flags &= ~M_PKTHDR; 1457 sc->age_cdata.age_rxprev_tail = 1458 sc->age_cdata.age_rxtail; 1459 sc->age_cdata.age_rxtail->m_next = mp; 1460 sc->age_cdata.age_rxtail = mp; 1461 } 1462 1463 if (count == nsegs - 1) { 1464 /* 1465 * It seems that L1 controller has no way 1466 * to tell hardware to strip CRC bytes. 1467 */ 1468 sc->age_cdata.age_rxlen -= ETHER_CRC_LEN; 1469 if (nsegs > 1) { 1470 /* Remove the CRC bytes in chained mbufs. */ 1471 pktlen -= ETHER_CRC_LEN; 1472 if (mp->m_len <= ETHER_CRC_LEN) { 1473 sc->age_cdata.age_rxtail = 1474 sc->age_cdata.age_rxprev_tail; 1475 sc->age_cdata.age_rxtail->m_len -= 1476 (ETHER_CRC_LEN - mp->m_len); 1477 sc->age_cdata.age_rxtail->m_next = NULL; 1478 m_freem(mp); 1479 } else { 1480 mp->m_len -= ETHER_CRC_LEN; 1481 } 1482 } 1483 1484 m = sc->age_cdata.age_rxhead; 1485 m->m_flags |= M_PKTHDR; 1486 m->m_pkthdr.rcvif = ifp; 1487 m->m_pkthdr.len = sc->age_cdata.age_rxlen; 1488 /* Set the first mbuf length. */ 1489 m->m_len = sc->age_cdata.age_rxlen - pktlen; 1490 1491 /* 1492 * Set checksum information. 1493 * It seems that L1 controller can compute partial 1494 * checksum. The partial checksum value can be used 1495 * to accelerate checksum computation for fragmented 1496 * TCP/UDP packets. Upper network stack already 1497 * takes advantage of the partial checksum value in 1498 * IP reassembly stage. But I'm not sure the 1499 * correctness of the partial hardware checksum 1500 * assistance due to lack of data sheet. If it is 1501 * proven to work on L1 I'll enable it. 1502 */ 1503 if (status & AGE_RRD_IPV4) { 1504 if (status & AGE_RRD_IPCSUM_NOK) 1505 m->m_pkthdr.csum_flags |= 1506 M_CSUM_IPv4_BAD; 1507 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 1508 (status & AGE_RRD_TCP_UDPCSUM_NOK)) { 1509 m->m_pkthdr.csum_flags |= 1510 M_CSUM_TCP_UDP_BAD; 1511 } 1512 /* 1513 * Don't mark bad checksum for TCP/UDP frames 1514 * as fragmented frames may always have set 1515 * bad checksummed bit of descriptor status. 1516 */ 1517 } 1518 #if NVLAN > 0 1519 /* Check for VLAN tagged frames. */ 1520 if (status & AGE_RRD_VLAN) { 1521 uint32_t vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 1522 VLAN_INPUT_TAG(ifp, m, AGE_RX_VLAN_TAG(vtag), 1523 continue); 1524 } 1525 #endif 1526 1527 #if NBPFILTER > 0 1528 if (ifp->if_bpf) 1529 bpf_mtap(ifp->if_bpf, m); 1530 #endif 1531 /* Pass it on. */ 1532 ether_input(ifp, m); 1533 1534 /* Reset mbuf chains. */ 1535 AGE_RXCHAIN_RESET(sc); 1536 } 1537 } 1538 1539 if (count != nsegs) { 1540 sc->age_cdata.age_rx_cons += nsegs; 1541 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1542 } else 1543 sc->age_cdata.age_rx_cons = rx_cons; 1544 } 1545 1546 static void 1547 age_rxintr(struct age_softc *sc, int rr_prod) 1548 { 1549 struct rx_rdesc *rxrd; 1550 int rr_cons, nsegs, pktlen, prog; 1551 1552 rr_cons = sc->age_cdata.age_rr_cons; 1553 if (rr_cons == rr_prod) 1554 return; 1555 1556 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1557 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1558 BUS_DMASYNC_POSTREAD); 1559 1560 for (prog = 0; rr_cons != rr_prod; prog++) { 1561 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 1562 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 1563 if (nsegs == 0) 1564 break; 1565 /* 1566 * Check number of segments against received bytes 1567 * Non-matching value would indicate that hardware 1568 * is still trying to update Rx return descriptors. 1569 * I'm not sure whether this check is really needed. 1570 */ 1571 pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 1572 if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) / 1573 (MCLBYTES - ETHER_ALIGN))) 1574 break; 1575 1576 /* Received a frame. */ 1577 age_rxeof(sc, rxrd); 1578 1579 /* Clear return ring. */ 1580 rxrd->index = 0; 1581 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 1582 } 1583 1584 if (prog > 0) { 1585 /* Update the consumer index. */ 1586 sc->age_cdata.age_rr_cons = rr_cons; 1587 1588 /* Sync descriptors. */ 1589 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1590 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1591 BUS_DMASYNC_PREWRITE); 1592 1593 /* Notify hardware availability of new Rx buffers. */ 1594 AGE_COMMIT_MBOX(sc); 1595 } 1596 } 1597 1598 static void 1599 age_tick(void *xsc) 1600 { 1601 struct age_softc *sc = xsc; 1602 struct mii_data *mii = &sc->sc_miibus; 1603 int s; 1604 1605 s = splnet(); 1606 mii_tick(mii); 1607 splx(s); 1608 1609 callout_schedule(&sc->sc_tick_ch, hz); 1610 } 1611 1612 static void 1613 age_reset(struct age_softc *sc) 1614 { 1615 uint32_t reg; 1616 int i; 1617 1618 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 1619 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1620 DELAY(1); 1621 if ((CSR_READ_4(sc, AGE_MASTER_CFG) & MASTER_RESET) == 0) 1622 break; 1623 } 1624 if (i == 0) 1625 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 1626 1627 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1628 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1629 break; 1630 DELAY(10); 1631 } 1632 1633 if (i == 0) 1634 printf("%s: reset timeout(0x%08x)!\n", device_xname(sc->sc_dev), 1635 reg); 1636 1637 /* Initialize PCIe module. From Linux. */ 1638 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1639 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1640 } 1641 1642 static int 1643 age_init(struct ifnet *ifp) 1644 { 1645 struct age_softc *sc = ifp->if_softc; 1646 struct mii_data *mii; 1647 uint8_t eaddr[ETHER_ADDR_LEN]; 1648 bus_addr_t paddr; 1649 uint32_t reg, fsize; 1650 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 1651 int error; 1652 1653 /* 1654 * Cancel any pending I/O. 1655 */ 1656 age_stop(ifp, 0); 1657 1658 /* 1659 * Reset the chip to a known state. 1660 */ 1661 age_reset(sc); 1662 1663 /* Initialize descriptors. */ 1664 error = age_init_rx_ring(sc); 1665 if (error != 0) { 1666 printf("%s: no memory for Rx buffers.\n", device_xname(sc->sc_dev)); 1667 age_stop(ifp, 0); 1668 return error; 1669 } 1670 age_init_rr_ring(sc); 1671 age_init_tx_ring(sc); 1672 age_init_cmb_block(sc); 1673 age_init_smb_block(sc); 1674 1675 /* Reprogram the station address. */ 1676 memcpy(eaddr, CLLADDR(ifp->if_sadl), sizeof(eaddr)); 1677 CSR_WRITE_4(sc, AGE_PAR0, 1678 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1679 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 1680 1681 /* Set descriptor base addresses. */ 1682 paddr = sc->age_rdata.age_tx_ring_paddr; 1683 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 1684 paddr = sc->age_rdata.age_rx_ring_paddr; 1685 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 1686 paddr = sc->age_rdata.age_rr_ring_paddr; 1687 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 1688 paddr = sc->age_rdata.age_tx_ring_paddr; 1689 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 1690 paddr = sc->age_rdata.age_cmb_block_paddr; 1691 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1692 paddr = sc->age_rdata.age_smb_block_paddr; 1693 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1694 1695 /* Set Rx/Rx return descriptor counter. */ 1696 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 1697 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 1698 DESC_RRD_CNT_MASK) | 1699 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 1700 1701 /* Set Tx descriptor counter. */ 1702 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 1703 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 1704 1705 /* Tell hardware that we're ready to load descriptors. */ 1706 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 1707 1708 /* 1709 * Initialize mailbox register. 1710 * Updated producer/consumer index information is exchanged 1711 * through this mailbox register. However Tx producer and 1712 * Rx return consumer/Rx producer are all shared such that 1713 * it's hard to separate code path between Tx and Rx without 1714 * locking. If L1 hardware have a separate mail box register 1715 * for Tx and Rx consumer/producer management we could have 1716 * indepent Tx/Rx handler which in turn Rx handler could have 1717 * been run without any locking. 1718 */ 1719 AGE_COMMIT_MBOX(sc); 1720 1721 /* Configure IPG/IFG parameters. */ 1722 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 1723 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 1724 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1725 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1726 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 1727 1728 /* Set parameters for half-duplex media. */ 1729 CSR_WRITE_4(sc, AGE_HDPX_CFG, 1730 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1731 HDPX_CFG_LCOL_MASK) | 1732 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1733 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1734 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1735 HDPX_CFG_ABEBT_MASK) | 1736 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1737 HDPX_CFG_JAMIPG_MASK)); 1738 1739 /* Configure interrupt moderation timer. */ 1740 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 1741 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 1742 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 1743 reg &= ~MASTER_MTIMER_ENB; 1744 if (AGE_USECS(sc->age_int_mod) == 0) 1745 reg &= ~MASTER_ITIMER_ENB; 1746 else 1747 reg |= MASTER_ITIMER_ENB; 1748 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 1749 if (agedebug) 1750 printf("%s: interrupt moderation is %d us.\n", 1751 device_xname(sc->sc_dev), sc->age_int_mod); 1752 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 1753 1754 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 1755 if (ifp->if_mtu < ETHERMTU) 1756 sc->age_max_frame_size = ETHERMTU; 1757 else 1758 sc->age_max_frame_size = ifp->if_mtu; 1759 sc->age_max_frame_size += ETHER_HDR_LEN + 1760 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 1761 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 1762 1763 /* Configure jumbo frame. */ 1764 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 1765 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 1766 (((fsize / sizeof(uint64_t)) << 1767 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 1768 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 1769 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 1770 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 1771 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 1772 1773 /* Configure flow-control parameters. From Linux. */ 1774 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 1775 /* 1776 * Magic workaround for old-L1. 1777 * Don't know which hw revision requires this magic. 1778 */ 1779 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1780 /* 1781 * Another magic workaround for flow-control mode 1782 * change. From Linux. 1783 */ 1784 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1785 } 1786 /* 1787 * TODO 1788 * Should understand pause parameter relationships between FIFO 1789 * size and number of Rx descriptors and Rx return descriptors. 1790 * 1791 * Magic parameters came from Linux. 1792 */ 1793 switch (sc->age_chip_rev) { 1794 case 0x8001: 1795 case 0x9001: 1796 case 0x9002: 1797 case 0x9003: 1798 rxf_hi = AGE_RX_RING_CNT / 16; 1799 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 1800 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 1801 rrd_lo = AGE_RR_RING_CNT / 16; 1802 break; 1803 default: 1804 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 1805 rxf_lo = reg / 16; 1806 if (rxf_lo < 192) 1807 rxf_lo = 192; 1808 rxf_hi = (reg * 7) / 8; 1809 if (rxf_hi < rxf_lo) 1810 rxf_hi = rxf_lo + 16; 1811 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 1812 rrd_lo = reg / 8; 1813 rrd_hi = (reg * 7) / 8; 1814 if (rrd_lo < 2) 1815 rrd_lo = 2; 1816 if (rrd_hi < rrd_lo) 1817 rrd_hi = rrd_lo + 3; 1818 break; 1819 } 1820 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 1821 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 1822 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 1823 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 1824 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 1825 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 1826 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 1827 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 1828 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 1829 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 1830 1831 /* Configure RxQ. */ 1832 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1833 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 1834 RXQ_CFG_RD_BURST_MASK) | 1835 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 1836 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 1837 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 1838 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 1839 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1840 1841 /* Configure TxQ. */ 1842 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1843 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1844 TXQ_CFG_TPD_BURST_MASK) | 1845 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 1846 TXQ_CFG_TX_FIFO_BURST_MASK) | 1847 ((TXQ_CFG_TPD_FETCH_DEFAULT << 1848 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 1849 TXQ_CFG_ENB); 1850 1851 /* Configure DMA parameters. */ 1852 CSR_WRITE_4(sc, AGE_DMA_CFG, 1853 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 1854 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 1855 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 1856 1857 /* Configure CMB DMA write threshold. */ 1858 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 1859 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 1860 CMB_WR_THRESH_RRD_MASK) | 1861 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 1862 CMB_WR_THRESH_TPD_MASK)); 1863 1864 /* Set CMB/SMB timer and enable them. */ 1865 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 1866 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 1867 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 1868 1869 /* Request SMB updates for every seconds. */ 1870 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 1871 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 1872 1873 /* 1874 * Disable all WOL bits as WOL can interfere normal Rx 1875 * operation. 1876 */ 1877 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1878 1879 /* 1880 * Configure Tx/Rx MACs. 1881 * - Auto-padding for short frames. 1882 * - Enable CRC generation. 1883 * Start with full-duplex/1000Mbps media. Actual reconfiguration 1884 * of MAC is followed after link establishment. 1885 */ 1886 CSR_WRITE_4(sc, AGE_MAC_CFG, 1887 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 1888 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 1889 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1890 MAC_CFG_PREAMBLE_MASK)); 1891 1892 /* Set up the receive filter. */ 1893 age_rxfilter(sc); 1894 age_rxvlan(sc); 1895 1896 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1897 reg |= MAC_CFG_RXCSUM_ENB; 1898 1899 /* Ack all pending interrupts and clear it. */ 1900 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 1901 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 1902 1903 /* Finally enable Tx/Rx MAC. */ 1904 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 1905 1906 sc->age_flags &= ~AGE_FLAG_LINK; 1907 1908 /* Switch to the current media. */ 1909 mii = &sc->sc_miibus; 1910 mii_mediachg(mii); 1911 1912 callout_schedule(&sc->sc_tick_ch, hz); 1913 1914 ifp->if_flags |= IFF_RUNNING; 1915 ifp->if_flags &= ~IFF_OACTIVE; 1916 1917 return 0; 1918 } 1919 1920 static void 1921 age_stop(struct ifnet *ifp, int disable) 1922 { 1923 struct age_softc *sc = ifp->if_softc; 1924 struct age_txdesc *txd; 1925 struct age_rxdesc *rxd; 1926 uint32_t reg; 1927 int i; 1928 1929 callout_stop(&sc->sc_tick_ch); 1930 1931 /* 1932 * Mark the interface down and cancel the watchdog timer. 1933 */ 1934 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1935 ifp->if_timer = 0; 1936 1937 sc->age_flags &= ~AGE_FLAG_LINK; 1938 1939 mii_down(&sc->sc_miibus); 1940 1941 /* 1942 * Disable interrupts. 1943 */ 1944 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 1945 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 1946 1947 /* Stop CMB/SMB updates. */ 1948 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 1949 1950 /* Stop Rx/Tx MAC. */ 1951 age_stop_rxmac(sc); 1952 age_stop_txmac(sc); 1953 1954 /* Stop DMA. */ 1955 CSR_WRITE_4(sc, AGE_DMA_CFG, 1956 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 1957 1958 /* Stop TxQ/RxQ. */ 1959 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1960 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 1961 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1962 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 1963 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1964 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1965 break; 1966 DELAY(10); 1967 } 1968 if (i == 0) 1969 printf("%s: stopping Rx/Tx MACs timed out(0x%08x)!\n", 1970 device_xname(sc->sc_dev), reg); 1971 1972 /* Reclaim Rx buffers that have been processed. */ 1973 if (sc->age_cdata.age_rxhead != NULL) 1974 m_freem(sc->age_cdata.age_rxhead); 1975 AGE_RXCHAIN_RESET(sc); 1976 1977 /* 1978 * Free RX and TX mbufs still in the queues. 1979 */ 1980 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1981 rxd = &sc->age_cdata.age_rxdesc[i]; 1982 if (rxd->rx_m != NULL) { 1983 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1984 m_freem(rxd->rx_m); 1985 rxd->rx_m = NULL; 1986 } 1987 } 1988 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1989 txd = &sc->age_cdata.age_txdesc[i]; 1990 if (txd->tx_m != NULL) { 1991 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1992 m_freem(txd->tx_m); 1993 txd->tx_m = NULL; 1994 } 1995 } 1996 } 1997 1998 static void 1999 age_stats_update(struct age_softc *sc) 2000 { 2001 struct ifnet *ifp = &sc->sc_ec.ec_if; 2002 struct age_stats *stat; 2003 struct smb *smb; 2004 2005 stat = &sc->age_stat; 2006 2007 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2008 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2009 2010 smb = sc->age_rdata.age_smb_block; 2011 if (smb->updated == 0) 2012 return; 2013 2014 /* Rx stats. */ 2015 stat->rx_frames += smb->rx_frames; 2016 stat->rx_bcast_frames += smb->rx_bcast_frames; 2017 stat->rx_mcast_frames += smb->rx_mcast_frames; 2018 stat->rx_pause_frames += smb->rx_pause_frames; 2019 stat->rx_control_frames += smb->rx_control_frames; 2020 stat->rx_crcerrs += smb->rx_crcerrs; 2021 stat->rx_lenerrs += smb->rx_lenerrs; 2022 stat->rx_bytes += smb->rx_bytes; 2023 stat->rx_runts += smb->rx_runts; 2024 stat->rx_fragments += smb->rx_fragments; 2025 stat->rx_pkts_64 += smb->rx_pkts_64; 2026 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2027 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2028 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2029 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2030 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2031 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2032 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2033 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2034 stat->rx_desc_oflows += smb->rx_desc_oflows; 2035 stat->rx_alignerrs += smb->rx_alignerrs; 2036 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2037 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2038 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2039 2040 /* Tx stats. */ 2041 stat->tx_frames += smb->tx_frames; 2042 stat->tx_bcast_frames += smb->tx_bcast_frames; 2043 stat->tx_mcast_frames += smb->tx_mcast_frames; 2044 stat->tx_pause_frames += smb->tx_pause_frames; 2045 stat->tx_excess_defer += smb->tx_excess_defer; 2046 stat->tx_control_frames += smb->tx_control_frames; 2047 stat->tx_deferred += smb->tx_deferred; 2048 stat->tx_bytes += smb->tx_bytes; 2049 stat->tx_pkts_64 += smb->tx_pkts_64; 2050 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2051 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2052 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2053 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2054 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2055 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2056 stat->tx_single_colls += smb->tx_single_colls; 2057 stat->tx_multi_colls += smb->tx_multi_colls; 2058 stat->tx_late_colls += smb->tx_late_colls; 2059 stat->tx_excess_colls += smb->tx_excess_colls; 2060 stat->tx_underrun += smb->tx_underrun; 2061 stat->tx_desc_underrun += smb->tx_desc_underrun; 2062 stat->tx_lenerrs += smb->tx_lenerrs; 2063 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2064 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2065 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2066 2067 /* Update counters in ifnet. */ 2068 ifp->if_opackets += smb->tx_frames; 2069 2070 ifp->if_collisions += smb->tx_single_colls + 2071 smb->tx_multi_colls + smb->tx_late_colls + 2072 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 2073 2074 ifp->if_oerrors += smb->tx_excess_colls + 2075 smb->tx_late_colls + smb->tx_underrun + 2076 smb->tx_pkts_truncated; 2077 2078 ifp->if_ipackets += smb->rx_frames; 2079 2080 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2081 smb->rx_runts + smb->rx_pkts_truncated + 2082 smb->rx_fifo_oflows + smb->rx_desc_oflows + 2083 smb->rx_alignerrs; 2084 2085 /* Update done, clear. */ 2086 smb->updated = 0; 2087 2088 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2089 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2090 } 2091 2092 static void 2093 age_stop_txmac(struct age_softc *sc) 2094 { 2095 uint32_t reg; 2096 int i; 2097 2098 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2099 if ((reg & MAC_CFG_TX_ENB) != 0) { 2100 reg &= ~MAC_CFG_TX_ENB; 2101 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2102 } 2103 /* Stop Tx DMA engine. */ 2104 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2105 if ((reg & DMA_CFG_RD_ENB) != 0) { 2106 reg &= ~DMA_CFG_RD_ENB; 2107 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2108 } 2109 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2110 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2111 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2112 break; 2113 DELAY(10); 2114 } 2115 if (i == 0) 2116 printf("%s: stopping TxMAC timeout!\n", device_xname(sc->sc_dev)); 2117 } 2118 2119 static void 2120 age_stop_rxmac(struct age_softc *sc) 2121 { 2122 uint32_t reg; 2123 int i; 2124 2125 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2126 if ((reg & MAC_CFG_RX_ENB) != 0) { 2127 reg &= ~MAC_CFG_RX_ENB; 2128 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2129 } 2130 /* Stop Rx DMA engine. */ 2131 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2132 if ((reg & DMA_CFG_WR_ENB) != 0) { 2133 reg &= ~DMA_CFG_WR_ENB; 2134 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2135 } 2136 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2137 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2138 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2139 break; 2140 DELAY(10); 2141 } 2142 if (i == 0) 2143 printf("%s: stopping RxMAC timeout!\n", device_xname(sc->sc_dev)); 2144 } 2145 2146 static void 2147 age_init_tx_ring(struct age_softc *sc) 2148 { 2149 struct age_ring_data *rd; 2150 struct age_txdesc *txd; 2151 int i; 2152 2153 sc->age_cdata.age_tx_prod = 0; 2154 sc->age_cdata.age_tx_cons = 0; 2155 sc->age_cdata.age_tx_cnt = 0; 2156 2157 rd = &sc->age_rdata; 2158 memset(rd->age_tx_ring, 0, AGE_TX_RING_SZ); 2159 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2160 txd = &sc->age_cdata.age_txdesc[i]; 2161 txd->tx_desc = &rd->age_tx_ring[i]; 2162 txd->tx_m = NULL; 2163 } 2164 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 2165 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2166 } 2167 2168 static int 2169 age_init_rx_ring(struct age_softc *sc) 2170 { 2171 struct age_ring_data *rd; 2172 struct age_rxdesc *rxd; 2173 int i; 2174 2175 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 2176 rd = &sc->age_rdata; 2177 memset(rd->age_rx_ring, 0, AGE_RX_RING_SZ); 2178 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2179 rxd = &sc->age_cdata.age_rxdesc[i]; 2180 rxd->rx_m = NULL; 2181 rxd->rx_desc = &rd->age_rx_ring[i]; 2182 if (age_newbuf(sc, rxd, 1) != 0) 2183 return ENOBUFS; 2184 } 2185 2186 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 0, 2187 sc->age_cdata.age_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2188 2189 return 0; 2190 } 2191 2192 static void 2193 age_init_rr_ring(struct age_softc *sc) 2194 { 2195 struct age_ring_data *rd; 2196 2197 sc->age_cdata.age_rr_cons = 0; 2198 AGE_RXCHAIN_RESET(sc); 2199 2200 rd = &sc->age_rdata; 2201 memset(rd->age_rr_ring, 0, AGE_RR_RING_SZ); 2202 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 2203 sc->age_cdata.age_rr_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2204 } 2205 2206 static void 2207 age_init_cmb_block(struct age_softc *sc) 2208 { 2209 struct age_ring_data *rd; 2210 2211 rd = &sc->age_rdata; 2212 memset(rd->age_cmb_block, 0, AGE_CMB_BLOCK_SZ); 2213 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 2214 sc->age_cdata.age_cmb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2215 } 2216 2217 static void 2218 age_init_smb_block(struct age_softc *sc) 2219 { 2220 struct age_ring_data *rd; 2221 2222 rd = &sc->age_rdata; 2223 memset(rd->age_smb_block, 0, AGE_SMB_BLOCK_SZ); 2224 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2225 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2226 } 2227 2228 static int 2229 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd, int init) 2230 { 2231 struct rx_desc *desc; 2232 struct mbuf *m; 2233 bus_dmamap_t map; 2234 int error; 2235 2236 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 2237 if (m == NULL) 2238 return ENOBUFS; 2239 MCLGET(m, init ? M_WAITOK : M_DONTWAIT); 2240 if (!(m->m_flags & M_EXT)) { 2241 m_freem(m); 2242 return ENOBUFS; 2243 } 2244 2245 m->m_len = m->m_pkthdr.len = MCLBYTES; 2246 m_adj(m, ETHER_ALIGN); 2247 2248 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2249 sc->age_cdata.age_rx_sparemap, m, BUS_DMA_NOWAIT); 2250 2251 if (error != 0) { 2252 if (!error) { 2253 bus_dmamap_unload(sc->sc_dmat, 2254 sc->age_cdata.age_rx_sparemap); 2255 error = EFBIG; 2256 printf("%s: too many segments?!\n", 2257 device_xname(sc->sc_dev)); 2258 } 2259 m_freem(m); 2260 2261 if (init) 2262 printf("%s: can't load RX mbuf\n", device_xname(sc->sc_dev)); 2263 return error; 2264 } 2265 2266 if (rxd->rx_m != NULL) { 2267 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2268 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2269 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2270 } 2271 map = rxd->rx_dmamap; 2272 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 2273 sc->age_cdata.age_rx_sparemap = map; 2274 rxd->rx_m = m; 2275 2276 desc = rxd->rx_desc; 2277 desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 2278 desc->len = 2279 htole32((rxd->rx_dmamap->dm_segs[0].ds_len & AGE_RD_LEN_MASK) << 2280 AGE_RD_LEN_SHIFT); 2281 2282 return 0; 2283 } 2284 2285 static void 2286 age_rxvlan(struct age_softc *sc) 2287 { 2288 uint32_t reg; 2289 2290 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2291 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2292 if (sc->sc_ec.ec_capabilities & ETHERCAP_VLAN_HWTAGGING) 2293 reg |= MAC_CFG_VLAN_TAG_STRIP; 2294 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2295 } 2296 2297 static void 2298 age_rxfilter(struct age_softc *sc) 2299 { 2300 struct ethercom *ec = &sc->sc_ec; 2301 struct ifnet *ifp = &sc->sc_ec.ec_if; 2302 struct ether_multi *enm; 2303 struct ether_multistep step; 2304 uint32_t crc; 2305 uint32_t mchash[2]; 2306 uint32_t rxcfg; 2307 2308 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 2309 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2310 ifp->if_flags &= ~IFF_ALLMULTI; 2311 2312 /* 2313 * Always accept broadcast frames. 2314 */ 2315 rxcfg |= MAC_CFG_BCAST; 2316 2317 if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 2318 ifp->if_flags |= IFF_ALLMULTI; 2319 if (ifp->if_flags & IFF_PROMISC) 2320 rxcfg |= MAC_CFG_PROMISC; 2321 else 2322 rxcfg |= MAC_CFG_ALLMULTI; 2323 mchash[0] = mchash[1] = 0xFFFFFFFF; 2324 } else { 2325 /* Program new filter. */ 2326 memset(mchash, 0, sizeof(mchash)); 2327 2328 ETHER_FIRST_MULTI(step, ec, enm); 2329 while (enm != NULL) { 2330 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2331 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2332 ETHER_NEXT_MULTI(step, enm); 2333 } 2334 } 2335 2336 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 2337 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 2338 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 2339 } 2340
Indexes created Fri Oct 03 02:09:57 GMT 2025