if_age.c revision 1.38.2.2
1 /* $NetBSD: if_age.c,v 1.38.2.2 2010/04/21 00:27:40 matt Exp $ */ 2 /* $OpenBSD: if_age.c,v 1.1 2009/01/16 05:00:34 kevlo Exp $ */ 3 4 /*- 5 * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: if_age.c,v 1.38.2.2 2010/04/21 00:27:40 matt Exp $"); 35 36 #include "bpfilter.h" 37 #include "vlan.h" 38 39 #include <sys/param.h> 40 #include <sys/proc.h> 41 #include <sys/endian.h> 42 #include <sys/systm.h> 43 #include <sys/types.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/queue.h> 47 #include <sys/kernel.h> 48 #include <sys/device.h> 49 #include <sys/callout.h> 50 #include <sys/socket.h> 51 52 #include <net/if.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #ifdef INET 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/in_var.h> 61 #include <netinet/ip.h> 62 #endif 63 64 #include <net/if_types.h> 65 #include <net/if_vlanvar.h> 66 67 #if NBPFILTER > 0 68 #include <net/bpf.h> 69 #endif 70 71 #include <sys/rnd.h> 72 73 #include <dev/mii/mii.h> 74 #include <dev/mii/miivar.h> 75 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/pcidevs.h> 79 80 #include <dev/pci/if_agereg.h> 81 82 static int age_match(device_t, cfdata_t, void *); 83 static void age_attach(device_t, device_t, void *); 84 static int age_detach(device_t, int); 85 86 static bool age_resume(device_t PMF_FN_PROTO); 87 88 static int age_miibus_readreg(device_t, int, int); 89 static void age_miibus_writereg(device_t, int, int, int); 90 static void age_miibus_statchg(device_t); 91 92 static int age_init(struct ifnet *); 93 static int age_ioctl(struct ifnet *, u_long, void *); 94 static void age_start(struct ifnet *); 95 static void age_watchdog(struct ifnet *); 96 static void age_mediastatus(struct ifnet *, struct ifmediareq *); 97 static int age_mediachange(struct ifnet *); 98 99 static int age_intr(void *); 100 static int age_dma_alloc(struct age_softc *); 101 static void age_dma_free(struct age_softc *); 102 static void age_get_macaddr(struct age_softc *, uint8_t[]); 103 static void age_phy_reset(struct age_softc *); 104 105 static int age_encap(struct age_softc *, struct mbuf **); 106 static void age_init_tx_ring(struct age_softc *); 107 static int age_init_rx_ring(struct age_softc *); 108 static void age_init_rr_ring(struct age_softc *); 109 static void age_init_cmb_block(struct age_softc *); 110 static void age_init_smb_block(struct age_softc *); 111 static int age_newbuf(struct age_softc *, struct age_rxdesc *, int); 112 static void age_mac_config(struct age_softc *); 113 static void age_txintr(struct age_softc *, int); 114 static void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 115 static void age_rxintr(struct age_softc *, int); 116 static void age_tick(void *); 117 static void age_reset(struct age_softc *); 118 static void age_stop(struct ifnet *, int); 119 static void age_stats_update(struct age_softc *); 120 static void age_stop_txmac(struct age_softc *); 121 static void age_stop_rxmac(struct age_softc *); 122 static void age_rxvlan(struct age_softc *sc); 123 static void age_rxfilter(struct age_softc *); 124 125 CFATTACH_DECL_NEW(age, sizeof(struct age_softc), 126 age_match, age_attach, age_detach, NULL); 127 128 int agedebug = 0; 129 #define DPRINTF(x) do { if (agedebug) printf x; } while (0) 130 131 #define ETHER_ALIGN 2 132 #define AGE_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 133 134 static int 135 age_match(device_t dev, cfdata_t match, void *aux) 136 { 137 struct pci_attach_args *pa = aux; 138 139 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && 140 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_GIGA); 141 } 142 143 static void 144 age_attach(device_t parent, device_t self, void *aux) 145 { 146 struct age_softc *sc = device_private(self); 147 struct pci_attach_args *pa = aux; 148 pci_intr_handle_t ih; 149 const char *intrstr; 150 struct ifnet *ifp = &sc->sc_ec.ec_if; 151 pcireg_t memtype; 152 int error = 0; 153 154 aprint_naive("\n"); 155 aprint_normal(": Attansic/Atheros L1 Gigabit Ethernet\n"); 156 157 sc->sc_dev = self; 158 sc->sc_dmat = pa->pa_dmat; 159 sc->sc_pct = pa->pa_pc; 160 sc->sc_pcitag = pa->pa_tag; 161 162 /* 163 * Allocate IO memory 164 */ 165 memtype = pci_mapreg_type(sc->sc_pct, sc->sc_pcitag, AGE_PCIR_BAR); 166 switch (memtype) { 167 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 168 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 169 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 170 break; 171 default: 172 aprint_error_dev(self, "invalid base address register\n"); 173 break; 174 } 175 176 if (pci_mapreg_map(pa, AGE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 177 &sc->sc_mem_bh, NULL, &sc->sc_mem_size) != 0) { 178 aprint_error_dev(self, "could not map mem space\n"); 179 return; 180 } 181 182 if (pci_intr_map(pa, &ih) != 0) { 183 aprint_error_dev(self, "could not map interrupt\n"); 184 goto fail; 185 } 186 187 /* 188 * Allocate IRQ 189 */ 190 intrstr = pci_intr_string(sc->sc_pct, ih); 191 sc->sc_irq_handle = pci_intr_establish(sc->sc_pct, ih, IPL_NET, 192 age_intr, sc); 193 if (sc->sc_irq_handle == NULL) { 194 aprint_error_dev(self, "could not establish interrupt"); 195 if (intrstr != NULL) 196 aprint_error(" at %s", intrstr); 197 aprint_error("\n"); 198 goto fail; 199 } 200 aprint_normal_dev(self, "%s\n", intrstr); 201 202 /* Set PHY address. */ 203 sc->age_phyaddr = AGE_PHY_ADDR; 204 205 /* Reset PHY. */ 206 age_phy_reset(sc); 207 208 /* Reset the ethernet controller. */ 209 age_reset(sc); 210 211 /* Get PCI and chip id/revision. */ 212 sc->age_rev = PCI_REVISION(pa->pa_class); 213 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 214 MASTER_CHIP_REV_SHIFT; 215 216 aprint_debug_dev(self, "PCI device revision : 0x%04x\n", sc->age_rev); 217 aprint_debug_dev(self, "Chip id/revision : 0x%04x\n", sc->age_chip_rev); 218 219 if (agedebug) { 220 aprint_debug_dev(self, "%d Tx FIFO, %d Rx FIFO\n", 221 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 222 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 223 } 224 225 /* Set max allowable DMA size. */ 226 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 227 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 228 229 /* Allocate DMA stuffs */ 230 error = age_dma_alloc(sc); 231 if (error) 232 goto fail; 233 234 callout_init(&sc->sc_tick_ch, 0); 235 callout_setfunc(&sc->sc_tick_ch, age_tick, sc); 236 237 /* Load station address. */ 238 age_get_macaddr(sc, sc->sc_enaddr); 239 240 aprint_normal_dev(self, "Ethernet address %s\n", 241 ether_sprintf(sc->sc_enaddr)); 242 243 ifp->if_softc = sc; 244 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 245 ifp->if_init = age_init; 246 ifp->if_ioctl = age_ioctl; 247 ifp->if_start = age_start; 248 ifp->if_stop = age_stop; 249 ifp->if_watchdog = age_watchdog; 250 ifp->if_baudrate = IF_Gbps(1); 251 IFQ_SET_MAXLEN(&ifp->if_snd, AGE_TX_RING_CNT - 1); 252 IFQ_SET_READY(&ifp->if_snd); 253 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 254 255 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 256 257 #ifdef AGE_CHECKSUM 258 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 259 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 260 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 261 #endif 262 263 #if NVLAN > 0 264 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 265 #endif 266 267 /* Set up MII bus. */ 268 sc->sc_miibus.mii_ifp = ifp; 269 sc->sc_miibus.mii_readreg = age_miibus_readreg; 270 sc->sc_miibus.mii_writereg = age_miibus_writereg; 271 sc->sc_miibus.mii_statchg = age_miibus_statchg; 272 273 sc->sc_ec.ec_mii = &sc->sc_miibus; 274 ifmedia_init(&sc->sc_miibus.mii_media, 0, age_mediachange, 275 age_mediastatus); 276 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 277 MII_OFFSET_ANY, MIIF_DOPAUSE); 278 279 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 280 aprint_error_dev(self, "no PHY found!\n"); 281 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 282 0, NULL); 283 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 284 } else 285 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 286 287 if_attach(ifp); 288 ether_ifattach(ifp, sc->sc_enaddr); 289 290 if (!pmf_device_register(self, NULL, age_resume)) 291 aprint_error_dev(self, "couldn't establish power handler\n"); 292 else 293 pmf_class_network_register(self, ifp); 294 295 return; 296 297 fail: 298 age_dma_free(sc); 299 if (sc->sc_irq_handle != NULL) { 300 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 301 sc->sc_irq_handle = NULL; 302 } 303 if (sc->sc_mem_size) { 304 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 305 sc->sc_mem_size = 0; 306 } 307 } 308 309 static int 310 age_detach(device_t self, int flags) 311 { 312 struct age_softc *sc = device_private(self); 313 struct ifnet *ifp = &sc->sc_ec.ec_if; 314 int s; 315 316 pmf_device_deregister(self); 317 s = splnet(); 318 age_stop(ifp, 0); 319 splx(s); 320 321 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 322 323 /* Delete all remaining media. */ 324 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 325 326 ether_ifdetach(ifp); 327 if_detach(ifp); 328 age_dma_free(sc); 329 330 if (sc->sc_irq_handle != NULL) { 331 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 332 sc->sc_irq_handle = NULL; 333 } 334 if (sc->sc_mem_size) { 335 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 336 sc->sc_mem_size = 0; 337 } 338 return 0; 339 } 340 341 /* 342 * Read a PHY register on the MII of the L1. 343 */ 344 static int 345 age_miibus_readreg(device_t dev, int phy, int reg) 346 { 347 struct age_softc *sc = device_private(dev); 348 uint32_t v; 349 int i; 350 351 if (phy != sc->age_phyaddr) 352 return 0; 353 354 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 355 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 356 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 357 DELAY(1); 358 v = CSR_READ_4(sc, AGE_MDIO); 359 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 360 break; 361 } 362 363 if (i == 0) { 364 printf("%s: phy read timeout: phy %d, reg %d\n", 365 device_xname(sc->sc_dev), phy, reg); 366 return 0; 367 } 368 369 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 370 } 371 372 /* 373 * Write a PHY register on the MII of the L1. 374 */ 375 static void 376 age_miibus_writereg(device_t dev, int phy, int reg, int val) 377 { 378 struct age_softc *sc = device_private(dev); 379 uint32_t v; 380 int i; 381 382 if (phy != sc->age_phyaddr) 383 return; 384 385 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 386 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 387 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 388 389 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 390 DELAY(1); 391 v = CSR_READ_4(sc, AGE_MDIO); 392 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 393 break; 394 } 395 396 if (i == 0) { 397 printf("%s: phy write timeout: phy %d, reg %d\n", 398 device_xname(sc->sc_dev), phy, reg); 399 } 400 } 401 402 /* 403 * Callback from MII layer when media changes. 404 */ 405 static void 406 age_miibus_statchg(device_t dev) 407 { 408 struct age_softc *sc = device_private(dev); 409 struct ifnet *ifp = &sc->sc_ec.ec_if; 410 struct mii_data *mii; 411 412 if ((ifp->if_flags & IFF_RUNNING) == 0) 413 return; 414 415 mii = &sc->sc_miibus; 416 417 sc->age_flags &= ~AGE_FLAG_LINK; 418 if ((mii->mii_media_status & IFM_AVALID) != 0) { 419 switch (IFM_SUBTYPE(mii->mii_media_active)) { 420 case IFM_10_T: 421 case IFM_100_TX: 422 case IFM_1000_T: 423 sc->age_flags |= AGE_FLAG_LINK; 424 break; 425 default: 426 break; 427 } 428 } 429 430 /* Stop Rx/Tx MACs. */ 431 age_stop_rxmac(sc); 432 age_stop_txmac(sc); 433 434 /* Program MACs with resolved speed/duplex/flow-control. */ 435 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 436 uint32_t reg; 437 438 age_mac_config(sc); 439 reg = CSR_READ_4(sc, AGE_MAC_CFG); 440 /* Restart DMA engine and Tx/Rx MAC. */ 441 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 442 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 443 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 444 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 445 } 446 } 447 448 /* 449 * Get the current interface media status. 450 */ 451 static void 452 age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 453 { 454 struct age_softc *sc = ifp->if_softc; 455 struct mii_data *mii = &sc->sc_miibus; 456 457 mii_pollstat(mii); 458 ifmr->ifm_status = mii->mii_media_status; 459 ifmr->ifm_active = mii->mii_media_active; 460 } 461 462 /* 463 * Set hardware to newly-selected media. 464 */ 465 static int 466 age_mediachange(struct ifnet *ifp) 467 { 468 struct age_softc *sc = ifp->if_softc; 469 struct mii_data *mii = &sc->sc_miibus; 470 int error; 471 472 if (mii->mii_instance != 0) { 473 struct mii_softc *miisc; 474 475 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 476 mii_phy_reset(miisc); 477 } 478 error = mii_mediachg(mii); 479 480 return error; 481 } 482 483 static int 484 age_intr(void *arg) 485 { 486 struct age_softc *sc = arg; 487 struct ifnet *ifp = &sc->sc_ec.ec_if; 488 struct cmb *cmb; 489 uint32_t status; 490 491 status = CSR_READ_4(sc, AGE_INTR_STATUS); 492 if (status == 0 || (status & AGE_INTRS) == 0) 493 return 0; 494 495 cmb = sc->age_rdata.age_cmb_block; 496 if (cmb == NULL) { 497 /* Happens when bringing up the interface 498 * w/o having a carrier. Ack. the interrupt. 499 */ 500 CSR_WRITE_4(sc, AGE_INTR_STATUS, status); 501 return 0; 502 } 503 504 /* Disable interrupts. */ 505 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 506 507 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 508 sc->age_cdata.age_cmb_block_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 509 status = le32toh(cmb->intr_status); 510 if ((status & AGE_INTRS) == 0) 511 goto back; 512 513 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 514 TPD_CONS_SHIFT; 515 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 516 RRD_PROD_SHIFT; 517 518 /* Let hardware know CMB was served. */ 519 cmb->intr_status = 0; 520 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 521 sc->age_cdata.age_cmb_block_map->dm_mapsize, 522 BUS_DMASYNC_PREWRITE); 523 524 if (ifp->if_flags & IFF_RUNNING) { 525 if (status & INTR_CMB_RX) 526 age_rxintr(sc, sc->age_rr_prod); 527 528 if (status & INTR_CMB_TX) 529 age_txintr(sc, sc->age_tpd_cons); 530 531 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 532 if (status & INTR_DMA_RD_TO_RST) 533 printf("%s: DMA read error! -- resetting\n", 534 device_xname(sc->sc_dev)); 535 if (status & INTR_DMA_WR_TO_RST) 536 printf("%s: DMA write error! -- resetting\n", 537 device_xname(sc->sc_dev)); 538 age_init(ifp); 539 } 540 541 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 542 age_start(ifp); 543 544 if (status & INTR_SMB) 545 age_stats_update(sc); 546 } 547 548 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 549 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 550 sc->age_cdata.age_cmb_block_map->dm_mapsize, 551 BUS_DMASYNC_POSTREAD); 552 553 back: 554 /* Re-enable interrupts. */ 555 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 556 557 return 1; 558 } 559 560 static void 561 age_get_macaddr(struct age_softc *sc, uint8_t eaddr[]) 562 { 563 uint32_t ea[2], reg; 564 int i, vpdc; 565 566 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 567 if ((reg & SPI_VPD_ENB) != 0) { 568 /* Get VPD stored in TWSI EEPROM. */ 569 reg &= ~SPI_VPD_ENB; 570 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 571 } 572 573 if (pci_get_capability(sc->sc_pct, sc->sc_pcitag, 574 PCI_CAP_VPD, &vpdc, NULL)) { 575 /* 576 * PCI VPD capability found, let TWSI reload EEPROM. 577 * This will set Ethernet address of controller. 578 */ 579 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | 580 TWSI_CTRL_SW_LD_START); 581 for (i = 100; i > 0; i++) { 582 DELAY(1000); 583 reg = CSR_READ_4(sc, AGE_TWSI_CTRL); 584 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 585 break; 586 } 587 if (i == 0) 588 printf("%s: reloading EEPROM timeout!\n", 589 device_xname(sc->sc_dev)); 590 } else { 591 if (agedebug) 592 printf("%s: PCI VPD capability not found!\n", 593 device_xname(sc->sc_dev)); 594 } 595 596 ea[0] = CSR_READ_4(sc, AGE_PAR0); 597 ea[1] = CSR_READ_4(sc, AGE_PAR1); 598 599 eaddr[0] = (ea[1] >> 8) & 0xFF; 600 eaddr[1] = (ea[1] >> 0) & 0xFF; 601 eaddr[2] = (ea[0] >> 24) & 0xFF; 602 eaddr[3] = (ea[0] >> 16) & 0xFF; 603 eaddr[4] = (ea[0] >> 8) & 0xFF; 604 eaddr[5] = (ea[0] >> 0) & 0xFF; 605 } 606 607 static void 608 age_phy_reset(struct age_softc *sc) 609 { 610 uint16_t reg, pn; 611 int i, linkup; 612 613 /* Reset PHY. */ 614 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 615 DELAY(2000); 616 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 617 DELAY(2000); 618 619 #define ATPHY_DBG_ADDR 0x1D 620 #define ATPHY_DBG_DATA 0x1E 621 #define ATPHY_CDTC 0x16 622 #define PHY_CDTC_ENB 0x0001 623 #define PHY_CDTC_POFF 8 624 #define ATPHY_CDTS 0x1C 625 #define PHY_CDTS_STAT_OK 0x0000 626 #define PHY_CDTS_STAT_SHORT 0x0100 627 #define PHY_CDTS_STAT_OPEN 0x0200 628 #define PHY_CDTS_STAT_INVAL 0x0300 629 #define PHY_CDTS_STAT_MASK 0x0300 630 631 /* Check power saving mode. Magic from Linux. */ 632 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET); 633 for (linkup = 0, pn = 0; pn < 4; pn++) { 634 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, ATPHY_CDTC, 635 (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB); 636 for (i = 200; i > 0; i--) { 637 DELAY(1000); 638 reg = age_miibus_readreg(sc->sc_dev, sc->age_phyaddr, 639 ATPHY_CDTC); 640 if ((reg & PHY_CDTC_ENB) == 0) 641 break; 642 } 643 DELAY(1000); 644 reg = age_miibus_readreg(sc->sc_dev, sc->age_phyaddr, 645 ATPHY_CDTS); 646 if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) { 647 linkup++; 648 break; 649 } 650 } 651 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, MII_BMCR, 652 BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 653 if (linkup == 0) { 654 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, 655 ATPHY_DBG_ADDR, 0); 656 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, 657 ATPHY_DBG_DATA, 0x124E); 658 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, 659 ATPHY_DBG_ADDR, 1); 660 reg = age_miibus_readreg(sc->sc_dev, sc->age_phyaddr, 661 ATPHY_DBG_DATA); 662 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, 663 ATPHY_DBG_DATA, reg | 0x03); 664 /* XXX */ 665 DELAY(1500 * 1000); 666 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, 667 ATPHY_DBG_ADDR, 0); 668 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, 669 ATPHY_DBG_DATA, 0x024E); 670 } 671 672 #undef ATPHY_DBG_ADDR 673 #undef ATPHY_DBG_DATA 674 #undef ATPHY_CDTC 675 #undef PHY_CDTC_ENB 676 #undef PHY_CDTC_POFF 677 #undef ATPHY_CDTS 678 #undef PHY_CDTS_STAT_OK 679 #undef PHY_CDTS_STAT_SHORT 680 #undef PHY_CDTS_STAT_OPEN 681 #undef PHY_CDTS_STAT_INVAL 682 #undef PHY_CDTS_STAT_MASK 683 } 684 685 static int 686 age_dma_alloc(struct age_softc *sc) 687 { 688 struct age_txdesc *txd; 689 struct age_rxdesc *rxd; 690 int nsegs, error, i; 691 692 /* 693 * Create DMA stuffs for TX ring 694 */ 695 error = bus_dmamap_create(sc->sc_dmat, AGE_TX_RING_SZ, 1, 696 AGE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_tx_ring_map); 697 if (error) { 698 sc->age_cdata.age_tx_ring_map = NULL; 699 return ENOBUFS; 700 } 701 702 /* Allocate DMA'able memory for TX ring */ 703 error = bus_dmamem_alloc(sc->sc_dmat, AGE_TX_RING_SZ, 704 ETHER_ALIGN, 0, &sc->age_rdata.age_tx_ring_seg, 1, 705 &nsegs, BUS_DMA_WAITOK); 706 if (error) { 707 printf("%s: could not allocate DMA'able memory for Tx ring, " 708 "error = %i\n", device_xname(sc->sc_dev), error); 709 return error; 710 } 711 712 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_tx_ring_seg, 713 nsegs, AGE_TX_RING_SZ, (void **)&sc->age_rdata.age_tx_ring, 714 BUS_DMA_NOWAIT); 715 if (error) 716 return ENOBUFS; 717 718 memset(sc->age_rdata.age_tx_ring, 0, AGE_TX_RING_SZ); 719 720 /* Load the DMA map for Tx ring. */ 721 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 722 sc->age_rdata.age_tx_ring, AGE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 723 if (error) { 724 printf("%s: could not load DMA'able memory for Tx ring, " 725 "error = %i\n", device_xname(sc->sc_dev), error); 726 bus_dmamem_free(sc->sc_dmat, 727 &sc->age_rdata.age_tx_ring_seg, 1); 728 return error; 729 } 730 731 sc->age_rdata.age_tx_ring_paddr = 732 sc->age_cdata.age_tx_ring_map->dm_segs[0].ds_addr; 733 734 /* 735 * Create DMA stuffs for RX ring 736 */ 737 error = bus_dmamap_create(sc->sc_dmat, AGE_RX_RING_SZ, 1, 738 AGE_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_ring_map); 739 if (error) { 740 sc->age_cdata.age_rx_ring_map = NULL; 741 return ENOBUFS; 742 } 743 744 /* Allocate DMA'able memory for RX ring */ 745 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RX_RING_SZ, 746 ETHER_ALIGN, 0, &sc->age_rdata.age_rx_ring_seg, 1, 747 &nsegs, BUS_DMA_WAITOK); 748 if (error) { 749 printf("%s: could not allocate DMA'able memory for Rx ring, " 750 "error = %i.\n", device_xname(sc->sc_dev), error); 751 return error; 752 } 753 754 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rx_ring_seg, 755 nsegs, AGE_RX_RING_SZ, (void **)&sc->age_rdata.age_rx_ring, 756 BUS_DMA_NOWAIT); 757 if (error) 758 return ENOBUFS; 759 760 memset(sc->age_rdata.age_rx_ring, 0, AGE_RX_RING_SZ); 761 762 /* Load the DMA map for Rx ring. */ 763 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 764 sc->age_rdata.age_rx_ring, AGE_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 765 if (error) { 766 printf("%s: could not load DMA'able memory for Rx ring, " 767 "error = %i.\n", device_xname(sc->sc_dev), error); 768 bus_dmamem_free(sc->sc_dmat, 769 &sc->age_rdata.age_rx_ring_seg, 1); 770 return error; 771 } 772 773 sc->age_rdata.age_rx_ring_paddr = 774 sc->age_cdata.age_rx_ring_map->dm_segs[0].ds_addr; 775 776 /* 777 * Create DMA stuffs for RX return ring 778 */ 779 error = bus_dmamap_create(sc->sc_dmat, AGE_RR_RING_SZ, 1, 780 AGE_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rr_ring_map); 781 if (error) { 782 sc->age_cdata.age_rr_ring_map = NULL; 783 return ENOBUFS; 784 } 785 786 /* Allocate DMA'able memory for RX return ring */ 787 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RR_RING_SZ, 788 ETHER_ALIGN, 0, &sc->age_rdata.age_rr_ring_seg, 1, 789 &nsegs, BUS_DMA_WAITOK); 790 if (error) { 791 printf("%s: could not allocate DMA'able memory for Rx " 792 "return ring, error = %i.\n", 793 device_xname(sc->sc_dev), error); 794 return error; 795 } 796 797 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rr_ring_seg, 798 nsegs, AGE_RR_RING_SZ, (void **)&sc->age_rdata.age_rr_ring, 799 BUS_DMA_NOWAIT); 800 if (error) 801 return ENOBUFS; 802 803 memset(sc->age_rdata.age_rr_ring, 0, AGE_RR_RING_SZ); 804 805 /* Load the DMA map for Rx return ring. */ 806 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 807 sc->age_rdata.age_rr_ring, AGE_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 808 if (error) { 809 printf("%s: could not load DMA'able memory for Rx return ring, " 810 "error = %i\n", device_xname(sc->sc_dev), error); 811 bus_dmamem_free(sc->sc_dmat, 812 &sc->age_rdata.age_rr_ring_seg, 1); 813 return error; 814 } 815 816 sc->age_rdata.age_rr_ring_paddr = 817 sc->age_cdata.age_rr_ring_map->dm_segs[0].ds_addr; 818 819 /* 820 * Create DMA stuffs for CMB block 821 */ 822 error = bus_dmamap_create(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 1, 823 AGE_CMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 824 &sc->age_cdata.age_cmb_block_map); 825 if (error) { 826 sc->age_cdata.age_cmb_block_map = NULL; 827 return ENOBUFS; 828 } 829 830 /* Allocate DMA'able memory for CMB block */ 831 error = bus_dmamem_alloc(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 832 ETHER_ALIGN, 0, &sc->age_rdata.age_cmb_block_seg, 1, 833 &nsegs, BUS_DMA_WAITOK); 834 if (error) { 835 printf("%s: could not allocate DMA'able memory for " 836 "CMB block, error = %i\n", device_xname(sc->sc_dev), error); 837 return error; 838 } 839 840 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_cmb_block_seg, 841 nsegs, AGE_CMB_BLOCK_SZ, (void **)&sc->age_rdata.age_cmb_block, 842 BUS_DMA_NOWAIT); 843 if (error) 844 return ENOBUFS; 845 846 memset(sc->age_rdata.age_cmb_block, 0, AGE_CMB_BLOCK_SZ); 847 848 /* Load the DMA map for CMB block. */ 849 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 850 sc->age_rdata.age_cmb_block, AGE_CMB_BLOCK_SZ, NULL, 851 BUS_DMA_WAITOK); 852 if (error) { 853 printf("%s: could not load DMA'able memory for CMB block, " 854 "error = %i\n", device_xname(sc->sc_dev), error); 855 bus_dmamem_free(sc->sc_dmat, 856 &sc->age_rdata.age_cmb_block_seg, 1); 857 return error; 858 } 859 860 sc->age_rdata.age_cmb_block_paddr = 861 sc->age_cdata.age_cmb_block_map->dm_segs[0].ds_addr; 862 863 /* 864 * Create DMA stuffs for SMB block 865 */ 866 error = bus_dmamap_create(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 1, 867 AGE_SMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 868 &sc->age_cdata.age_smb_block_map); 869 if (error) { 870 sc->age_cdata.age_smb_block_map = NULL; 871 return ENOBUFS; 872 } 873 874 /* Allocate DMA'able memory for SMB block */ 875 error = bus_dmamem_alloc(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 876 ETHER_ALIGN, 0, &sc->age_rdata.age_smb_block_seg, 1, 877 &nsegs, BUS_DMA_WAITOK); 878 if (error) { 879 printf("%s: could not allocate DMA'able memory for " 880 "SMB block, error = %i\n", device_xname(sc->sc_dev), error); 881 return error; 882 } 883 884 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_smb_block_seg, 885 nsegs, AGE_SMB_BLOCK_SZ, (void **)&sc->age_rdata.age_smb_block, 886 BUS_DMA_NOWAIT); 887 if (error) 888 return ENOBUFS; 889 890 memset(sc->age_rdata.age_smb_block, 0, AGE_SMB_BLOCK_SZ); 891 892 /* Load the DMA map for SMB block */ 893 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 894 sc->age_rdata.age_smb_block, AGE_SMB_BLOCK_SZ, NULL, 895 BUS_DMA_WAITOK); 896 if (error) { 897 printf("%s: could not load DMA'able memory for SMB block, " 898 "error = %i\n", device_xname(sc->sc_dev), error); 899 bus_dmamem_free(sc->sc_dmat, 900 &sc->age_rdata.age_smb_block_seg, 1); 901 return error; 902 } 903 904 sc->age_rdata.age_smb_block_paddr = 905 sc->age_cdata.age_smb_block_map->dm_segs[0].ds_addr; 906 907 /* Create DMA maps for Tx buffers. */ 908 for (i = 0; i < AGE_TX_RING_CNT; i++) { 909 txd = &sc->age_cdata.age_txdesc[i]; 910 txd->tx_m = NULL; 911 txd->tx_dmamap = NULL; 912 error = bus_dmamap_create(sc->sc_dmat, AGE_TSO_MAXSIZE, 913 AGE_MAXTXSEGS, AGE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 914 &txd->tx_dmamap); 915 if (error) { 916 txd->tx_dmamap = NULL; 917 printf("%s: could not create Tx dmamap, error = %i.\n", 918 device_xname(sc->sc_dev), error); 919 return error; 920 } 921 } 922 923 /* Create DMA maps for Rx buffers. */ 924 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 925 BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_sparemap); 926 if (error) { 927 sc->age_cdata.age_rx_sparemap = NULL; 928 printf("%s: could not create spare Rx dmamap, error = %i.\n", 929 device_xname(sc->sc_dev), error); 930 return error; 931 } 932 for (i = 0; i < AGE_RX_RING_CNT; i++) { 933 rxd = &sc->age_cdata.age_rxdesc[i]; 934 rxd->rx_m = NULL; 935 rxd->rx_dmamap = NULL; 936 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 937 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 938 if (error) { 939 rxd->rx_dmamap = NULL; 940 printf("%s: could not create Rx dmamap, error = %i.\n", 941 device_xname(sc->sc_dev), error); 942 return error; 943 } 944 } 945 946 return 0; 947 } 948 949 static void 950 age_dma_free(struct age_softc *sc) 951 { 952 struct age_txdesc *txd; 953 struct age_rxdesc *rxd; 954 int i; 955 956 /* Tx buffers */ 957 for (i = 0; i < AGE_TX_RING_CNT; i++) { 958 txd = &sc->age_cdata.age_txdesc[i]; 959 if (txd->tx_dmamap != NULL) { 960 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 961 txd->tx_dmamap = NULL; 962 } 963 } 964 /* Rx buffers */ 965 for (i = 0; i < AGE_RX_RING_CNT; i++) { 966 rxd = &sc->age_cdata.age_rxdesc[i]; 967 if (rxd->rx_dmamap != NULL) { 968 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 969 rxd->rx_dmamap = NULL; 970 } 971 } 972 if (sc->age_cdata.age_rx_sparemap != NULL) { 973 bus_dmamap_destroy(sc->sc_dmat, sc->age_cdata.age_rx_sparemap); 974 sc->age_cdata.age_rx_sparemap = NULL; 975 } 976 977 /* Tx ring. */ 978 if (sc->age_cdata.age_tx_ring_map != NULL) 979 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_tx_ring_map); 980 if (sc->age_cdata.age_tx_ring_map != NULL && 981 sc->age_rdata.age_tx_ring != NULL) 982 bus_dmamem_free(sc->sc_dmat, 983 &sc->age_rdata.age_tx_ring_seg, 1); 984 sc->age_rdata.age_tx_ring = NULL; 985 sc->age_cdata.age_tx_ring_map = NULL; 986 987 /* Rx ring. */ 988 if (sc->age_cdata.age_rx_ring_map != NULL) 989 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rx_ring_map); 990 if (sc->age_cdata.age_rx_ring_map != NULL && 991 sc->age_rdata.age_rx_ring != NULL) 992 bus_dmamem_free(sc->sc_dmat, 993 &sc->age_rdata.age_rx_ring_seg, 1); 994 sc->age_rdata.age_rx_ring = NULL; 995 sc->age_cdata.age_rx_ring_map = NULL; 996 997 /* Rx return ring. */ 998 if (sc->age_cdata.age_rr_ring_map != NULL) 999 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rr_ring_map); 1000 if (sc->age_cdata.age_rr_ring_map != NULL && 1001 sc->age_rdata.age_rr_ring != NULL) 1002 bus_dmamem_free(sc->sc_dmat, 1003 &sc->age_rdata.age_rr_ring_seg, 1); 1004 sc->age_rdata.age_rr_ring = NULL; 1005 sc->age_cdata.age_rr_ring_map = NULL; 1006 1007 /* CMB block */ 1008 if (sc->age_cdata.age_cmb_block_map != NULL) 1009 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_cmb_block_map); 1010 if (sc->age_cdata.age_cmb_block_map != NULL && 1011 sc->age_rdata.age_cmb_block != NULL) 1012 bus_dmamem_free(sc->sc_dmat, 1013 &sc->age_rdata.age_cmb_block_seg, 1); 1014 sc->age_rdata.age_cmb_block = NULL; 1015 sc->age_cdata.age_cmb_block_map = NULL; 1016 1017 /* SMB block */ 1018 if (sc->age_cdata.age_smb_block_map != NULL) 1019 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_smb_block_map); 1020 if (sc->age_cdata.age_smb_block_map != NULL && 1021 sc->age_rdata.age_smb_block != NULL) 1022 bus_dmamem_free(sc->sc_dmat, 1023 &sc->age_rdata.age_smb_block_seg, 1); 1024 sc->age_rdata.age_smb_block = NULL; 1025 sc->age_cdata.age_smb_block_map = NULL; 1026 } 1027 1028 static void 1029 age_start(struct ifnet *ifp) 1030 { 1031 struct age_softc *sc = ifp->if_softc; 1032 struct mbuf *m_head; 1033 int enq; 1034 1035 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1036 return; 1037 1038 enq = 0; 1039 for (;;) { 1040 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1041 if (m_head == NULL) 1042 break; 1043 1044 /* 1045 * Pack the data into the transmit ring. If we 1046 * don't have room, set the OACTIVE flag and wait 1047 * for the NIC to drain the ring. 1048 */ 1049 if (age_encap(sc, &m_head)) { 1050 if (m_head == NULL) 1051 break; 1052 IF_PREPEND(&ifp->if_snd, m_head); 1053 ifp->if_flags |= IFF_OACTIVE; 1054 break; 1055 } 1056 enq = 1; 1057 1058 #if NBPFILTER > 0 1059 /* 1060 * If there's a BPF listener, bounce a copy of this frame 1061 * to him. 1062 */ 1063 if (ifp->if_bpf != NULL) 1064 bpf_mtap(ifp->if_bpf, m_head); 1065 #endif 1066 } 1067 1068 if (enq) { 1069 /* Update mbox. */ 1070 AGE_COMMIT_MBOX(sc); 1071 /* Set a timeout in case the chip goes out to lunch. */ 1072 ifp->if_timer = AGE_TX_TIMEOUT; 1073 } 1074 } 1075 1076 static void 1077 age_watchdog(struct ifnet *ifp) 1078 { 1079 struct age_softc *sc = ifp->if_softc; 1080 1081 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1082 printf("%s: watchdog timeout (missed link)\n", 1083 device_xname(sc->sc_dev)); 1084 ifp->if_oerrors++; 1085 age_init(ifp); 1086 return; 1087 } 1088 1089 if (sc->age_cdata.age_tx_cnt == 0) { 1090 printf("%s: watchdog timeout (missed Tx interrupts) " 1091 "-- recovering\n", device_xname(sc->sc_dev)); 1092 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1093 age_start(ifp); 1094 return; 1095 } 1096 1097 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1098 ifp->if_oerrors++; 1099 age_init(ifp); 1100 1101 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1102 age_start(ifp); 1103 } 1104 1105 static int 1106 age_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1107 { 1108 struct age_softc *sc = ifp->if_softc; 1109 int s, error; 1110 1111 s = splnet(); 1112 1113 error = ether_ioctl(ifp, cmd, data); 1114 if (error == ENETRESET) { 1115 if (ifp->if_flags & IFF_RUNNING) 1116 age_rxfilter(sc); 1117 error = 0; 1118 } 1119 1120 splx(s); 1121 return error; 1122 } 1123 1124 static void 1125 age_mac_config(struct age_softc *sc) 1126 { 1127 struct mii_data *mii; 1128 uint32_t reg; 1129 1130 mii = &sc->sc_miibus; 1131 1132 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1133 reg &= ~MAC_CFG_FULL_DUPLEX; 1134 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1135 reg &= ~MAC_CFG_SPEED_MASK; 1136 1137 /* Reprogram MAC with resolved speed/duplex. */ 1138 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1139 case IFM_10_T: 1140 case IFM_100_TX: 1141 reg |= MAC_CFG_SPEED_10_100; 1142 break; 1143 case IFM_1000_T: 1144 reg |= MAC_CFG_SPEED_1000; 1145 break; 1146 } 1147 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1148 reg |= MAC_CFG_FULL_DUPLEX; 1149 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1150 reg |= MAC_CFG_TX_FC; 1151 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1152 reg |= MAC_CFG_RX_FC; 1153 } 1154 1155 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1156 } 1157 1158 static bool 1159 age_resume(device_t dv PMF_FN_ARGS) 1160 { 1161 struct age_softc *sc = device_private(dv); 1162 uint16_t cmd; 1163 1164 /* 1165 * Clear INTx emulation disable for hardware that 1166 * is set in resume event. From Linux. 1167 */ 1168 cmd = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 1169 if ((cmd & PCI_COMMAND_INTERRUPT_DISABLE) != 0) { 1170 cmd &= ~PCI_COMMAND_INTERRUPT_DISABLE; 1171 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 1172 PCI_COMMAND_STATUS_REG, cmd); 1173 } 1174 1175 return true; 1176 } 1177 1178 static int 1179 age_encap(struct age_softc *sc, struct mbuf **m_head) 1180 { 1181 struct age_txdesc *txd, *txd_last; 1182 struct tx_desc *desc; 1183 struct mbuf *m; 1184 bus_dmamap_t map; 1185 uint32_t cflags, poff, vtag; 1186 int error, i, nsegs, prod; 1187 #if NVLAN > 0 1188 struct m_tag *mtag; 1189 #endif 1190 1191 m = *m_head; 1192 cflags = vtag = 0; 1193 poff = 0; 1194 1195 prod = sc->age_cdata.age_tx_prod; 1196 txd = &sc->age_cdata.age_txdesc[prod]; 1197 txd_last = txd; 1198 map = txd->tx_dmamap; 1199 1200 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1201 1202 if (error == EFBIG) { 1203 error = 0; 1204 1205 *m_head = m_pullup(*m_head, MHLEN); 1206 if (*m_head == NULL) { 1207 printf("%s: can't defrag TX mbuf\n", 1208 device_xname(sc->sc_dev)); 1209 return ENOBUFS; 1210 } 1211 1212 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1213 BUS_DMA_NOWAIT); 1214 1215 if (error != 0) { 1216 printf("%s: could not load defragged TX mbuf\n", 1217 device_xname(sc->sc_dev)); 1218 m_freem(*m_head); 1219 *m_head = NULL; 1220 return error; 1221 } 1222 } else if (error) { 1223 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 1224 return error; 1225 } 1226 1227 nsegs = map->dm_nsegs; 1228 1229 if (nsegs == 0) { 1230 m_freem(*m_head); 1231 *m_head = NULL; 1232 return EIO; 1233 } 1234 1235 /* Check descriptor overrun. */ 1236 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1237 bus_dmamap_unload(sc->sc_dmat, map); 1238 return ENOBUFS; 1239 } 1240 1241 m = *m_head; 1242 /* Configure Tx IP/TCP/UDP checksum offload. */ 1243 if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1244 cflags |= AGE_TD_CSUM; 1245 if ((m->m_pkthdr.csum_flags & M_CSUM_TCPv4) != 0) 1246 cflags |= AGE_TD_TCPCSUM; 1247 if ((m->m_pkthdr.csum_flags & M_CSUM_UDPv4) != 0) 1248 cflags |= AGE_TD_UDPCSUM; 1249 /* Set checksum start offset. */ 1250 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1251 } 1252 1253 #if NVLAN > 0 1254 /* Configure VLAN hardware tag insertion. */ 1255 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m))) { 1256 vtag = AGE_TX_VLAN_TAG(htons(VLAN_TAG_VALUE(mtag))); 1257 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1258 cflags |= AGE_TD_INSERT_VLAN_TAG; 1259 } 1260 #endif 1261 1262 desc = NULL; 1263 for (i = 0; i < nsegs; i++) { 1264 desc = &sc->age_rdata.age_tx_ring[prod]; 1265 desc->addr = htole64(map->dm_segs[i].ds_addr); 1266 desc->len = 1267 htole32(AGE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 1268 desc->flags = htole32(cflags); 1269 sc->age_cdata.age_tx_cnt++; 1270 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1271 } 1272 1273 /* Update producer index. */ 1274 sc->age_cdata.age_tx_prod = prod; 1275 1276 /* Set EOP on the last descriptor. */ 1277 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1278 desc = &sc->age_rdata.age_tx_ring[prod]; 1279 desc->flags |= htole32(AGE_TD_EOP); 1280 1281 /* Swap dmamap of the first and the last. */ 1282 txd = &sc->age_cdata.age_txdesc[prod]; 1283 map = txd_last->tx_dmamap; 1284 txd_last->tx_dmamap = txd->tx_dmamap; 1285 txd->tx_dmamap = map; 1286 txd->tx_m = m; 1287 1288 /* Sync descriptors. */ 1289 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1290 BUS_DMASYNC_PREWRITE); 1291 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1292 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1293 1294 return 0; 1295 } 1296 1297 static void 1298 age_txintr(struct age_softc *sc, int tpd_cons) 1299 { 1300 struct ifnet *ifp = &sc->sc_ec.ec_if; 1301 struct age_txdesc *txd; 1302 int cons, prog; 1303 1304 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1305 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1306 1307 /* 1308 * Go through our Tx list and free mbufs for those 1309 * frames which have been transmitted. 1310 */ 1311 cons = sc->age_cdata.age_tx_cons; 1312 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 1313 if (sc->age_cdata.age_tx_cnt <= 0) 1314 break; 1315 prog++; 1316 ifp->if_flags &= ~IFF_OACTIVE; 1317 sc->age_cdata.age_tx_cnt--; 1318 txd = &sc->age_cdata.age_txdesc[cons]; 1319 /* 1320 * Clear Tx descriptors, it's not required but would 1321 * help debugging in case of Tx issues. 1322 */ 1323 txd->tx_desc->addr = 0; 1324 txd->tx_desc->len = 0; 1325 txd->tx_desc->flags = 0; 1326 1327 if (txd->tx_m == NULL) 1328 continue; 1329 /* Reclaim transmitted mbufs. */ 1330 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1331 m_freem(txd->tx_m); 1332 txd->tx_m = NULL; 1333 } 1334 1335 if (prog > 0) { 1336 sc->age_cdata.age_tx_cons = cons; 1337 1338 /* 1339 * Unarm watchdog timer only when there are no pending 1340 * Tx descriptors in queue. 1341 */ 1342 if (sc->age_cdata.age_tx_cnt == 0) 1343 ifp->if_timer = 0; 1344 1345 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1346 sc->age_cdata.age_tx_ring_map->dm_mapsize, 1347 BUS_DMASYNC_PREWRITE); 1348 } 1349 } 1350 1351 /* Receive a frame. */ 1352 static void 1353 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 1354 { 1355 struct ifnet *ifp = &sc->sc_ec.ec_if; 1356 struct age_rxdesc *rxd; 1357 struct rx_desc *desc; 1358 struct mbuf *mp, *m; 1359 uint32_t status, index; 1360 int count, nsegs, pktlen; 1361 int rx_cons; 1362 1363 status = le32toh(rxrd->flags); 1364 index = le32toh(rxrd->index); 1365 rx_cons = AGE_RX_CONS(index); 1366 nsegs = AGE_RX_NSEGS(index); 1367 1368 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 1369 if ((status & AGE_RRD_ERROR) != 0 && 1370 (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 1371 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) { 1372 /* 1373 * We want to pass the following frames to upper 1374 * layer regardless of error status of Rx return 1375 * ring. 1376 * 1377 * o IP/TCP/UDP checksum is bad. 1378 * o frame length and protocol specific length 1379 * does not match. 1380 */ 1381 sc->age_cdata.age_rx_cons += nsegs; 1382 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1383 return; 1384 } 1385 1386 pktlen = 0; 1387 for (count = 0; count < nsegs; count++, 1388 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 1389 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 1390 mp = rxd->rx_m; 1391 desc = rxd->rx_desc; 1392 /* Add a new receive buffer to the ring. */ 1393 if (age_newbuf(sc, rxd, 0) != 0) { 1394 ifp->if_iqdrops++; 1395 /* Reuse Rx buffers. */ 1396 if (sc->age_cdata.age_rxhead != NULL) { 1397 m_freem(sc->age_cdata.age_rxhead); 1398 AGE_RXCHAIN_RESET(sc); 1399 } 1400 break; 1401 } 1402 1403 /* The length of the first mbuf is computed last. */ 1404 if (count != 0) { 1405 mp->m_len = AGE_RX_BYTES(le32toh(desc->len)); 1406 pktlen += mp->m_len; 1407 } 1408 1409 /* Chain received mbufs. */ 1410 if (sc->age_cdata.age_rxhead == NULL) { 1411 sc->age_cdata.age_rxhead = mp; 1412 sc->age_cdata.age_rxtail = mp; 1413 } else { 1414 mp->m_flags &= ~M_PKTHDR; 1415 sc->age_cdata.age_rxprev_tail = 1416 sc->age_cdata.age_rxtail; 1417 sc->age_cdata.age_rxtail->m_next = mp; 1418 sc->age_cdata.age_rxtail = mp; 1419 } 1420 1421 if (count == nsegs - 1) { 1422 /* 1423 * It seems that L1 controller has no way 1424 * to tell hardware to strip CRC bytes. 1425 */ 1426 sc->age_cdata.age_rxlen -= ETHER_CRC_LEN; 1427 if (nsegs > 1) { 1428 /* Remove the CRC bytes in chained mbufs. */ 1429 pktlen -= ETHER_CRC_LEN; 1430 if (mp->m_len <= ETHER_CRC_LEN) { 1431 sc->age_cdata.age_rxtail = 1432 sc->age_cdata.age_rxprev_tail; 1433 sc->age_cdata.age_rxtail->m_len -= 1434 (ETHER_CRC_LEN - mp->m_len); 1435 sc->age_cdata.age_rxtail->m_next = NULL; 1436 m_freem(mp); 1437 } else { 1438 mp->m_len -= ETHER_CRC_LEN; 1439 } 1440 } 1441 1442 m = sc->age_cdata.age_rxhead; 1443 m->m_flags |= M_PKTHDR; 1444 m->m_pkthdr.rcvif = ifp; 1445 m->m_pkthdr.len = sc->age_cdata.age_rxlen; 1446 /* Set the first mbuf length. */ 1447 m->m_len = sc->age_cdata.age_rxlen - pktlen; 1448 1449 /* 1450 * Set checksum information. 1451 * It seems that L1 controller can compute partial 1452 * checksum. The partial checksum value can be used 1453 * to accelerate checksum computation for fragmented 1454 * TCP/UDP packets. Upper network stack already 1455 * takes advantage of the partial checksum value in 1456 * IP reassembly stage. But I'm not sure the 1457 * correctness of the partial hardware checksum 1458 * assistance due to lack of data sheet. If it is 1459 * proven to work on L1 I'll enable it. 1460 */ 1461 if (status & AGE_RRD_IPV4) { 1462 if (status & AGE_RRD_IPCSUM_NOK) 1463 m->m_pkthdr.csum_flags |= 1464 M_CSUM_IPv4_BAD; 1465 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 1466 (status & AGE_RRD_TCP_UDPCSUM_NOK)) { 1467 m->m_pkthdr.csum_flags |= 1468 M_CSUM_TCP_UDP_BAD; 1469 } 1470 /* 1471 * Don't mark bad checksum for TCP/UDP frames 1472 * as fragmented frames may always have set 1473 * bad checksummed bit of descriptor status. 1474 */ 1475 } 1476 #if NVLAN > 0 1477 /* Check for VLAN tagged frames. */ 1478 if (status & AGE_RRD_VLAN) { 1479 uint32_t vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 1480 VLAN_INPUT_TAG(ifp, m, AGE_RX_VLAN_TAG(vtag), 1481 continue); 1482 } 1483 #endif 1484 1485 #if NBPFILTER > 0 1486 if (ifp->if_bpf) 1487 bpf_mtap(ifp->if_bpf, m); 1488 #endif 1489 /* Pass it on. */ 1490 ether_input(ifp, m); 1491 1492 /* Reset mbuf chains. */ 1493 AGE_RXCHAIN_RESET(sc); 1494 } 1495 } 1496 1497 if (count != nsegs) { 1498 sc->age_cdata.age_rx_cons += nsegs; 1499 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1500 } else 1501 sc->age_cdata.age_rx_cons = rx_cons; 1502 } 1503 1504 static void 1505 age_rxintr(struct age_softc *sc, int rr_prod) 1506 { 1507 struct rx_rdesc *rxrd; 1508 int rr_cons, nsegs, pktlen, prog; 1509 1510 rr_cons = sc->age_cdata.age_rr_cons; 1511 if (rr_cons == rr_prod) 1512 return; 1513 1514 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1515 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1516 BUS_DMASYNC_POSTREAD); 1517 1518 for (prog = 0; rr_cons != rr_prod; prog++) { 1519 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 1520 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 1521 if (nsegs == 0) 1522 break; 1523 /* 1524 * Check number of segments against received bytes 1525 * Non-matching value would indicate that hardware 1526 * is still trying to update Rx return descriptors. 1527 * I'm not sure whether this check is really needed. 1528 */ 1529 pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 1530 if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) / 1531 (MCLBYTES - ETHER_ALIGN))) 1532 break; 1533 1534 /* Received a frame. */ 1535 age_rxeof(sc, rxrd); 1536 1537 /* Clear return ring. */ 1538 rxrd->index = 0; 1539 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 1540 } 1541 1542 if (prog > 0) { 1543 /* Update the consumer index. */ 1544 sc->age_cdata.age_rr_cons = rr_cons; 1545 1546 /* Sync descriptors. */ 1547 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1548 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1549 BUS_DMASYNC_PREWRITE); 1550 1551 /* Notify hardware availability of new Rx buffers. */ 1552 AGE_COMMIT_MBOX(sc); 1553 } 1554 } 1555 1556 static void 1557 age_tick(void *xsc) 1558 { 1559 struct age_softc *sc = xsc; 1560 struct mii_data *mii = &sc->sc_miibus; 1561 int s; 1562 1563 s = splnet(); 1564 mii_tick(mii); 1565 splx(s); 1566 1567 callout_schedule(&sc->sc_tick_ch, hz); 1568 } 1569 1570 static void 1571 age_reset(struct age_softc *sc) 1572 { 1573 uint32_t reg; 1574 int i; 1575 1576 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 1577 CSR_READ_4(sc, AGE_MASTER_CFG); 1578 DELAY(1000); 1579 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1580 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1581 break; 1582 DELAY(10); 1583 } 1584 1585 if (i == 0) 1586 printf("%s: reset timeout(0x%08x)!\n", device_xname(sc->sc_dev), 1587 reg); 1588 1589 /* Initialize PCIe module. From Linux. */ 1590 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1591 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1592 } 1593 1594 static int 1595 age_init(struct ifnet *ifp) 1596 { 1597 struct age_softc *sc = ifp->if_softc; 1598 struct mii_data *mii; 1599 uint8_t eaddr[ETHER_ADDR_LEN]; 1600 bus_addr_t paddr; 1601 uint32_t reg, fsize; 1602 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 1603 int error; 1604 1605 /* 1606 * Cancel any pending I/O. 1607 */ 1608 age_stop(ifp, 0); 1609 1610 /* 1611 * Reset the chip to a known state. 1612 */ 1613 age_reset(sc); 1614 1615 /* Initialize descriptors. */ 1616 error = age_init_rx_ring(sc); 1617 if (error != 0) { 1618 printf("%s: no memory for Rx buffers.\n", device_xname(sc->sc_dev)); 1619 age_stop(ifp, 0); 1620 return error; 1621 } 1622 age_init_rr_ring(sc); 1623 age_init_tx_ring(sc); 1624 age_init_cmb_block(sc); 1625 age_init_smb_block(sc); 1626 1627 /* Reprogram the station address. */ 1628 memcpy(eaddr, CLLADDR(ifp->if_sadl), sizeof(eaddr)); 1629 CSR_WRITE_4(sc, AGE_PAR0, 1630 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1631 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 1632 1633 /* Set descriptor base addresses. */ 1634 paddr = sc->age_rdata.age_tx_ring_paddr; 1635 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 1636 paddr = sc->age_rdata.age_rx_ring_paddr; 1637 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 1638 paddr = sc->age_rdata.age_rr_ring_paddr; 1639 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 1640 paddr = sc->age_rdata.age_tx_ring_paddr; 1641 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 1642 paddr = sc->age_rdata.age_cmb_block_paddr; 1643 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1644 paddr = sc->age_rdata.age_smb_block_paddr; 1645 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1646 1647 /* Set Rx/Rx return descriptor counter. */ 1648 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 1649 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 1650 DESC_RRD_CNT_MASK) | 1651 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 1652 1653 /* Set Tx descriptor counter. */ 1654 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 1655 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 1656 1657 /* Tell hardware that we're ready to load descriptors. */ 1658 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 1659 1660 /* 1661 * Initialize mailbox register. 1662 * Updated producer/consumer index information is exchanged 1663 * through this mailbox register. However Tx producer and 1664 * Rx return consumer/Rx producer are all shared such that 1665 * it's hard to separate code path between Tx and Rx without 1666 * locking. If L1 hardware have a separate mail box register 1667 * for Tx and Rx consumer/producer management we could have 1668 * indepent Tx/Rx handler which in turn Rx handler could have 1669 * been run without any locking. 1670 */ 1671 AGE_COMMIT_MBOX(sc); 1672 1673 /* Configure IPG/IFG parameters. */ 1674 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 1675 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 1676 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1677 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1678 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 1679 1680 /* Set parameters for half-duplex media. */ 1681 CSR_WRITE_4(sc, AGE_HDPX_CFG, 1682 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1683 HDPX_CFG_LCOL_MASK) | 1684 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1685 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1686 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1687 HDPX_CFG_ABEBT_MASK) | 1688 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1689 HDPX_CFG_JAMIPG_MASK)); 1690 1691 /* Configure interrupt moderation timer. */ 1692 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 1693 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 1694 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 1695 reg &= ~MASTER_MTIMER_ENB; 1696 if (AGE_USECS(sc->age_int_mod) == 0) 1697 reg &= ~MASTER_ITIMER_ENB; 1698 else 1699 reg |= MASTER_ITIMER_ENB; 1700 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 1701 if (agedebug) 1702 printf("%s: interrupt moderation is %d us.\n", 1703 device_xname(sc->sc_dev), sc->age_int_mod); 1704 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 1705 1706 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 1707 if (ifp->if_mtu < ETHERMTU) 1708 sc->age_max_frame_size = ETHERMTU; 1709 else 1710 sc->age_max_frame_size = ifp->if_mtu; 1711 sc->age_max_frame_size += ETHER_HDR_LEN + 1712 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 1713 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 1714 1715 /* Configure jumbo frame. */ 1716 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 1717 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 1718 (((fsize / sizeof(uint64_t)) << 1719 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 1720 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 1721 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 1722 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 1723 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 1724 1725 /* Configure flow-control parameters. From Linux. */ 1726 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 1727 /* 1728 * Magic workaround for old-L1. 1729 * Don't know which hw revision requires this magic. 1730 */ 1731 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1732 /* 1733 * Another magic workaround for flow-control mode 1734 * change. From Linux. 1735 */ 1736 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1737 } 1738 /* 1739 * TODO 1740 * Should understand pause parameter relationships between FIFO 1741 * size and number of Rx descriptors and Rx return descriptors. 1742 * 1743 * Magic parameters came from Linux. 1744 */ 1745 switch (sc->age_chip_rev) { 1746 case 0x8001: 1747 case 0x9001: 1748 case 0x9002: 1749 case 0x9003: 1750 rxf_hi = AGE_RX_RING_CNT / 16; 1751 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 1752 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 1753 rrd_lo = AGE_RR_RING_CNT / 16; 1754 break; 1755 default: 1756 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 1757 rxf_lo = reg / 16; 1758 if (rxf_lo < 192) 1759 rxf_lo = 192; 1760 rxf_hi = (reg * 7) / 8; 1761 if (rxf_hi < rxf_lo) 1762 rxf_hi = rxf_lo + 16; 1763 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 1764 rrd_lo = reg / 8; 1765 rrd_hi = (reg * 7) / 8; 1766 if (rrd_lo < 2) 1767 rrd_lo = 2; 1768 if (rrd_hi < rrd_lo) 1769 rrd_hi = rrd_lo + 3; 1770 break; 1771 } 1772 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 1773 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 1774 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 1775 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 1776 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 1777 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 1778 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 1779 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 1780 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 1781 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 1782 1783 /* Configure RxQ. */ 1784 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1785 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 1786 RXQ_CFG_RD_BURST_MASK) | 1787 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 1788 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 1789 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 1790 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 1791 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1792 1793 /* Configure TxQ. */ 1794 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1795 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1796 TXQ_CFG_TPD_BURST_MASK) | 1797 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 1798 TXQ_CFG_TX_FIFO_BURST_MASK) | 1799 ((TXQ_CFG_TPD_FETCH_DEFAULT << 1800 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 1801 TXQ_CFG_ENB); 1802 1803 /* Configure DMA parameters. */ 1804 CSR_WRITE_4(sc, AGE_DMA_CFG, 1805 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 1806 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 1807 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 1808 1809 /* Configure CMB DMA write threshold. */ 1810 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 1811 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 1812 CMB_WR_THRESH_RRD_MASK) | 1813 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 1814 CMB_WR_THRESH_TPD_MASK)); 1815 1816 /* Set CMB/SMB timer and enable them. */ 1817 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 1818 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 1819 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 1820 1821 /* Request SMB updates for every seconds. */ 1822 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 1823 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 1824 1825 /* 1826 * Disable all WOL bits as WOL can interfere normal Rx 1827 * operation. 1828 */ 1829 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1830 1831 /* 1832 * Configure Tx/Rx MACs. 1833 * - Auto-padding for short frames. 1834 * - Enable CRC generation. 1835 * Start with full-duplex/1000Mbps media. Actual reconfiguration 1836 * of MAC is followed after link establishment. 1837 */ 1838 CSR_WRITE_4(sc, AGE_MAC_CFG, 1839 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 1840 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 1841 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1842 MAC_CFG_PREAMBLE_MASK)); 1843 1844 /* Set up the receive filter. */ 1845 age_rxfilter(sc); 1846 age_rxvlan(sc); 1847 1848 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1849 reg |= MAC_CFG_RXCSUM_ENB; 1850 1851 /* Ack all pending interrupts and clear it. */ 1852 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 1853 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 1854 1855 /* Finally enable Tx/Rx MAC. */ 1856 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 1857 1858 sc->age_flags &= ~AGE_FLAG_LINK; 1859 1860 /* Switch to the current media. */ 1861 mii = &sc->sc_miibus; 1862 mii_mediachg(mii); 1863 1864 callout_schedule(&sc->sc_tick_ch, hz); 1865 1866 ifp->if_flags |= IFF_RUNNING; 1867 ifp->if_flags &= ~IFF_OACTIVE; 1868 1869 return 0; 1870 } 1871 1872 static void 1873 age_stop(struct ifnet *ifp, int disable) 1874 { 1875 struct age_softc *sc = ifp->if_softc; 1876 struct age_txdesc *txd; 1877 struct age_rxdesc *rxd; 1878 uint32_t reg; 1879 int i; 1880 1881 callout_stop(&sc->sc_tick_ch); 1882 1883 /* 1884 * Mark the interface down and cancel the watchdog timer. 1885 */ 1886 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1887 ifp->if_timer = 0; 1888 1889 sc->age_flags &= ~AGE_FLAG_LINK; 1890 1891 mii_down(&sc->sc_miibus); 1892 1893 /* 1894 * Disable interrupts. 1895 */ 1896 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 1897 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 1898 1899 /* Stop CMB/SMB updates. */ 1900 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 1901 1902 /* Stop Rx/Tx MAC. */ 1903 age_stop_rxmac(sc); 1904 age_stop_txmac(sc); 1905 1906 /* Stop DMA. */ 1907 CSR_WRITE_4(sc, AGE_DMA_CFG, 1908 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 1909 1910 /* Stop TxQ/RxQ. */ 1911 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1912 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 1913 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1914 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 1915 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1916 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1917 break; 1918 DELAY(10); 1919 } 1920 if (i == 0) 1921 printf("%s: stopping Rx/Tx MACs timed out(0x%08x)!\n", 1922 device_xname(sc->sc_dev), reg); 1923 1924 /* Reclaim Rx buffers that have been processed. */ 1925 if (sc->age_cdata.age_rxhead != NULL) 1926 m_freem(sc->age_cdata.age_rxhead); 1927 AGE_RXCHAIN_RESET(sc); 1928 1929 /* 1930 * Free RX and TX mbufs still in the queues. 1931 */ 1932 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1933 rxd = &sc->age_cdata.age_rxdesc[i]; 1934 if (rxd->rx_m != NULL) { 1935 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1936 m_freem(rxd->rx_m); 1937 rxd->rx_m = NULL; 1938 } 1939 } 1940 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1941 txd = &sc->age_cdata.age_txdesc[i]; 1942 if (txd->tx_m != NULL) { 1943 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1944 m_freem(txd->tx_m); 1945 txd->tx_m = NULL; 1946 } 1947 } 1948 } 1949 1950 static void 1951 age_stats_update(struct age_softc *sc) 1952 { 1953 struct ifnet *ifp = &sc->sc_ec.ec_if; 1954 struct age_stats *stat; 1955 struct smb *smb; 1956 1957 stat = &sc->age_stat; 1958 1959 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 1960 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1961 1962 smb = sc->age_rdata.age_smb_block; 1963 if (smb->updated == 0) 1964 return; 1965 1966 /* Rx stats. */ 1967 stat->rx_frames += smb->rx_frames; 1968 stat->rx_bcast_frames += smb->rx_bcast_frames; 1969 stat->rx_mcast_frames += smb->rx_mcast_frames; 1970 stat->rx_pause_frames += smb->rx_pause_frames; 1971 stat->rx_control_frames += smb->rx_control_frames; 1972 stat->rx_crcerrs += smb->rx_crcerrs; 1973 stat->rx_lenerrs += smb->rx_lenerrs; 1974 stat->rx_bytes += smb->rx_bytes; 1975 stat->rx_runts += smb->rx_runts; 1976 stat->rx_fragments += smb->rx_fragments; 1977 stat->rx_pkts_64 += smb->rx_pkts_64; 1978 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1979 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1980 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1981 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1982 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1983 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1984 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1985 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1986 stat->rx_desc_oflows += smb->rx_desc_oflows; 1987 stat->rx_alignerrs += smb->rx_alignerrs; 1988 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1989 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1990 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1991 1992 /* Tx stats. */ 1993 stat->tx_frames += smb->tx_frames; 1994 stat->tx_bcast_frames += smb->tx_bcast_frames; 1995 stat->tx_mcast_frames += smb->tx_mcast_frames; 1996 stat->tx_pause_frames += smb->tx_pause_frames; 1997 stat->tx_excess_defer += smb->tx_excess_defer; 1998 stat->tx_control_frames += smb->tx_control_frames; 1999 stat->tx_deferred += smb->tx_deferred; 2000 stat->tx_bytes += smb->tx_bytes; 2001 stat->tx_pkts_64 += smb->tx_pkts_64; 2002 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2003 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2004 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2005 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2006 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2007 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2008 stat->tx_single_colls += smb->tx_single_colls; 2009 stat->tx_multi_colls += smb->tx_multi_colls; 2010 stat->tx_late_colls += smb->tx_late_colls; 2011 stat->tx_excess_colls += smb->tx_excess_colls; 2012 stat->tx_underrun += smb->tx_underrun; 2013 stat->tx_desc_underrun += smb->tx_desc_underrun; 2014 stat->tx_lenerrs += smb->tx_lenerrs; 2015 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2016 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2017 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2018 2019 /* Update counters in ifnet. */ 2020 ifp->if_opackets += smb->tx_frames; 2021 2022 ifp->if_collisions += smb->tx_single_colls + 2023 smb->tx_multi_colls + smb->tx_late_colls + 2024 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 2025 2026 ifp->if_oerrors += smb->tx_excess_colls + 2027 smb->tx_late_colls + smb->tx_underrun + 2028 smb->tx_pkts_truncated; 2029 2030 ifp->if_ipackets += smb->rx_frames; 2031 2032 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2033 smb->rx_runts + smb->rx_pkts_truncated + 2034 smb->rx_fifo_oflows + smb->rx_desc_oflows + 2035 smb->rx_alignerrs; 2036 2037 /* Update done, clear. */ 2038 smb->updated = 0; 2039 2040 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2041 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2042 } 2043 2044 static void 2045 age_stop_txmac(struct age_softc *sc) 2046 { 2047 uint32_t reg; 2048 int i; 2049 2050 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2051 if ((reg & MAC_CFG_TX_ENB) != 0) { 2052 reg &= ~MAC_CFG_TX_ENB; 2053 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2054 } 2055 /* Stop Tx DMA engine. */ 2056 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2057 if ((reg & DMA_CFG_RD_ENB) != 0) { 2058 reg &= ~DMA_CFG_RD_ENB; 2059 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2060 } 2061 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2062 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2063 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2064 break; 2065 DELAY(10); 2066 } 2067 if (i == 0) 2068 printf("%s: stopping TxMAC timeout!\n", device_xname(sc->sc_dev)); 2069 } 2070 2071 static void 2072 age_stop_rxmac(struct age_softc *sc) 2073 { 2074 uint32_t reg; 2075 int i; 2076 2077 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2078 if ((reg & MAC_CFG_RX_ENB) != 0) { 2079 reg &= ~MAC_CFG_RX_ENB; 2080 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2081 } 2082 /* Stop Rx DMA engine. */ 2083 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2084 if ((reg & DMA_CFG_WR_ENB) != 0) { 2085 reg &= ~DMA_CFG_WR_ENB; 2086 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2087 } 2088 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2089 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2090 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2091 break; 2092 DELAY(10); 2093 } 2094 if (i == 0) 2095 printf("%s: stopping RxMAC timeout!\n", device_xname(sc->sc_dev)); 2096 } 2097 2098 static void 2099 age_init_tx_ring(struct age_softc *sc) 2100 { 2101 struct age_ring_data *rd; 2102 struct age_txdesc *txd; 2103 int i; 2104 2105 sc->age_cdata.age_tx_prod = 0; 2106 sc->age_cdata.age_tx_cons = 0; 2107 sc->age_cdata.age_tx_cnt = 0; 2108 2109 rd = &sc->age_rdata; 2110 memset(rd->age_tx_ring, 0, AGE_TX_RING_SZ); 2111 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2112 txd = &sc->age_cdata.age_txdesc[i]; 2113 txd->tx_desc = &rd->age_tx_ring[i]; 2114 txd->tx_m = NULL; 2115 } 2116 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 2117 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2118 } 2119 2120 static int 2121 age_init_rx_ring(struct age_softc *sc) 2122 { 2123 struct age_ring_data *rd; 2124 struct age_rxdesc *rxd; 2125 int i; 2126 2127 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 2128 rd = &sc->age_rdata; 2129 memset(rd->age_rx_ring, 0, AGE_RX_RING_SZ); 2130 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2131 rxd = &sc->age_cdata.age_rxdesc[i]; 2132 rxd->rx_m = NULL; 2133 rxd->rx_desc = &rd->age_rx_ring[i]; 2134 if (age_newbuf(sc, rxd, 1) != 0) 2135 return ENOBUFS; 2136 } 2137 2138 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 0, 2139 sc->age_cdata.age_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2140 2141 return 0; 2142 } 2143 2144 static void 2145 age_init_rr_ring(struct age_softc *sc) 2146 { 2147 struct age_ring_data *rd; 2148 2149 sc->age_cdata.age_rr_cons = 0; 2150 AGE_RXCHAIN_RESET(sc); 2151 2152 rd = &sc->age_rdata; 2153 memset(rd->age_rr_ring, 0, AGE_RR_RING_SZ); 2154 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 2155 sc->age_cdata.age_rr_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2156 } 2157 2158 static void 2159 age_init_cmb_block(struct age_softc *sc) 2160 { 2161 struct age_ring_data *rd; 2162 2163 rd = &sc->age_rdata; 2164 memset(rd->age_cmb_block, 0, AGE_CMB_BLOCK_SZ); 2165 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 2166 sc->age_cdata.age_cmb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2167 } 2168 2169 static void 2170 age_init_smb_block(struct age_softc *sc) 2171 { 2172 struct age_ring_data *rd; 2173 2174 rd = &sc->age_rdata; 2175 memset(rd->age_smb_block, 0, AGE_SMB_BLOCK_SZ); 2176 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2177 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2178 } 2179 2180 static int 2181 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd, int init) 2182 { 2183 struct rx_desc *desc; 2184 struct mbuf *m; 2185 bus_dmamap_t map; 2186 int error; 2187 2188 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 2189 if (m == NULL) 2190 return ENOBUFS; 2191 MCLGET(m, init ? M_WAITOK : M_DONTWAIT); 2192 if (!(m->m_flags & M_EXT)) { 2193 m_freem(m); 2194 return ENOBUFS; 2195 } 2196 2197 m->m_len = m->m_pkthdr.len = MCLBYTES; 2198 m_adj(m, ETHER_ALIGN); 2199 2200 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2201 sc->age_cdata.age_rx_sparemap, m, BUS_DMA_NOWAIT); 2202 2203 if (error != 0) { 2204 if (!error) { 2205 bus_dmamap_unload(sc->sc_dmat, 2206 sc->age_cdata.age_rx_sparemap); 2207 error = EFBIG; 2208 printf("%s: too many segments?!\n", 2209 device_xname(sc->sc_dev)); 2210 } 2211 m_freem(m); 2212 2213 if (init) 2214 printf("%s: can't load RX mbuf\n", device_xname(sc->sc_dev)); 2215 return error; 2216 } 2217 2218 if (rxd->rx_m != NULL) { 2219 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2220 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2221 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2222 } 2223 map = rxd->rx_dmamap; 2224 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 2225 sc->age_cdata.age_rx_sparemap = map; 2226 rxd->rx_m = m; 2227 2228 desc = rxd->rx_desc; 2229 desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 2230 desc->len = 2231 htole32((rxd->rx_dmamap->dm_segs[0].ds_len & AGE_RD_LEN_MASK) << 2232 AGE_RD_LEN_SHIFT); 2233 2234 return 0; 2235 } 2236 2237 static void 2238 age_rxvlan(struct age_softc *sc) 2239 { 2240 uint32_t reg; 2241 2242 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2243 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2244 if (sc->sc_ec.ec_capabilities & ETHERCAP_VLAN_HWTAGGING) 2245 reg |= MAC_CFG_VLAN_TAG_STRIP; 2246 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2247 } 2248 2249 static void 2250 age_rxfilter(struct age_softc *sc) 2251 { 2252 struct ethercom *ec = &sc->sc_ec; 2253 struct ifnet *ifp = &sc->sc_ec.ec_if; 2254 struct ether_multi *enm; 2255 struct ether_multistep step; 2256 uint32_t crc; 2257 uint32_t mchash[2]; 2258 uint32_t rxcfg; 2259 2260 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 2261 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2262 ifp->if_flags &= ~IFF_ALLMULTI; 2263 2264 /* 2265 * Always accept broadcast frames. 2266 */ 2267 rxcfg |= MAC_CFG_BCAST; 2268 2269 if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 2270 ifp->if_flags |= IFF_ALLMULTI; 2271 if (ifp->if_flags & IFF_PROMISC) 2272 rxcfg |= MAC_CFG_PROMISC; 2273 else 2274 rxcfg |= MAC_CFG_ALLMULTI; 2275 mchash[0] = mchash[1] = 0xFFFFFFFF; 2276 } else { 2277 /* Program new filter. */ 2278 memset(mchash, 0, sizeof(mchash)); 2279 2280 ETHER_FIRST_MULTI(step, ec, enm); 2281 while (enm != NULL) { 2282 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2283 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2284 ETHER_NEXT_MULTI(step, enm); 2285 } 2286 } 2287 2288 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 2289 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 2290 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 2291 } 2292
Indexes created Fri Oct 03 02:09:57 GMT 2025