if_age.c revision 1.44
1 /* $NetBSD: if_age.c,v 1.44 2014/03/29 19:28:24 christos Exp $ */ 2 /* $OpenBSD: if_age.c,v 1.1 2009/01/16 05:00:34 kevlo Exp $ */ 3 4 /*- 5 * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: if_age.c,v 1.44 2014/03/29 19:28:24 christos Exp $"); 35 36 #include "vlan.h" 37 38 #include <sys/param.h> 39 #include <sys/proc.h> 40 #include <sys/endian.h> 41 #include <sys/systm.h> 42 #include <sys/types.h> 43 #include <sys/sockio.h> 44 #include <sys/mbuf.h> 45 #include <sys/queue.h> 46 #include <sys/kernel.h> 47 #include <sys/device.h> 48 #include <sys/callout.h> 49 #include <sys/socket.h> 50 51 #include <net/if.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 #include <net/if_ether.h> 55 56 #ifdef INET 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <netinet/ip.h> 61 #endif 62 63 #include <net/if_types.h> 64 #include <net/if_vlanvar.h> 65 66 #include <net/bpf.h> 67 68 #include <sys/rnd.h> 69 70 #include <dev/mii/mii.h> 71 #include <dev/mii/miivar.h> 72 73 #include <dev/pci/pcireg.h> 74 #include <dev/pci/pcivar.h> 75 #include <dev/pci/pcidevs.h> 76 77 #include <dev/pci/if_agereg.h> 78 79 static int age_match(device_t, cfdata_t, void *); 80 static void age_attach(device_t, device_t, void *); 81 static int age_detach(device_t, int); 82 83 static bool age_resume(device_t, const pmf_qual_t *); 84 85 static int age_miibus_readreg(device_t, int, int); 86 static void age_miibus_writereg(device_t, int, int, int); 87 static void age_miibus_statchg(struct ifnet *); 88 89 static int age_init(struct ifnet *); 90 static int age_ioctl(struct ifnet *, u_long, void *); 91 static void age_start(struct ifnet *); 92 static void age_watchdog(struct ifnet *); 93 static bool age_shutdown(device_t, int); 94 static void age_mediastatus(struct ifnet *, struct ifmediareq *); 95 static int age_mediachange(struct ifnet *); 96 97 static int age_intr(void *); 98 static int age_dma_alloc(struct age_softc *); 99 static void age_dma_free(struct age_softc *); 100 static void age_get_macaddr(struct age_softc *, uint8_t[]); 101 static void age_phy_reset(struct age_softc *); 102 103 static int age_encap(struct age_softc *, struct mbuf **); 104 static void age_init_tx_ring(struct age_softc *); 105 static int age_init_rx_ring(struct age_softc *); 106 static void age_init_rr_ring(struct age_softc *); 107 static void age_init_cmb_block(struct age_softc *); 108 static void age_init_smb_block(struct age_softc *); 109 static int age_newbuf(struct age_softc *, struct age_rxdesc *, int); 110 static void age_mac_config(struct age_softc *); 111 static void age_txintr(struct age_softc *, int); 112 static void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 113 static void age_rxintr(struct age_softc *, int); 114 static void age_tick(void *); 115 static void age_reset(struct age_softc *); 116 static void age_stop(struct ifnet *, int); 117 static void age_stats_update(struct age_softc *); 118 static void age_stop_txmac(struct age_softc *); 119 static void age_stop_rxmac(struct age_softc *); 120 static void age_rxvlan(struct age_softc *sc); 121 static void age_rxfilter(struct age_softc *); 122 123 CFATTACH_DECL_NEW(age, sizeof(struct age_softc), 124 age_match, age_attach, age_detach, NULL); 125 126 int agedebug = 0; 127 #define DPRINTF(x) do { if (agedebug) printf x; } while (0) 128 129 #define ETHER_ALIGN 2 130 #define AGE_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 131 132 static int 133 age_match(device_t dev, cfdata_t match, void *aux) 134 { 135 struct pci_attach_args *pa = aux; 136 137 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && 138 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_GIGA); 139 } 140 141 static void 142 age_attach(device_t parent, device_t self, void *aux) 143 { 144 struct age_softc *sc = device_private(self); 145 struct pci_attach_args *pa = aux; 146 pci_intr_handle_t ih; 147 const char *intrstr; 148 struct ifnet *ifp = &sc->sc_ec.ec_if; 149 pcireg_t memtype; 150 int error = 0; 151 char intrbuf[PCI_INTRSTR_LEN]; 152 153 aprint_naive("\n"); 154 aprint_normal(": Attansic/Atheros L1 Gigabit Ethernet\n"); 155 156 sc->sc_dev = self; 157 sc->sc_dmat = pa->pa_dmat; 158 sc->sc_pct = pa->pa_pc; 159 sc->sc_pcitag = pa->pa_tag; 160 161 /* 162 * Allocate IO memory 163 */ 164 memtype = pci_mapreg_type(sc->sc_pct, sc->sc_pcitag, AGE_PCIR_BAR); 165 switch (memtype) { 166 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 167 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 168 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 169 break; 170 default: 171 aprint_error_dev(self, "invalid base address register\n"); 172 break; 173 } 174 175 if (pci_mapreg_map(pa, AGE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 176 &sc->sc_mem_bh, NULL, &sc->sc_mem_size) != 0) { 177 aprint_error_dev(self, "could not map mem space\n"); 178 return; 179 } 180 181 if (pci_intr_map(pa, &ih) != 0) { 182 aprint_error_dev(self, "could not map interrupt\n"); 183 goto fail; 184 } 185 186 /* 187 * Allocate IRQ 188 */ 189 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf)); 190 sc->sc_irq_handle = pci_intr_establish(sc->sc_pct, ih, IPL_NET, 191 age_intr, sc); 192 if (sc->sc_irq_handle == NULL) { 193 aprint_error_dev(self, "could not establish interrupt"); 194 if (intrstr != NULL) 195 aprint_error(" at %s", intrstr); 196 aprint_error("\n"); 197 goto fail; 198 } 199 aprint_normal_dev(self, "%s\n", intrstr); 200 201 /* Set PHY address. */ 202 sc->age_phyaddr = AGE_PHY_ADDR; 203 204 /* Reset PHY. */ 205 age_phy_reset(sc); 206 207 /* Reset the ethernet controller. */ 208 age_reset(sc); 209 210 /* Get PCI and chip id/revision. */ 211 sc->age_rev = PCI_REVISION(pa->pa_class); 212 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 213 MASTER_CHIP_REV_SHIFT; 214 215 aprint_debug_dev(self, "PCI device revision : 0x%04x\n", sc->age_rev); 216 aprint_debug_dev(self, "Chip id/revision : 0x%04x\n", sc->age_chip_rev); 217 218 if (agedebug) { 219 aprint_debug_dev(self, "%d Tx FIFO, %d Rx FIFO\n", 220 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 221 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 222 } 223 224 /* Set max allowable DMA size. */ 225 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 226 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 227 228 /* Allocate DMA stuffs */ 229 error = age_dma_alloc(sc); 230 if (error) 231 goto fail; 232 233 callout_init(&sc->sc_tick_ch, 0); 234 callout_setfunc(&sc->sc_tick_ch, age_tick, sc); 235 236 /* Load station address. */ 237 age_get_macaddr(sc, sc->sc_enaddr); 238 239 aprint_normal_dev(self, "Ethernet address %s\n", 240 ether_sprintf(sc->sc_enaddr)); 241 242 ifp->if_softc = sc; 243 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 244 ifp->if_init = age_init; 245 ifp->if_ioctl = age_ioctl; 246 ifp->if_start = age_start; 247 ifp->if_stop = age_stop; 248 ifp->if_watchdog = age_watchdog; 249 ifp->if_baudrate = IF_Gbps(1); 250 IFQ_SET_MAXLEN(&ifp->if_snd, AGE_TX_RING_CNT - 1); 251 IFQ_SET_READY(&ifp->if_snd); 252 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 253 254 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 255 256 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Rx | 257 IFCAP_CSUM_TCPv4_Rx | 258 IFCAP_CSUM_UDPv4_Rx; 259 #ifdef AGE_CHECKSUM 260 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | 261 IFCAP_CSUM_TCPv4_Tx | 262 IFCAP_CSUM_UDPv4_Tx; 263 #endif 264 265 #if NVLAN > 0 266 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 267 #endif 268 269 /* Set up MII bus. */ 270 sc->sc_miibus.mii_ifp = ifp; 271 sc->sc_miibus.mii_readreg = age_miibus_readreg; 272 sc->sc_miibus.mii_writereg = age_miibus_writereg; 273 sc->sc_miibus.mii_statchg = age_miibus_statchg; 274 275 sc->sc_ec.ec_mii = &sc->sc_miibus; 276 ifmedia_init(&sc->sc_miibus.mii_media, 0, age_mediachange, 277 age_mediastatus); 278 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 279 MII_OFFSET_ANY, MIIF_DOPAUSE); 280 281 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 282 aprint_error_dev(self, "no PHY found!\n"); 283 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 284 0, NULL); 285 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 286 } else 287 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 288 289 if_attach(ifp); 290 ether_ifattach(ifp, sc->sc_enaddr); 291 292 if (pmf_device_register1(self, NULL, age_resume, age_shutdown)) 293 pmf_class_network_register(self, ifp); 294 else 295 aprint_error_dev(self, "couldn't establish power handler\n"); 296 297 return; 298 299 fail: 300 age_dma_free(sc); 301 if (sc->sc_irq_handle != NULL) { 302 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 303 sc->sc_irq_handle = NULL; 304 } 305 if (sc->sc_mem_size) { 306 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 307 sc->sc_mem_size = 0; 308 } 309 } 310 311 static int 312 age_detach(device_t self, int flags) 313 { 314 struct age_softc *sc = device_private(self); 315 struct ifnet *ifp = &sc->sc_ec.ec_if; 316 int s; 317 318 pmf_device_deregister(self); 319 s = splnet(); 320 age_stop(ifp, 0); 321 splx(s); 322 323 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 324 325 /* Delete all remaining media. */ 326 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 327 328 ether_ifdetach(ifp); 329 if_detach(ifp); 330 age_dma_free(sc); 331 332 if (sc->sc_irq_handle != NULL) { 333 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 334 sc->sc_irq_handle = NULL; 335 } 336 if (sc->sc_mem_size) { 337 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 338 sc->sc_mem_size = 0; 339 } 340 return 0; 341 } 342 343 /* 344 * Read a PHY register on the MII of the L1. 345 */ 346 static int 347 age_miibus_readreg(device_t dev, int phy, int reg) 348 { 349 struct age_softc *sc = device_private(dev); 350 uint32_t v; 351 int i; 352 353 if (phy != sc->age_phyaddr) 354 return 0; 355 356 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 357 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 358 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 359 DELAY(1); 360 v = CSR_READ_4(sc, AGE_MDIO); 361 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 362 break; 363 } 364 365 if (i == 0) { 366 printf("%s: phy read timeout: phy %d, reg %d\n", 367 device_xname(sc->sc_dev), phy, reg); 368 return 0; 369 } 370 371 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 372 } 373 374 /* 375 * Write a PHY register on the MII of the L1. 376 */ 377 static void 378 age_miibus_writereg(device_t dev, int phy, int reg, int val) 379 { 380 struct age_softc *sc = device_private(dev); 381 uint32_t v; 382 int i; 383 384 if (phy != sc->age_phyaddr) 385 return; 386 387 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 388 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 389 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 390 391 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 392 DELAY(1); 393 v = CSR_READ_4(sc, AGE_MDIO); 394 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 395 break; 396 } 397 398 if (i == 0) { 399 printf("%s: phy write timeout: phy %d, reg %d\n", 400 device_xname(sc->sc_dev), phy, reg); 401 } 402 } 403 404 /* 405 * Callback from MII layer when media changes. 406 */ 407 static void 408 age_miibus_statchg(struct ifnet *ifp) 409 { 410 struct age_softc *sc = ifp->if_softc; 411 struct mii_data *mii = &sc->sc_miibus; 412 413 if ((ifp->if_flags & IFF_RUNNING) == 0) 414 return; 415 416 sc->age_flags &= ~AGE_FLAG_LINK; 417 if ((mii->mii_media_status & IFM_AVALID) != 0) { 418 switch (IFM_SUBTYPE(mii->mii_media_active)) { 419 case IFM_10_T: 420 case IFM_100_TX: 421 case IFM_1000_T: 422 sc->age_flags |= AGE_FLAG_LINK; 423 break; 424 default: 425 break; 426 } 427 } 428 429 /* Stop Rx/Tx MACs. */ 430 age_stop_rxmac(sc); 431 age_stop_txmac(sc); 432 433 /* Program MACs with resolved speed/duplex/flow-control. */ 434 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 435 uint32_t reg; 436 437 age_mac_config(sc); 438 reg = CSR_READ_4(sc, AGE_MAC_CFG); 439 /* Restart DMA engine and Tx/Rx MAC. */ 440 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 441 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 442 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 443 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 444 } 445 } 446 447 /* 448 * Get the current interface media status. 449 */ 450 static void 451 age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 452 { 453 struct age_softc *sc = ifp->if_softc; 454 struct mii_data *mii = &sc->sc_miibus; 455 456 mii_pollstat(mii); 457 ifmr->ifm_status = mii->mii_media_status; 458 ifmr->ifm_active = mii->mii_media_active; 459 } 460 461 /* 462 * Set hardware to newly-selected media. 463 */ 464 static int 465 age_mediachange(struct ifnet *ifp) 466 { 467 struct age_softc *sc = ifp->if_softc; 468 struct mii_data *mii = &sc->sc_miibus; 469 int error; 470 471 if (mii->mii_instance != 0) { 472 struct mii_softc *miisc; 473 474 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 475 mii_phy_reset(miisc); 476 } 477 error = mii_mediachg(mii); 478 479 return error; 480 } 481 482 static int 483 age_intr(void *arg) 484 { 485 struct age_softc *sc = arg; 486 struct ifnet *ifp = &sc->sc_ec.ec_if; 487 struct cmb *cmb; 488 uint32_t status; 489 490 status = CSR_READ_4(sc, AGE_INTR_STATUS); 491 if (status == 0 || (status & AGE_INTRS) == 0) 492 return 0; 493 494 cmb = sc->age_rdata.age_cmb_block; 495 if (cmb == NULL) { 496 /* Happens when bringing up the interface 497 * w/o having a carrier. Ack the interrupt. 498 */ 499 CSR_WRITE_4(sc, AGE_INTR_STATUS, status); 500 return 0; 501 } 502 503 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 504 sc->age_cdata.age_cmb_block_map->dm_mapsize, 505 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 506 status = le32toh(cmb->intr_status); 507 /* ACK/reenable interrupts */ 508 CSR_WRITE_4(sc, AGE_INTR_STATUS, status); 509 while ((status & AGE_INTRS) != 0) { 510 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 511 TPD_CONS_SHIFT; 512 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 513 RRD_PROD_SHIFT; 514 515 /* Let hardware know CMB was served. */ 516 cmb->intr_status = 0; 517 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 518 sc->age_cdata.age_cmb_block_map->dm_mapsize, 519 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 520 521 if (ifp->if_flags & IFF_RUNNING) { 522 if (status & INTR_CMB_RX) 523 age_rxintr(sc, sc->age_rr_prod); 524 525 if (status & INTR_CMB_TX) 526 age_txintr(sc, sc->age_tpd_cons); 527 528 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 529 if (status & INTR_DMA_RD_TO_RST) 530 printf("%s: DMA read error! -- " 531 "resetting\n", 532 device_xname(sc->sc_dev)); 533 if (status & INTR_DMA_WR_TO_RST) 534 printf("%s: DMA write error! -- " 535 "resetting\n", 536 device_xname(sc->sc_dev)); 537 age_init(ifp); 538 } 539 540 age_start(ifp); 541 542 if (status & INTR_SMB) 543 age_stats_update(sc); 544 } 545 /* check if more interrupts did came in */ 546 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 547 sc->age_cdata.age_cmb_block_map->dm_mapsize, 548 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 549 status = le32toh(cmb->intr_status); 550 } 551 552 return 1; 553 } 554 555 static void 556 age_get_macaddr(struct age_softc *sc, uint8_t eaddr[]) 557 { 558 uint32_t ea[2], reg; 559 int i, vpdc; 560 561 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 562 if ((reg & SPI_VPD_ENB) != 0) { 563 /* Get VPD stored in TWSI EEPROM. */ 564 reg &= ~SPI_VPD_ENB; 565 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 566 } 567 568 if (pci_get_capability(sc->sc_pct, sc->sc_pcitag, 569 PCI_CAP_VPD, &vpdc, NULL)) { 570 /* 571 * PCI VPD capability found, let TWSI reload EEPROM. 572 * This will set Ethernet address of controller. 573 */ 574 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | 575 TWSI_CTRL_SW_LD_START); 576 for (i = 100; i > 0; i++) { 577 DELAY(1000); 578 reg = CSR_READ_4(sc, AGE_TWSI_CTRL); 579 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 580 break; 581 } 582 if (i == 0) 583 printf("%s: reloading EEPROM timeout!\n", 584 device_xname(sc->sc_dev)); 585 } else { 586 if (agedebug) 587 printf("%s: PCI VPD capability not found!\n", 588 device_xname(sc->sc_dev)); 589 } 590 591 ea[0] = CSR_READ_4(sc, AGE_PAR0); 592 ea[1] = CSR_READ_4(sc, AGE_PAR1); 593 594 eaddr[0] = (ea[1] >> 8) & 0xFF; 595 eaddr[1] = (ea[1] >> 0) & 0xFF; 596 eaddr[2] = (ea[0] >> 24) & 0xFF; 597 eaddr[3] = (ea[0] >> 16) & 0xFF; 598 eaddr[4] = (ea[0] >> 8) & 0xFF; 599 eaddr[5] = (ea[0] >> 0) & 0xFF; 600 } 601 602 static void 603 age_phy_reset(struct age_softc *sc) 604 { 605 uint16_t reg, pn; 606 int i, linkup; 607 608 /* Reset PHY. */ 609 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 610 DELAY(2000); 611 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 612 DELAY(2000); 613 614 #define ATPHY_DBG_ADDR 0x1D 615 #define ATPHY_DBG_DATA 0x1E 616 #define ATPHY_CDTC 0x16 617 #define PHY_CDTC_ENB 0x0001 618 #define PHY_CDTC_POFF 8 619 #define ATPHY_CDTS 0x1C 620 #define PHY_CDTS_STAT_OK 0x0000 621 #define PHY_CDTS_STAT_SHORT 0x0100 622 #define PHY_CDTS_STAT_OPEN 0x0200 623 #define PHY_CDTS_STAT_INVAL 0x0300 624 #define PHY_CDTS_STAT_MASK 0x0300 625 626 /* Check power saving mode. Magic from Linux. */ 627 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET); 628 for (linkup = 0, pn = 0; pn < 4; pn++) { 629 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, ATPHY_CDTC, 630 (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB); 631 for (i = 200; i > 0; i--) { 632 DELAY(1000); 633 reg = age_miibus_readreg(sc->sc_dev, sc->age_phyaddr, 634 ATPHY_CDTC); 635 if ((reg & PHY_CDTC_ENB) == 0) 636 break; 637 } 638 DELAY(1000); 639 reg = age_miibus_readreg(sc->sc_dev, sc->age_phyaddr, 640 ATPHY_CDTS); 641 if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) { 642 linkup++; 643 break; 644 } 645 } 646 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, MII_BMCR, 647 BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 648 if (linkup == 0) { 649 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, 650 ATPHY_DBG_ADDR, 0); 651 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, 652 ATPHY_DBG_DATA, 0x124E); 653 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, 654 ATPHY_DBG_ADDR, 1); 655 reg = age_miibus_readreg(sc->sc_dev, sc->age_phyaddr, 656 ATPHY_DBG_DATA); 657 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, 658 ATPHY_DBG_DATA, reg | 0x03); 659 /* XXX */ 660 DELAY(1500 * 1000); 661 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, 662 ATPHY_DBG_ADDR, 0); 663 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, 664 ATPHY_DBG_DATA, 0x024E); 665 } 666 667 #undef ATPHY_DBG_ADDR 668 #undef ATPHY_DBG_DATA 669 #undef ATPHY_CDTC 670 #undef PHY_CDTC_ENB 671 #undef PHY_CDTC_POFF 672 #undef ATPHY_CDTS 673 #undef PHY_CDTS_STAT_OK 674 #undef PHY_CDTS_STAT_SHORT 675 #undef PHY_CDTS_STAT_OPEN 676 #undef PHY_CDTS_STAT_INVAL 677 #undef PHY_CDTS_STAT_MASK 678 } 679 680 static int 681 age_dma_alloc(struct age_softc *sc) 682 { 683 struct age_txdesc *txd; 684 struct age_rxdesc *rxd; 685 int nsegs, error, i; 686 687 /* 688 * Create DMA stuffs for TX ring 689 */ 690 error = bus_dmamap_create(sc->sc_dmat, AGE_TX_RING_SZ, 1, 691 AGE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_tx_ring_map); 692 if (error) { 693 sc->age_cdata.age_tx_ring_map = NULL; 694 return ENOBUFS; 695 } 696 697 /* Allocate DMA'able memory for TX ring */ 698 error = bus_dmamem_alloc(sc->sc_dmat, AGE_TX_RING_SZ, 699 ETHER_ALIGN, 0, &sc->age_rdata.age_tx_ring_seg, 1, 700 &nsegs, BUS_DMA_NOWAIT); 701 if (error) { 702 printf("%s: could not allocate DMA'able memory for Tx ring, " 703 "error = %i\n", device_xname(sc->sc_dev), error); 704 return error; 705 } 706 707 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_tx_ring_seg, 708 nsegs, AGE_TX_RING_SZ, (void **)&sc->age_rdata.age_tx_ring, 709 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 710 if (error) 711 return ENOBUFS; 712 713 memset(sc->age_rdata.age_tx_ring, 0, AGE_TX_RING_SZ); 714 715 /* Load the DMA map for Tx ring. */ 716 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 717 sc->age_rdata.age_tx_ring, AGE_TX_RING_SZ, NULL, BUS_DMA_NOWAIT); 718 if (error) { 719 printf("%s: could not load DMA'able memory for Tx ring, " 720 "error = %i\n", device_xname(sc->sc_dev), error); 721 bus_dmamem_free(sc->sc_dmat, 722 &sc->age_rdata.age_tx_ring_seg, 1); 723 return error; 724 } 725 726 sc->age_rdata.age_tx_ring_paddr = 727 sc->age_cdata.age_tx_ring_map->dm_segs[0].ds_addr; 728 729 /* 730 * Create DMA stuffs for RX ring 731 */ 732 error = bus_dmamap_create(sc->sc_dmat, AGE_RX_RING_SZ, 1, 733 AGE_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_ring_map); 734 if (error) { 735 sc->age_cdata.age_rx_ring_map = NULL; 736 return ENOBUFS; 737 } 738 739 /* Allocate DMA'able memory for RX ring */ 740 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RX_RING_SZ, 741 ETHER_ALIGN, 0, &sc->age_rdata.age_rx_ring_seg, 1, 742 &nsegs, BUS_DMA_NOWAIT); 743 if (error) { 744 printf("%s: could not allocate DMA'able memory for Rx ring, " 745 "error = %i.\n", device_xname(sc->sc_dev), error); 746 return error; 747 } 748 749 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rx_ring_seg, 750 nsegs, AGE_RX_RING_SZ, (void **)&sc->age_rdata.age_rx_ring, 751 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 752 if (error) 753 return ENOBUFS; 754 755 memset(sc->age_rdata.age_rx_ring, 0, AGE_RX_RING_SZ); 756 757 /* Load the DMA map for Rx ring. */ 758 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 759 sc->age_rdata.age_rx_ring, AGE_RX_RING_SZ, NULL, BUS_DMA_NOWAIT); 760 if (error) { 761 printf("%s: could not load DMA'able memory for Rx ring, " 762 "error = %i.\n", device_xname(sc->sc_dev), error); 763 bus_dmamem_free(sc->sc_dmat, 764 &sc->age_rdata.age_rx_ring_seg, 1); 765 return error; 766 } 767 768 sc->age_rdata.age_rx_ring_paddr = 769 sc->age_cdata.age_rx_ring_map->dm_segs[0].ds_addr; 770 771 /* 772 * Create DMA stuffs for RX return ring 773 */ 774 error = bus_dmamap_create(sc->sc_dmat, AGE_RR_RING_SZ, 1, 775 AGE_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rr_ring_map); 776 if (error) { 777 sc->age_cdata.age_rr_ring_map = NULL; 778 return ENOBUFS; 779 } 780 781 /* Allocate DMA'able memory for RX return ring */ 782 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RR_RING_SZ, 783 ETHER_ALIGN, 0, &sc->age_rdata.age_rr_ring_seg, 1, 784 &nsegs, BUS_DMA_NOWAIT); 785 if (error) { 786 printf("%s: could not allocate DMA'able memory for Rx " 787 "return ring, error = %i.\n", 788 device_xname(sc->sc_dev), error); 789 return error; 790 } 791 792 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rr_ring_seg, 793 nsegs, AGE_RR_RING_SZ, (void **)&sc->age_rdata.age_rr_ring, 794 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 795 if (error) 796 return ENOBUFS; 797 798 memset(sc->age_rdata.age_rr_ring, 0, AGE_RR_RING_SZ); 799 800 /* Load the DMA map for Rx return ring. */ 801 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 802 sc->age_rdata.age_rr_ring, AGE_RR_RING_SZ, NULL, BUS_DMA_NOWAIT); 803 if (error) { 804 printf("%s: could not load DMA'able memory for Rx return ring, " 805 "error = %i\n", device_xname(sc->sc_dev), error); 806 bus_dmamem_free(sc->sc_dmat, 807 &sc->age_rdata.age_rr_ring_seg, 1); 808 return error; 809 } 810 811 sc->age_rdata.age_rr_ring_paddr = 812 sc->age_cdata.age_rr_ring_map->dm_segs[0].ds_addr; 813 814 /* 815 * Create DMA stuffs for CMB block 816 */ 817 error = bus_dmamap_create(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 1, 818 AGE_CMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 819 &sc->age_cdata.age_cmb_block_map); 820 if (error) { 821 sc->age_cdata.age_cmb_block_map = NULL; 822 return ENOBUFS; 823 } 824 825 /* Allocate DMA'able memory for CMB block */ 826 error = bus_dmamem_alloc(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 827 ETHER_ALIGN, 0, &sc->age_rdata.age_cmb_block_seg, 1, 828 &nsegs, BUS_DMA_NOWAIT); 829 if (error) { 830 printf("%s: could not allocate DMA'able memory for " 831 "CMB block, error = %i\n", device_xname(sc->sc_dev), error); 832 return error; 833 } 834 835 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_cmb_block_seg, 836 nsegs, AGE_CMB_BLOCK_SZ, (void **)&sc->age_rdata.age_cmb_block, 837 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 838 if (error) 839 return ENOBUFS; 840 841 memset(sc->age_rdata.age_cmb_block, 0, AGE_CMB_BLOCK_SZ); 842 843 /* Load the DMA map for CMB block. */ 844 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 845 sc->age_rdata.age_cmb_block, AGE_CMB_BLOCK_SZ, NULL, 846 BUS_DMA_NOWAIT); 847 if (error) { 848 printf("%s: could not load DMA'able memory for CMB block, " 849 "error = %i\n", device_xname(sc->sc_dev), error); 850 bus_dmamem_free(sc->sc_dmat, 851 &sc->age_rdata.age_cmb_block_seg, 1); 852 return error; 853 } 854 855 sc->age_rdata.age_cmb_block_paddr = 856 sc->age_cdata.age_cmb_block_map->dm_segs[0].ds_addr; 857 858 /* 859 * Create DMA stuffs for SMB block 860 */ 861 error = bus_dmamap_create(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 1, 862 AGE_SMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 863 &sc->age_cdata.age_smb_block_map); 864 if (error) { 865 sc->age_cdata.age_smb_block_map = NULL; 866 return ENOBUFS; 867 } 868 869 /* Allocate DMA'able memory for SMB block */ 870 error = bus_dmamem_alloc(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 871 ETHER_ALIGN, 0, &sc->age_rdata.age_smb_block_seg, 1, 872 &nsegs, BUS_DMA_NOWAIT); 873 if (error) { 874 printf("%s: could not allocate DMA'able memory for " 875 "SMB block, error = %i\n", device_xname(sc->sc_dev), error); 876 return error; 877 } 878 879 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_smb_block_seg, 880 nsegs, AGE_SMB_BLOCK_SZ, (void **)&sc->age_rdata.age_smb_block, 881 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 882 if (error) 883 return ENOBUFS; 884 885 memset(sc->age_rdata.age_smb_block, 0, AGE_SMB_BLOCK_SZ); 886 887 /* Load the DMA map for SMB block */ 888 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 889 sc->age_rdata.age_smb_block, AGE_SMB_BLOCK_SZ, NULL, 890 BUS_DMA_NOWAIT); 891 if (error) { 892 printf("%s: could not load DMA'able memory for SMB block, " 893 "error = %i\n", device_xname(sc->sc_dev), error); 894 bus_dmamem_free(sc->sc_dmat, 895 &sc->age_rdata.age_smb_block_seg, 1); 896 return error; 897 } 898 899 sc->age_rdata.age_smb_block_paddr = 900 sc->age_cdata.age_smb_block_map->dm_segs[0].ds_addr; 901 902 /* Create DMA maps for Tx buffers. */ 903 for (i = 0; i < AGE_TX_RING_CNT; i++) { 904 txd = &sc->age_cdata.age_txdesc[i]; 905 txd->tx_m = NULL; 906 txd->tx_dmamap = NULL; 907 error = bus_dmamap_create(sc->sc_dmat, AGE_TSO_MAXSIZE, 908 AGE_MAXTXSEGS, AGE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 909 &txd->tx_dmamap); 910 if (error) { 911 txd->tx_dmamap = NULL; 912 printf("%s: could not create Tx dmamap, error = %i.\n", 913 device_xname(sc->sc_dev), error); 914 return error; 915 } 916 } 917 918 /* Create DMA maps for Rx buffers. */ 919 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 920 BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_sparemap); 921 if (error) { 922 sc->age_cdata.age_rx_sparemap = NULL; 923 printf("%s: could not create spare Rx dmamap, error = %i.\n", 924 device_xname(sc->sc_dev), error); 925 return error; 926 } 927 for (i = 0; i < AGE_RX_RING_CNT; i++) { 928 rxd = &sc->age_cdata.age_rxdesc[i]; 929 rxd->rx_m = NULL; 930 rxd->rx_dmamap = NULL; 931 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 932 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 933 if (error) { 934 rxd->rx_dmamap = NULL; 935 printf("%s: could not create Rx dmamap, error = %i.\n", 936 device_xname(sc->sc_dev), error); 937 return error; 938 } 939 } 940 941 return 0; 942 } 943 944 static void 945 age_dma_free(struct age_softc *sc) 946 { 947 struct age_txdesc *txd; 948 struct age_rxdesc *rxd; 949 int i; 950 951 /* Tx buffers */ 952 for (i = 0; i < AGE_TX_RING_CNT; i++) { 953 txd = &sc->age_cdata.age_txdesc[i]; 954 if (txd->tx_dmamap != NULL) { 955 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 956 txd->tx_dmamap = NULL; 957 } 958 } 959 /* Rx buffers */ 960 for (i = 0; i < AGE_RX_RING_CNT; i++) { 961 rxd = &sc->age_cdata.age_rxdesc[i]; 962 if (rxd->rx_dmamap != NULL) { 963 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 964 rxd->rx_dmamap = NULL; 965 } 966 } 967 if (sc->age_cdata.age_rx_sparemap != NULL) { 968 bus_dmamap_destroy(sc->sc_dmat, sc->age_cdata.age_rx_sparemap); 969 sc->age_cdata.age_rx_sparemap = NULL; 970 } 971 972 /* Tx ring. */ 973 if (sc->age_cdata.age_tx_ring_map != NULL) 974 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_tx_ring_map); 975 if (sc->age_cdata.age_tx_ring_map != NULL && 976 sc->age_rdata.age_tx_ring != NULL) 977 bus_dmamem_free(sc->sc_dmat, 978 &sc->age_rdata.age_tx_ring_seg, 1); 979 sc->age_rdata.age_tx_ring = NULL; 980 sc->age_cdata.age_tx_ring_map = NULL; 981 982 /* Rx ring. */ 983 if (sc->age_cdata.age_rx_ring_map != NULL) 984 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rx_ring_map); 985 if (sc->age_cdata.age_rx_ring_map != NULL && 986 sc->age_rdata.age_rx_ring != NULL) 987 bus_dmamem_free(sc->sc_dmat, 988 &sc->age_rdata.age_rx_ring_seg, 1); 989 sc->age_rdata.age_rx_ring = NULL; 990 sc->age_cdata.age_rx_ring_map = NULL; 991 992 /* Rx return ring. */ 993 if (sc->age_cdata.age_rr_ring_map != NULL) 994 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rr_ring_map); 995 if (sc->age_cdata.age_rr_ring_map != NULL && 996 sc->age_rdata.age_rr_ring != NULL) 997 bus_dmamem_free(sc->sc_dmat, 998 &sc->age_rdata.age_rr_ring_seg, 1); 999 sc->age_rdata.age_rr_ring = NULL; 1000 sc->age_cdata.age_rr_ring_map = NULL; 1001 1002 /* CMB block */ 1003 if (sc->age_cdata.age_cmb_block_map != NULL) 1004 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_cmb_block_map); 1005 if (sc->age_cdata.age_cmb_block_map != NULL && 1006 sc->age_rdata.age_cmb_block != NULL) 1007 bus_dmamem_free(sc->sc_dmat, 1008 &sc->age_rdata.age_cmb_block_seg, 1); 1009 sc->age_rdata.age_cmb_block = NULL; 1010 sc->age_cdata.age_cmb_block_map = NULL; 1011 1012 /* SMB block */ 1013 if (sc->age_cdata.age_smb_block_map != NULL) 1014 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_smb_block_map); 1015 if (sc->age_cdata.age_smb_block_map != NULL && 1016 sc->age_rdata.age_smb_block != NULL) 1017 bus_dmamem_free(sc->sc_dmat, 1018 &sc->age_rdata.age_smb_block_seg, 1); 1019 sc->age_rdata.age_smb_block = NULL; 1020 sc->age_cdata.age_smb_block_map = NULL; 1021 } 1022 1023 static void 1024 age_start(struct ifnet *ifp) 1025 { 1026 struct age_softc *sc = ifp->if_softc; 1027 struct mbuf *m_head; 1028 int enq; 1029 1030 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1031 return; 1032 if ((sc->age_flags & AGE_FLAG_LINK) == 0) 1033 return; 1034 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1035 return; 1036 1037 enq = 0; 1038 for (;;) { 1039 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1040 if (m_head == NULL) 1041 break; 1042 1043 /* 1044 * Pack the data into the transmit ring. If we 1045 * don't have room, set the OACTIVE flag and wait 1046 * for the NIC to drain the ring. 1047 */ 1048 if (age_encap(sc, &m_head)) { 1049 if (m_head == NULL) 1050 break; 1051 IF_PREPEND(&ifp->if_snd, m_head); 1052 ifp->if_flags |= IFF_OACTIVE; 1053 break; 1054 } 1055 enq = 1; 1056 1057 /* 1058 * If there's a BPF listener, bounce a copy of this frame 1059 * to him. 1060 */ 1061 bpf_mtap(ifp, m_head); 1062 } 1063 1064 if (enq) { 1065 /* Update mbox. */ 1066 AGE_COMMIT_MBOX(sc); 1067 /* Set a timeout in case the chip goes out to lunch. */ 1068 ifp->if_timer = AGE_TX_TIMEOUT; 1069 } 1070 } 1071 1072 static void 1073 age_watchdog(struct ifnet *ifp) 1074 { 1075 struct age_softc *sc = ifp->if_softc; 1076 1077 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1078 printf("%s: watchdog timeout (missed link)\n", 1079 device_xname(sc->sc_dev)); 1080 ifp->if_oerrors++; 1081 age_init(ifp); 1082 return; 1083 } 1084 1085 if (sc->age_cdata.age_tx_cnt == 0) { 1086 printf("%s: watchdog timeout (missed Tx interrupts) " 1087 "-- recovering\n", device_xname(sc->sc_dev)); 1088 age_start(ifp); 1089 return; 1090 } 1091 1092 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1093 ifp->if_oerrors++; 1094 age_init(ifp); 1095 age_start(ifp); 1096 } 1097 1098 static bool 1099 age_shutdown(device_t self, int howto) 1100 { 1101 struct age_softc *sc; 1102 struct ifnet *ifp; 1103 1104 sc = device_private(self); 1105 ifp = &sc->sc_ec.ec_if; 1106 age_stop(ifp, 1); 1107 1108 return true; 1109 } 1110 1111 1112 static int 1113 age_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1114 { 1115 struct age_softc *sc = ifp->if_softc; 1116 int s, error; 1117 1118 s = splnet(); 1119 1120 error = ether_ioctl(ifp, cmd, data); 1121 if (error == ENETRESET) { 1122 if (ifp->if_flags & IFF_RUNNING) 1123 age_rxfilter(sc); 1124 error = 0; 1125 } 1126 1127 splx(s); 1128 return error; 1129 } 1130 1131 static void 1132 age_mac_config(struct age_softc *sc) 1133 { 1134 struct mii_data *mii; 1135 uint32_t reg; 1136 1137 mii = &sc->sc_miibus; 1138 1139 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1140 reg &= ~MAC_CFG_FULL_DUPLEX; 1141 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1142 reg &= ~MAC_CFG_SPEED_MASK; 1143 1144 /* Reprogram MAC with resolved speed/duplex. */ 1145 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1146 case IFM_10_T: 1147 case IFM_100_TX: 1148 reg |= MAC_CFG_SPEED_10_100; 1149 break; 1150 case IFM_1000_T: 1151 reg |= MAC_CFG_SPEED_1000; 1152 break; 1153 } 1154 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1155 reg |= MAC_CFG_FULL_DUPLEX; 1156 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1157 reg |= MAC_CFG_TX_FC; 1158 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1159 reg |= MAC_CFG_RX_FC; 1160 } 1161 1162 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1163 } 1164 1165 static bool 1166 age_resume(device_t dv, const pmf_qual_t *qual) 1167 { 1168 struct age_softc *sc = device_private(dv); 1169 uint16_t cmd; 1170 1171 /* 1172 * Clear INTx emulation disable for hardware that 1173 * is set in resume event. From Linux. 1174 */ 1175 cmd = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 1176 if ((cmd & PCI_COMMAND_INTERRUPT_DISABLE) != 0) { 1177 cmd &= ~PCI_COMMAND_INTERRUPT_DISABLE; 1178 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 1179 PCI_COMMAND_STATUS_REG, cmd); 1180 } 1181 1182 return true; 1183 } 1184 1185 static int 1186 age_encap(struct age_softc *sc, struct mbuf **m_head) 1187 { 1188 struct age_txdesc *txd, *txd_last; 1189 struct tx_desc *desc; 1190 struct mbuf *m; 1191 bus_dmamap_t map; 1192 uint32_t cflags, poff, vtag; 1193 int error, i, nsegs, prod; 1194 #if NVLAN > 0 1195 struct m_tag *mtag; 1196 #endif 1197 1198 m = *m_head; 1199 cflags = vtag = 0; 1200 poff = 0; 1201 1202 prod = sc->age_cdata.age_tx_prod; 1203 txd = &sc->age_cdata.age_txdesc[prod]; 1204 txd_last = txd; 1205 map = txd->tx_dmamap; 1206 1207 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1208 1209 if (error == EFBIG) { 1210 error = 0; 1211 1212 *m_head = m_pullup(*m_head, MHLEN); 1213 if (*m_head == NULL) { 1214 printf("%s: can't defrag TX mbuf\n", 1215 device_xname(sc->sc_dev)); 1216 return ENOBUFS; 1217 } 1218 1219 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1220 BUS_DMA_NOWAIT); 1221 1222 if (error != 0) { 1223 printf("%s: could not load defragged TX mbuf\n", 1224 device_xname(sc->sc_dev)); 1225 m_freem(*m_head); 1226 *m_head = NULL; 1227 return error; 1228 } 1229 } else if (error) { 1230 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 1231 return error; 1232 } 1233 1234 nsegs = map->dm_nsegs; 1235 1236 if (nsegs == 0) { 1237 m_freem(*m_head); 1238 *m_head = NULL; 1239 return EIO; 1240 } 1241 1242 /* Check descriptor overrun. */ 1243 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1244 bus_dmamap_unload(sc->sc_dmat, map); 1245 return ENOBUFS; 1246 } 1247 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1248 BUS_DMASYNC_PREWRITE); 1249 1250 m = *m_head; 1251 /* Configure Tx IP/TCP/UDP checksum offload. */ 1252 if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1253 cflags |= AGE_TD_CSUM; 1254 if ((m->m_pkthdr.csum_flags & M_CSUM_TCPv4) != 0) 1255 cflags |= AGE_TD_TCPCSUM; 1256 if ((m->m_pkthdr.csum_flags & M_CSUM_UDPv4) != 0) 1257 cflags |= AGE_TD_UDPCSUM; 1258 /* Set checksum start offset. */ 1259 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1260 } 1261 1262 #if NVLAN > 0 1263 /* Configure VLAN hardware tag insertion. */ 1264 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m))) { 1265 vtag = AGE_TX_VLAN_TAG(htons(VLAN_TAG_VALUE(mtag))); 1266 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1267 cflags |= AGE_TD_INSERT_VLAN_TAG; 1268 } 1269 #endif 1270 1271 desc = NULL; 1272 KASSERT(nsegs > 0); 1273 for (i = 0; ; i++) { 1274 desc = &sc->age_rdata.age_tx_ring[prod]; 1275 desc->addr = htole64(map->dm_segs[i].ds_addr); 1276 desc->len = 1277 htole32(AGE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 1278 desc->flags = htole32(cflags); 1279 sc->age_cdata.age_tx_cnt++; 1280 if (i == (nsegs - 1)) 1281 break; 1282 1283 /* sync this descriptor and go to the next one */ 1284 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 1285 prod * sizeof(struct tx_desc), sizeof(struct tx_desc), 1286 BUS_DMASYNC_PREWRITE); 1287 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1288 } 1289 1290 /* Set EOP on the last descriptor and sync it. */ 1291 desc->flags |= htole32(AGE_TD_EOP); 1292 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 1293 prod * sizeof(struct tx_desc), sizeof(struct tx_desc), 1294 BUS_DMASYNC_PREWRITE); 1295 1296 if (nsegs > 1) { 1297 /* Swap dmamap of the first and the last. */ 1298 txd = &sc->age_cdata.age_txdesc[prod]; 1299 map = txd_last->tx_dmamap; 1300 txd_last->tx_dmamap = txd->tx_dmamap; 1301 txd->tx_dmamap = map; 1302 txd->tx_m = m; 1303 KASSERT(txd_last->tx_m == NULL); 1304 } else { 1305 KASSERT(txd_last == &sc->age_cdata.age_txdesc[prod]); 1306 txd_last->tx_m = m; 1307 } 1308 1309 /* Update producer index. */ 1310 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1311 sc->age_cdata.age_tx_prod = prod; 1312 1313 return 0; 1314 } 1315 1316 static void 1317 age_txintr(struct age_softc *sc, int tpd_cons) 1318 { 1319 struct ifnet *ifp = &sc->sc_ec.ec_if; 1320 struct age_txdesc *txd; 1321 int cons, prog; 1322 1323 1324 if (sc->age_cdata.age_tx_cnt <= 0) { 1325 if (ifp->if_timer != 0) 1326 printf("timer running without packets\n"); 1327 if (sc->age_cdata.age_tx_cnt) 1328 printf("age_tx_cnt corrupted\n"); 1329 } 1330 1331 /* 1332 * Go through our Tx list and free mbufs for those 1333 * frames which have been transmitted. 1334 */ 1335 cons = sc->age_cdata.age_tx_cons; 1336 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 1337 if (sc->age_cdata.age_tx_cnt <= 0) 1338 break; 1339 prog++; 1340 ifp->if_flags &= ~IFF_OACTIVE; 1341 sc->age_cdata.age_tx_cnt--; 1342 txd = &sc->age_cdata.age_txdesc[cons]; 1343 /* 1344 * Clear Tx descriptors, it's not required but would 1345 * help debugging in case of Tx issues. 1346 */ 1347 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 1348 cons * sizeof(struct tx_desc), sizeof(struct tx_desc), 1349 BUS_DMASYNC_POSTWRITE); 1350 txd->tx_desc->addr = 0; 1351 txd->tx_desc->len = 0; 1352 txd->tx_desc->flags = 0; 1353 1354 if (txd->tx_m == NULL) 1355 continue; 1356 /* Reclaim transmitted mbufs. */ 1357 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1358 m_freem(txd->tx_m); 1359 txd->tx_m = NULL; 1360 } 1361 1362 if (prog > 0) { 1363 sc->age_cdata.age_tx_cons = cons; 1364 1365 /* 1366 * Unarm watchdog timer only when there are no pending 1367 * Tx descriptors in queue. 1368 */ 1369 if (sc->age_cdata.age_tx_cnt == 0) 1370 ifp->if_timer = 0; 1371 } 1372 } 1373 1374 /* Receive a frame. */ 1375 static void 1376 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 1377 { 1378 struct ifnet *ifp = &sc->sc_ec.ec_if; 1379 struct age_rxdesc *rxd; 1380 struct rx_desc *desc; 1381 struct mbuf *mp, *m; 1382 uint32_t status, index; 1383 int count, nsegs, pktlen; 1384 int rx_cons; 1385 1386 status = le32toh(rxrd->flags); 1387 index = le32toh(rxrd->index); 1388 rx_cons = AGE_RX_CONS(index); 1389 nsegs = AGE_RX_NSEGS(index); 1390 1391 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 1392 if ((status & AGE_RRD_ERROR) != 0 && 1393 (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 1394 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) { 1395 /* 1396 * We want to pass the following frames to upper 1397 * layer regardless of error status of Rx return 1398 * ring. 1399 * 1400 * o IP/TCP/UDP checksum is bad. 1401 * o frame length and protocol specific length 1402 * does not match. 1403 */ 1404 sc->age_cdata.age_rx_cons += nsegs; 1405 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1406 return; 1407 } 1408 1409 pktlen = 0; 1410 for (count = 0; count < nsegs; count++, 1411 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 1412 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 1413 mp = rxd->rx_m; 1414 desc = rxd->rx_desc; 1415 /* Add a new receive buffer to the ring. */ 1416 if (age_newbuf(sc, rxd, 0) != 0) { 1417 ifp->if_iqdrops++; 1418 /* Reuse Rx buffers. */ 1419 if (sc->age_cdata.age_rxhead != NULL) { 1420 m_freem(sc->age_cdata.age_rxhead); 1421 AGE_RXCHAIN_RESET(sc); 1422 } 1423 break; 1424 } 1425 1426 /* The length of the first mbuf is computed last. */ 1427 if (count != 0) { 1428 mp->m_len = AGE_RX_BYTES(le32toh(desc->len)); 1429 pktlen += mp->m_len; 1430 } 1431 1432 /* Chain received mbufs. */ 1433 if (sc->age_cdata.age_rxhead == NULL) { 1434 sc->age_cdata.age_rxhead = mp; 1435 sc->age_cdata.age_rxtail = mp; 1436 } else { 1437 mp->m_flags &= ~M_PKTHDR; 1438 sc->age_cdata.age_rxprev_tail = 1439 sc->age_cdata.age_rxtail; 1440 sc->age_cdata.age_rxtail->m_next = mp; 1441 sc->age_cdata.age_rxtail = mp; 1442 } 1443 1444 if (count == nsegs - 1) { 1445 /* 1446 * It seems that L1 controller has no way 1447 * to tell hardware to strip CRC bytes. 1448 */ 1449 sc->age_cdata.age_rxlen -= ETHER_CRC_LEN; 1450 if (nsegs > 1) { 1451 /* Remove the CRC bytes in chained mbufs. */ 1452 pktlen -= ETHER_CRC_LEN; 1453 if (mp->m_len <= ETHER_CRC_LEN) { 1454 sc->age_cdata.age_rxtail = 1455 sc->age_cdata.age_rxprev_tail; 1456 sc->age_cdata.age_rxtail->m_len -= 1457 (ETHER_CRC_LEN - mp->m_len); 1458 sc->age_cdata.age_rxtail->m_next = NULL; 1459 m_freem(mp); 1460 } else { 1461 mp->m_len -= ETHER_CRC_LEN; 1462 } 1463 } 1464 1465 m = sc->age_cdata.age_rxhead; 1466 m->m_flags |= M_PKTHDR; 1467 m->m_pkthdr.rcvif = ifp; 1468 m->m_pkthdr.len = sc->age_cdata.age_rxlen; 1469 /* Set the first mbuf length. */ 1470 m->m_len = sc->age_cdata.age_rxlen - pktlen; 1471 1472 /* 1473 * Set checksum information. 1474 * It seems that L1 controller can compute partial 1475 * checksum. The partial checksum value can be used 1476 * to accelerate checksum computation for fragmented 1477 * TCP/UDP packets. Upper network stack already 1478 * takes advantage of the partial checksum value in 1479 * IP reassembly stage. But I'm not sure the 1480 * correctness of the partial hardware checksum 1481 * assistance due to lack of data sheet. If it is 1482 * proven to work on L1 I'll enable it. 1483 */ 1484 if (status & AGE_RRD_IPV4) { 1485 if (status & AGE_RRD_IPCSUM_NOK) 1486 m->m_pkthdr.csum_flags |= 1487 M_CSUM_IPv4_BAD; 1488 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 1489 (status & AGE_RRD_TCP_UDPCSUM_NOK)) { 1490 m->m_pkthdr.csum_flags |= 1491 M_CSUM_TCP_UDP_BAD; 1492 } 1493 /* 1494 * Don't mark bad checksum for TCP/UDP frames 1495 * as fragmented frames may always have set 1496 * bad checksummed bit of descriptor status. 1497 */ 1498 } 1499 #if NVLAN > 0 1500 /* Check for VLAN tagged frames. */ 1501 if (status & AGE_RRD_VLAN) { 1502 uint32_t vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 1503 VLAN_INPUT_TAG(ifp, m, AGE_RX_VLAN_TAG(vtag), 1504 continue); 1505 } 1506 #endif 1507 1508 bpf_mtap(ifp, m); 1509 /* Pass it on. */ 1510 (*ifp->if_input)(ifp, m); 1511 1512 /* Reset mbuf chains. */ 1513 AGE_RXCHAIN_RESET(sc); 1514 } 1515 } 1516 1517 if (count != nsegs) { 1518 sc->age_cdata.age_rx_cons += nsegs; 1519 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1520 } else 1521 sc->age_cdata.age_rx_cons = rx_cons; 1522 } 1523 1524 static void 1525 age_rxintr(struct age_softc *sc, int rr_prod) 1526 { 1527 struct rx_rdesc *rxrd; 1528 int rr_cons, nsegs, pktlen, prog; 1529 1530 rr_cons = sc->age_cdata.age_rr_cons; 1531 if (rr_cons == rr_prod) 1532 return; 1533 1534 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1535 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1536 BUS_DMASYNC_POSTREAD); 1537 1538 for (prog = 0; rr_cons != rr_prod; prog++) { 1539 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 1540 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 1541 if (nsegs == 0) 1542 break; 1543 /* 1544 * Check number of segments against received bytes 1545 * Non-matching value would indicate that hardware 1546 * is still trying to update Rx return descriptors. 1547 * I'm not sure whether this check is really needed. 1548 */ 1549 pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 1550 if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) / 1551 (MCLBYTES - ETHER_ALIGN))) 1552 break; 1553 1554 /* Received a frame. */ 1555 age_rxeof(sc, rxrd); 1556 1557 /* Clear return ring. */ 1558 rxrd->index = 0; 1559 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 1560 } 1561 1562 if (prog > 0) { 1563 /* Update the consumer index. */ 1564 sc->age_cdata.age_rr_cons = rr_cons; 1565 1566 /* Sync descriptors. */ 1567 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1568 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1569 BUS_DMASYNC_PREWRITE); 1570 1571 /* Notify hardware availability of new Rx buffers. */ 1572 AGE_COMMIT_MBOX(sc); 1573 } 1574 } 1575 1576 static void 1577 age_tick(void *xsc) 1578 { 1579 struct age_softc *sc = xsc; 1580 struct mii_data *mii = &sc->sc_miibus; 1581 int s; 1582 1583 s = splnet(); 1584 mii_tick(mii); 1585 splx(s); 1586 1587 callout_schedule(&sc->sc_tick_ch, hz); 1588 } 1589 1590 static void 1591 age_reset(struct age_softc *sc) 1592 { 1593 uint32_t reg; 1594 int i; 1595 1596 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 1597 CSR_READ_4(sc, AGE_MASTER_CFG); 1598 DELAY(1000); 1599 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1600 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1601 break; 1602 DELAY(10); 1603 } 1604 1605 if (i == 0) 1606 printf("%s: reset timeout(0x%08x)!\n", device_xname(sc->sc_dev), 1607 reg); 1608 1609 /* Initialize PCIe module. From Linux. */ 1610 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1611 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1612 } 1613 1614 static int 1615 age_init(struct ifnet *ifp) 1616 { 1617 struct age_softc *sc = ifp->if_softc; 1618 struct mii_data *mii; 1619 uint8_t eaddr[ETHER_ADDR_LEN]; 1620 bus_addr_t paddr; 1621 uint32_t reg, fsize; 1622 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 1623 int error; 1624 1625 /* 1626 * Cancel any pending I/O. 1627 */ 1628 age_stop(ifp, 0); 1629 1630 /* 1631 * Reset the chip to a known state. 1632 */ 1633 age_reset(sc); 1634 1635 /* Initialize descriptors. */ 1636 error = age_init_rx_ring(sc); 1637 if (error != 0) { 1638 printf("%s: no memory for Rx buffers.\n", device_xname(sc->sc_dev)); 1639 age_stop(ifp, 0); 1640 return error; 1641 } 1642 age_init_rr_ring(sc); 1643 age_init_tx_ring(sc); 1644 age_init_cmb_block(sc); 1645 age_init_smb_block(sc); 1646 1647 /* Reprogram the station address. */ 1648 memcpy(eaddr, CLLADDR(ifp->if_sadl), sizeof(eaddr)); 1649 CSR_WRITE_4(sc, AGE_PAR0, 1650 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1651 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 1652 1653 /* Set descriptor base addresses. */ 1654 paddr = sc->age_rdata.age_tx_ring_paddr; 1655 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 1656 paddr = sc->age_rdata.age_rx_ring_paddr; 1657 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 1658 paddr = sc->age_rdata.age_rr_ring_paddr; 1659 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 1660 paddr = sc->age_rdata.age_tx_ring_paddr; 1661 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 1662 paddr = sc->age_rdata.age_cmb_block_paddr; 1663 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1664 paddr = sc->age_rdata.age_smb_block_paddr; 1665 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1666 1667 /* Set Rx/Rx return descriptor counter. */ 1668 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 1669 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 1670 DESC_RRD_CNT_MASK) | 1671 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 1672 1673 /* Set Tx descriptor counter. */ 1674 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 1675 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 1676 1677 /* Tell hardware that we're ready to load descriptors. */ 1678 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 1679 1680 /* 1681 * Initialize mailbox register. 1682 * Updated producer/consumer index information is exchanged 1683 * through this mailbox register. However Tx producer and 1684 * Rx return consumer/Rx producer are all shared such that 1685 * it's hard to separate code path between Tx and Rx without 1686 * locking. If L1 hardware have a separate mail box register 1687 * for Tx and Rx consumer/producer management we could have 1688 * indepent Tx/Rx handler which in turn Rx handler could have 1689 * been run without any locking. 1690 */ 1691 AGE_COMMIT_MBOX(sc); 1692 1693 /* Configure IPG/IFG parameters. */ 1694 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 1695 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 1696 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1697 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1698 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 1699 1700 /* Set parameters for half-duplex media. */ 1701 CSR_WRITE_4(sc, AGE_HDPX_CFG, 1702 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1703 HDPX_CFG_LCOL_MASK) | 1704 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1705 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1706 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1707 HDPX_CFG_ABEBT_MASK) | 1708 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1709 HDPX_CFG_JAMIPG_MASK)); 1710 1711 /* Configure interrupt moderation timer. */ 1712 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 1713 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 1714 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 1715 reg &= ~MASTER_MTIMER_ENB; 1716 if (AGE_USECS(sc->age_int_mod) == 0) 1717 reg &= ~MASTER_ITIMER_ENB; 1718 else 1719 reg |= MASTER_ITIMER_ENB; 1720 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 1721 if (agedebug) 1722 printf("%s: interrupt moderation is %d us.\n", 1723 device_xname(sc->sc_dev), sc->age_int_mod); 1724 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 1725 1726 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 1727 if (ifp->if_mtu < ETHERMTU) 1728 sc->age_max_frame_size = ETHERMTU; 1729 else 1730 sc->age_max_frame_size = ifp->if_mtu; 1731 sc->age_max_frame_size += ETHER_HDR_LEN + 1732 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 1733 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 1734 1735 /* Configure jumbo frame. */ 1736 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 1737 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 1738 (((fsize / sizeof(uint64_t)) << 1739 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 1740 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 1741 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 1742 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 1743 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 1744 1745 /* Configure flow-control parameters. From Linux. */ 1746 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 1747 /* 1748 * Magic workaround for old-L1. 1749 * Don't know which hw revision requires this magic. 1750 */ 1751 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1752 /* 1753 * Another magic workaround for flow-control mode 1754 * change. From Linux. 1755 */ 1756 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1757 } 1758 /* 1759 * TODO 1760 * Should understand pause parameter relationships between FIFO 1761 * size and number of Rx descriptors and Rx return descriptors. 1762 * 1763 * Magic parameters came from Linux. 1764 */ 1765 switch (sc->age_chip_rev) { 1766 case 0x8001: 1767 case 0x9001: 1768 case 0x9002: 1769 case 0x9003: 1770 rxf_hi = AGE_RX_RING_CNT / 16; 1771 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 1772 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 1773 rrd_lo = AGE_RR_RING_CNT / 16; 1774 break; 1775 default: 1776 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 1777 rxf_lo = reg / 16; 1778 if (rxf_lo < 192) 1779 rxf_lo = 192; 1780 rxf_hi = (reg * 7) / 8; 1781 if (rxf_hi < rxf_lo) 1782 rxf_hi = rxf_lo + 16; 1783 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 1784 rrd_lo = reg / 8; 1785 rrd_hi = (reg * 7) / 8; 1786 if (rrd_lo < 2) 1787 rrd_lo = 2; 1788 if (rrd_hi < rrd_lo) 1789 rrd_hi = rrd_lo + 3; 1790 break; 1791 } 1792 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 1793 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 1794 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 1795 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 1796 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 1797 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 1798 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 1799 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 1800 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 1801 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 1802 1803 /* Configure RxQ. */ 1804 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1805 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 1806 RXQ_CFG_RD_BURST_MASK) | 1807 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 1808 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 1809 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 1810 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 1811 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1812 1813 /* Configure TxQ. */ 1814 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1815 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1816 TXQ_CFG_TPD_BURST_MASK) | 1817 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 1818 TXQ_CFG_TX_FIFO_BURST_MASK) | 1819 ((TXQ_CFG_TPD_FETCH_DEFAULT << 1820 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 1821 TXQ_CFG_ENB); 1822 1823 /* Configure DMA parameters. */ 1824 CSR_WRITE_4(sc, AGE_DMA_CFG, 1825 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 1826 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 1827 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 1828 1829 /* Configure CMB DMA write threshold. */ 1830 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 1831 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 1832 CMB_WR_THRESH_RRD_MASK) | 1833 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 1834 CMB_WR_THRESH_TPD_MASK)); 1835 1836 /* Set CMB/SMB timer and enable them. */ 1837 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 1838 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 1839 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 1840 1841 /* Request SMB updates for every seconds. */ 1842 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 1843 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 1844 1845 /* 1846 * Disable all WOL bits as WOL can interfere normal Rx 1847 * operation. 1848 */ 1849 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1850 1851 /* 1852 * Configure Tx/Rx MACs. 1853 * - Auto-padding for short frames. 1854 * - Enable CRC generation. 1855 * Start with full-duplex/1000Mbps media. Actual reconfiguration 1856 * of MAC is followed after link establishment. 1857 */ 1858 CSR_WRITE_4(sc, AGE_MAC_CFG, 1859 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 1860 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 1861 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1862 MAC_CFG_PREAMBLE_MASK)); 1863 1864 /* Set up the receive filter. */ 1865 age_rxfilter(sc); 1866 age_rxvlan(sc); 1867 1868 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1869 reg |= MAC_CFG_RXCSUM_ENB; 1870 1871 /* Ack all pending interrupts and clear it. */ 1872 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 1873 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 1874 1875 /* Finally enable Tx/Rx MAC. */ 1876 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 1877 1878 sc->age_flags &= ~AGE_FLAG_LINK; 1879 1880 /* Switch to the current media. */ 1881 mii = &sc->sc_miibus; 1882 mii_mediachg(mii); 1883 1884 callout_schedule(&sc->sc_tick_ch, hz); 1885 1886 ifp->if_flags |= IFF_RUNNING; 1887 ifp->if_flags &= ~IFF_OACTIVE; 1888 1889 return 0; 1890 } 1891 1892 static void 1893 age_stop(struct ifnet *ifp, int disable) 1894 { 1895 struct age_softc *sc = ifp->if_softc; 1896 struct age_txdesc *txd; 1897 struct age_rxdesc *rxd; 1898 uint32_t reg; 1899 int i; 1900 1901 callout_stop(&sc->sc_tick_ch); 1902 1903 /* 1904 * Mark the interface down and cancel the watchdog timer. 1905 */ 1906 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1907 ifp->if_timer = 0; 1908 1909 sc->age_flags &= ~AGE_FLAG_LINK; 1910 1911 mii_down(&sc->sc_miibus); 1912 1913 /* 1914 * Disable interrupts. 1915 */ 1916 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 1917 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 1918 1919 /* Stop CMB/SMB updates. */ 1920 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 1921 1922 /* Stop Rx/Tx MAC. */ 1923 age_stop_rxmac(sc); 1924 age_stop_txmac(sc); 1925 1926 /* Stop DMA. */ 1927 CSR_WRITE_4(sc, AGE_DMA_CFG, 1928 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 1929 1930 /* Stop TxQ/RxQ. */ 1931 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1932 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 1933 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1934 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 1935 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1936 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1937 break; 1938 DELAY(10); 1939 } 1940 if (i == 0) 1941 printf("%s: stopping Rx/Tx MACs timed out(0x%08x)!\n", 1942 device_xname(sc->sc_dev), reg); 1943 1944 /* Reclaim Rx buffers that have been processed. */ 1945 if (sc->age_cdata.age_rxhead != NULL) 1946 m_freem(sc->age_cdata.age_rxhead); 1947 AGE_RXCHAIN_RESET(sc); 1948 1949 /* 1950 * Free RX and TX mbufs still in the queues. 1951 */ 1952 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1953 rxd = &sc->age_cdata.age_rxdesc[i]; 1954 if (rxd->rx_m != NULL) { 1955 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1956 m_freem(rxd->rx_m); 1957 rxd->rx_m = NULL; 1958 } 1959 } 1960 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1961 txd = &sc->age_cdata.age_txdesc[i]; 1962 if (txd->tx_m != NULL) { 1963 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1964 m_freem(txd->tx_m); 1965 txd->tx_m = NULL; 1966 } 1967 } 1968 } 1969 1970 static void 1971 age_stats_update(struct age_softc *sc) 1972 { 1973 struct ifnet *ifp = &sc->sc_ec.ec_if; 1974 struct age_stats *stat; 1975 struct smb *smb; 1976 1977 stat = &sc->age_stat; 1978 1979 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 1980 sc->age_cdata.age_smb_block_map->dm_mapsize, 1981 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1982 1983 smb = sc->age_rdata.age_smb_block; 1984 if (smb->updated == 0) 1985 return; 1986 1987 /* Rx stats. */ 1988 stat->rx_frames += smb->rx_frames; 1989 stat->rx_bcast_frames += smb->rx_bcast_frames; 1990 stat->rx_mcast_frames += smb->rx_mcast_frames; 1991 stat->rx_pause_frames += smb->rx_pause_frames; 1992 stat->rx_control_frames += smb->rx_control_frames; 1993 stat->rx_crcerrs += smb->rx_crcerrs; 1994 stat->rx_lenerrs += smb->rx_lenerrs; 1995 stat->rx_bytes += smb->rx_bytes; 1996 stat->rx_runts += smb->rx_runts; 1997 stat->rx_fragments += smb->rx_fragments; 1998 stat->rx_pkts_64 += smb->rx_pkts_64; 1999 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2000 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2001 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2002 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2003 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2004 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2005 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2006 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2007 stat->rx_desc_oflows += smb->rx_desc_oflows; 2008 stat->rx_alignerrs += smb->rx_alignerrs; 2009 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2010 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2011 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2012 2013 /* Tx stats. */ 2014 stat->tx_frames += smb->tx_frames; 2015 stat->tx_bcast_frames += smb->tx_bcast_frames; 2016 stat->tx_mcast_frames += smb->tx_mcast_frames; 2017 stat->tx_pause_frames += smb->tx_pause_frames; 2018 stat->tx_excess_defer += smb->tx_excess_defer; 2019 stat->tx_control_frames += smb->tx_control_frames; 2020 stat->tx_deferred += smb->tx_deferred; 2021 stat->tx_bytes += smb->tx_bytes; 2022 stat->tx_pkts_64 += smb->tx_pkts_64; 2023 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2024 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2025 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2026 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2027 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2028 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2029 stat->tx_single_colls += smb->tx_single_colls; 2030 stat->tx_multi_colls += smb->tx_multi_colls; 2031 stat->tx_late_colls += smb->tx_late_colls; 2032 stat->tx_excess_colls += smb->tx_excess_colls; 2033 stat->tx_underrun += smb->tx_underrun; 2034 stat->tx_desc_underrun += smb->tx_desc_underrun; 2035 stat->tx_lenerrs += smb->tx_lenerrs; 2036 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2037 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2038 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2039 2040 /* Update counters in ifnet. */ 2041 ifp->if_opackets += smb->tx_frames; 2042 2043 ifp->if_collisions += smb->tx_single_colls + 2044 smb->tx_multi_colls + smb->tx_late_colls + 2045 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 2046 2047 ifp->if_oerrors += smb->tx_excess_colls + 2048 smb->tx_late_colls + smb->tx_underrun + 2049 smb->tx_pkts_truncated; 2050 2051 ifp->if_ipackets += smb->rx_frames; 2052 2053 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2054 smb->rx_runts + smb->rx_pkts_truncated + 2055 smb->rx_fifo_oflows + smb->rx_desc_oflows + 2056 smb->rx_alignerrs; 2057 2058 /* Update done, clear. */ 2059 smb->updated = 0; 2060 2061 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2062 sc->age_cdata.age_smb_block_map->dm_mapsize, 2063 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2064 } 2065 2066 static void 2067 age_stop_txmac(struct age_softc *sc) 2068 { 2069 uint32_t reg; 2070 int i; 2071 2072 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2073 if ((reg & MAC_CFG_TX_ENB) != 0) { 2074 reg &= ~MAC_CFG_TX_ENB; 2075 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2076 } 2077 /* Stop Tx DMA engine. */ 2078 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2079 if ((reg & DMA_CFG_RD_ENB) != 0) { 2080 reg &= ~DMA_CFG_RD_ENB; 2081 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2082 } 2083 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2084 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2085 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2086 break; 2087 DELAY(10); 2088 } 2089 if (i == 0) 2090 printf("%s: stopping TxMAC timeout!\n", device_xname(sc->sc_dev)); 2091 } 2092 2093 static void 2094 age_stop_rxmac(struct age_softc *sc) 2095 { 2096 uint32_t reg; 2097 int i; 2098 2099 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2100 if ((reg & MAC_CFG_RX_ENB) != 0) { 2101 reg &= ~MAC_CFG_RX_ENB; 2102 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2103 } 2104 /* Stop Rx DMA engine. */ 2105 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2106 if ((reg & DMA_CFG_WR_ENB) != 0) { 2107 reg &= ~DMA_CFG_WR_ENB; 2108 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2109 } 2110 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2111 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2112 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2113 break; 2114 DELAY(10); 2115 } 2116 if (i == 0) 2117 printf("%s: stopping RxMAC timeout!\n", device_xname(sc->sc_dev)); 2118 } 2119 2120 static void 2121 age_init_tx_ring(struct age_softc *sc) 2122 { 2123 struct age_ring_data *rd; 2124 struct age_txdesc *txd; 2125 int i; 2126 2127 sc->age_cdata.age_tx_prod = 0; 2128 sc->age_cdata.age_tx_cons = 0; 2129 sc->age_cdata.age_tx_cnt = 0; 2130 2131 rd = &sc->age_rdata; 2132 memset(rd->age_tx_ring, 0, AGE_TX_RING_SZ); 2133 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2134 txd = &sc->age_cdata.age_txdesc[i]; 2135 txd->tx_desc = &rd->age_tx_ring[i]; 2136 txd->tx_m = NULL; 2137 } 2138 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 2139 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2140 } 2141 2142 static int 2143 age_init_rx_ring(struct age_softc *sc) 2144 { 2145 struct age_ring_data *rd; 2146 struct age_rxdesc *rxd; 2147 int i; 2148 2149 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 2150 rd = &sc->age_rdata; 2151 memset(rd->age_rx_ring, 0, AGE_RX_RING_SZ); 2152 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2153 rxd = &sc->age_cdata.age_rxdesc[i]; 2154 rxd->rx_m = NULL; 2155 rxd->rx_desc = &rd->age_rx_ring[i]; 2156 if (age_newbuf(sc, rxd, 1) != 0) 2157 return ENOBUFS; 2158 } 2159 2160 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 0, 2161 sc->age_cdata.age_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2162 2163 return 0; 2164 } 2165 2166 static void 2167 age_init_rr_ring(struct age_softc *sc) 2168 { 2169 struct age_ring_data *rd; 2170 2171 sc->age_cdata.age_rr_cons = 0; 2172 AGE_RXCHAIN_RESET(sc); 2173 2174 rd = &sc->age_rdata; 2175 memset(rd->age_rr_ring, 0, AGE_RR_RING_SZ); 2176 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 2177 sc->age_cdata.age_rr_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2178 } 2179 2180 static void 2181 age_init_cmb_block(struct age_softc *sc) 2182 { 2183 struct age_ring_data *rd; 2184 2185 rd = &sc->age_rdata; 2186 memset(rd->age_cmb_block, 0, AGE_CMB_BLOCK_SZ); 2187 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 2188 sc->age_cdata.age_cmb_block_map->dm_mapsize, 2189 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2190 } 2191 2192 static void 2193 age_init_smb_block(struct age_softc *sc) 2194 { 2195 struct age_ring_data *rd; 2196 2197 rd = &sc->age_rdata; 2198 memset(rd->age_smb_block, 0, AGE_SMB_BLOCK_SZ); 2199 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2200 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2201 } 2202 2203 static int 2204 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd, int init) 2205 { 2206 struct rx_desc *desc; 2207 struct mbuf *m; 2208 bus_dmamap_t map; 2209 int error; 2210 2211 MGETHDR(m, M_DONTWAIT, MT_DATA); 2212 if (m == NULL) 2213 return ENOBUFS; 2214 MCLGET(m, M_DONTWAIT); 2215 if (!(m->m_flags & M_EXT)) { 2216 m_freem(m); 2217 return ENOBUFS; 2218 } 2219 2220 m->m_len = m->m_pkthdr.len = MCLBYTES; 2221 m_adj(m, ETHER_ALIGN); 2222 2223 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2224 sc->age_cdata.age_rx_sparemap, m, BUS_DMA_NOWAIT); 2225 2226 if (error != 0) { 2227 if (!error) { 2228 bus_dmamap_unload(sc->sc_dmat, 2229 sc->age_cdata.age_rx_sparemap); 2230 error = EFBIG; 2231 printf("%s: too many segments?!\n", 2232 device_xname(sc->sc_dev)); 2233 } 2234 m_freem(m); 2235 2236 if (init) 2237 printf("%s: can't load RX mbuf\n", device_xname(sc->sc_dev)); 2238 return error; 2239 } 2240 2241 if (rxd->rx_m != NULL) { 2242 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2243 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2244 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2245 } 2246 map = rxd->rx_dmamap; 2247 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 2248 sc->age_cdata.age_rx_sparemap = map; 2249 rxd->rx_m = m; 2250 2251 desc = rxd->rx_desc; 2252 desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 2253 desc->len = 2254 htole32((rxd->rx_dmamap->dm_segs[0].ds_len & AGE_RD_LEN_MASK) << 2255 AGE_RD_LEN_SHIFT); 2256 2257 return 0; 2258 } 2259 2260 static void 2261 age_rxvlan(struct age_softc *sc) 2262 { 2263 uint32_t reg; 2264 2265 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2266 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2267 if (sc->sc_ec.ec_capenable & ETHERCAP_VLAN_HWTAGGING) 2268 reg |= MAC_CFG_VLAN_TAG_STRIP; 2269 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2270 } 2271 2272 static void 2273 age_rxfilter(struct age_softc *sc) 2274 { 2275 struct ethercom *ec = &sc->sc_ec; 2276 struct ifnet *ifp = &sc->sc_ec.ec_if; 2277 struct ether_multi *enm; 2278 struct ether_multistep step; 2279 uint32_t crc; 2280 uint32_t mchash[2]; 2281 uint32_t rxcfg; 2282 2283 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 2284 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2285 ifp->if_flags &= ~IFF_ALLMULTI; 2286 2287 /* 2288 * Always accept broadcast frames. 2289 */ 2290 rxcfg |= MAC_CFG_BCAST; 2291 2292 if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 2293 ifp->if_flags |= IFF_ALLMULTI; 2294 if (ifp->if_flags & IFF_PROMISC) 2295 rxcfg |= MAC_CFG_PROMISC; 2296 else 2297 rxcfg |= MAC_CFG_ALLMULTI; 2298 mchash[0] = mchash[1] = 0xFFFFFFFF; 2299 } else { 2300 /* Program new filter. */ 2301 memset(mchash, 0, sizeof(mchash)); 2302 2303 ETHER_FIRST_MULTI(step, ec, enm); 2304 while (enm != NULL) { 2305 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2306 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2307 ETHER_NEXT_MULTI(step, enm); 2308 } 2309 } 2310 2311 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 2312 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 2313 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 2314 } 2315
Indexes created Mon Sep 29 21:09:56 GMT 2025