if_age.c revision 1.51.2.4
1 /* $NetBSD: if_age.c,v 1.51.2.4 2019/01/26 22:00:07 pgoyette Exp $ */ 2 /* $OpenBSD: if_age.c,v 1.1 2009/01/16 05:00:34 kevlo Exp $ */ 3 4 /*- 5 * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: if_age.c,v 1.51.2.4 2019/01/26 22:00:07 pgoyette Exp $"); 35 36 #include "vlan.h" 37 38 #include <sys/param.h> 39 #include <sys/proc.h> 40 #include <sys/endian.h> 41 #include <sys/systm.h> 42 #include <sys/types.h> 43 #include <sys/sockio.h> 44 #include <sys/mbuf.h> 45 #include <sys/queue.h> 46 #include <sys/kernel.h> 47 #include <sys/device.h> 48 #include <sys/callout.h> 49 #include <sys/socket.h> 50 51 #include <net/if.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 #include <net/if_ether.h> 55 56 #ifdef INET 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <netinet/ip.h> 61 #endif 62 63 #include <net/if_types.h> 64 #include <net/if_vlanvar.h> 65 66 #include <net/bpf.h> 67 68 #include <dev/mii/mii.h> 69 #include <dev/mii/miivar.h> 70 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcivar.h> 73 #include <dev/pci/pcidevs.h> 74 75 #include <dev/pci/if_agereg.h> 76 77 static int age_match(device_t, cfdata_t, void *); 78 static void age_attach(device_t, device_t, void *); 79 static int age_detach(device_t, int); 80 81 static bool age_resume(device_t, const pmf_qual_t *); 82 83 static int age_miibus_readreg(device_t, int, int, uint16_t *); 84 static int age_miibus_writereg(device_t, int, int, uint16_t); 85 static void age_miibus_statchg(struct ifnet *); 86 87 static int age_init(struct ifnet *); 88 static int age_ioctl(struct ifnet *, u_long, void *); 89 static void age_start(struct ifnet *); 90 static void age_watchdog(struct ifnet *); 91 static bool age_shutdown(device_t, int); 92 static void age_mediastatus(struct ifnet *, struct ifmediareq *); 93 static int age_mediachange(struct ifnet *); 94 95 static int age_intr(void *); 96 static int age_dma_alloc(struct age_softc *); 97 static void age_dma_free(struct age_softc *); 98 static void age_get_macaddr(struct age_softc *, uint8_t[]); 99 static void age_phy_reset(struct age_softc *); 100 101 static int age_encap(struct age_softc *, struct mbuf **); 102 static void age_init_tx_ring(struct age_softc *); 103 static int age_init_rx_ring(struct age_softc *); 104 static void age_init_rr_ring(struct age_softc *); 105 static void age_init_cmb_block(struct age_softc *); 106 static void age_init_smb_block(struct age_softc *); 107 static int age_newbuf(struct age_softc *, struct age_rxdesc *, int); 108 static void age_mac_config(struct age_softc *); 109 static void age_txintr(struct age_softc *, int); 110 static void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 111 static void age_rxintr(struct age_softc *, int); 112 static void age_tick(void *); 113 static void age_reset(struct age_softc *); 114 static void age_stop(struct ifnet *, int); 115 static void age_stats_update(struct age_softc *); 116 static void age_stop_txmac(struct age_softc *); 117 static void age_stop_rxmac(struct age_softc *); 118 static void age_rxvlan(struct age_softc *sc); 119 static void age_rxfilter(struct age_softc *); 120 121 CFATTACH_DECL_NEW(age, sizeof(struct age_softc), 122 age_match, age_attach, age_detach, NULL); 123 124 int agedebug = 0; 125 #define DPRINTF(x) do { if (agedebug) printf x; } while (0) 126 127 #define ETHER_ALIGN 2 128 #define AGE_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 129 130 static int 131 age_match(device_t dev, cfdata_t match, void *aux) 132 { 133 struct pci_attach_args *pa = aux; 134 135 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && 136 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_GIGA); 137 } 138 139 static void 140 age_attach(device_t parent, device_t self, void *aux) 141 { 142 struct age_softc *sc = device_private(self); 143 struct pci_attach_args *pa = aux; 144 pci_intr_handle_t ih; 145 const char *intrstr; 146 struct ifnet *ifp = &sc->sc_ec.ec_if; 147 pcireg_t memtype; 148 int error = 0; 149 char intrbuf[PCI_INTRSTR_LEN]; 150 151 aprint_naive("\n"); 152 aprint_normal(": Attansic/Atheros L1 Gigabit Ethernet\n"); 153 154 sc->sc_dev = self; 155 sc->sc_dmat = pa->pa_dmat; 156 sc->sc_pct = pa->pa_pc; 157 sc->sc_pcitag = pa->pa_tag; 158 159 /* 160 * Allocate IO memory 161 */ 162 memtype = pci_mapreg_type(sc->sc_pct, sc->sc_pcitag, AGE_PCIR_BAR); 163 switch (memtype) { 164 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 165 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 166 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 167 break; 168 default: 169 aprint_error_dev(self, "invalid base address register\n"); 170 break; 171 } 172 173 if (pci_mapreg_map(pa, AGE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 174 &sc->sc_mem_bh, NULL, &sc->sc_mem_size) != 0) { 175 aprint_error_dev(self, "could not map mem space\n"); 176 return; 177 } 178 179 if (pci_intr_map(pa, &ih) != 0) { 180 aprint_error_dev(self, "could not map interrupt\n"); 181 goto fail; 182 } 183 184 /* 185 * Allocate IRQ 186 */ 187 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf)); 188 sc->sc_irq_handle = pci_intr_establish_xname(sc->sc_pct, ih, IPL_NET, 189 age_intr, sc, device_xname(self)); 190 if (sc->sc_irq_handle == NULL) { 191 aprint_error_dev(self, "could not establish interrupt"); 192 if (intrstr != NULL) 193 aprint_error(" at %s", intrstr); 194 aprint_error("\n"); 195 goto fail; 196 } 197 aprint_normal_dev(self, "%s\n", intrstr); 198 199 /* Set PHY address. */ 200 sc->age_phyaddr = AGE_PHY_ADDR; 201 202 /* Reset PHY. */ 203 age_phy_reset(sc); 204 205 /* Reset the ethernet controller. */ 206 age_reset(sc); 207 208 /* Get PCI and chip id/revision. */ 209 sc->age_rev = PCI_REVISION(pa->pa_class); 210 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 211 MASTER_CHIP_REV_SHIFT; 212 213 aprint_debug_dev(self, "PCI device revision : 0x%04x\n", sc->age_rev); 214 aprint_debug_dev(self, "Chip id/revision : 0x%04x\n", sc->age_chip_rev); 215 216 if (agedebug) { 217 aprint_debug_dev(self, "%d Tx FIFO, %d Rx FIFO\n", 218 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 219 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 220 } 221 222 /* Set max allowable DMA size. */ 223 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 224 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 225 226 /* Allocate DMA stuffs */ 227 error = age_dma_alloc(sc); 228 if (error) 229 goto fail; 230 231 callout_init(&sc->sc_tick_ch, 0); 232 callout_setfunc(&sc->sc_tick_ch, age_tick, sc); 233 234 /* Load station address. */ 235 age_get_macaddr(sc, sc->sc_enaddr); 236 237 aprint_normal_dev(self, "Ethernet address %s\n", 238 ether_sprintf(sc->sc_enaddr)); 239 240 ifp->if_softc = sc; 241 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 242 ifp->if_init = age_init; 243 ifp->if_ioctl = age_ioctl; 244 ifp->if_start = age_start; 245 ifp->if_stop = age_stop; 246 ifp->if_watchdog = age_watchdog; 247 ifp->if_baudrate = IF_Gbps(1); 248 IFQ_SET_MAXLEN(&ifp->if_snd, AGE_TX_RING_CNT - 1); 249 IFQ_SET_READY(&ifp->if_snd); 250 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 251 252 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 253 254 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Rx | 255 IFCAP_CSUM_TCPv4_Rx | 256 IFCAP_CSUM_UDPv4_Rx; 257 #ifdef AGE_CHECKSUM 258 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | 259 IFCAP_CSUM_TCPv4_Tx | 260 IFCAP_CSUM_UDPv4_Tx; 261 #endif 262 263 #if NVLAN > 0 264 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 265 #endif 266 267 /* Set up MII bus. */ 268 sc->sc_miibus.mii_ifp = ifp; 269 sc->sc_miibus.mii_readreg = age_miibus_readreg; 270 sc->sc_miibus.mii_writereg = age_miibus_writereg; 271 sc->sc_miibus.mii_statchg = age_miibus_statchg; 272 273 sc->sc_ec.ec_mii = &sc->sc_miibus; 274 ifmedia_init(&sc->sc_miibus.mii_media, 0, age_mediachange, 275 age_mediastatus); 276 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 277 MII_OFFSET_ANY, MIIF_DOPAUSE); 278 279 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 280 aprint_error_dev(self, "no PHY found!\n"); 281 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 282 0, NULL); 283 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 284 } else 285 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 286 287 if_attach(ifp); 288 if_deferred_start_init(ifp, NULL); 289 ether_ifattach(ifp, sc->sc_enaddr); 290 291 if (pmf_device_register1(self, NULL, age_resume, age_shutdown)) 292 pmf_class_network_register(self, ifp); 293 else 294 aprint_error_dev(self, "couldn't establish power handler\n"); 295 296 return; 297 298 fail: 299 age_dma_free(sc); 300 if (sc->sc_irq_handle != NULL) { 301 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 302 sc->sc_irq_handle = NULL; 303 } 304 if (sc->sc_mem_size) { 305 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 306 sc->sc_mem_size = 0; 307 } 308 } 309 310 static int 311 age_detach(device_t self, int flags) 312 { 313 struct age_softc *sc = device_private(self); 314 struct ifnet *ifp = &sc->sc_ec.ec_if; 315 int s; 316 317 pmf_device_deregister(self); 318 s = splnet(); 319 age_stop(ifp, 0); 320 splx(s); 321 322 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 323 324 /* Delete all remaining media. */ 325 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 326 327 ether_ifdetach(ifp); 328 if_detach(ifp); 329 age_dma_free(sc); 330 331 if (sc->sc_irq_handle != NULL) { 332 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 333 sc->sc_irq_handle = NULL; 334 } 335 if (sc->sc_mem_size) { 336 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 337 sc->sc_mem_size = 0; 338 } 339 return 0; 340 } 341 342 /* 343 * Read a PHY register on the MII of the L1. 344 */ 345 static int 346 age_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 347 { 348 struct age_softc *sc = device_private(dev); 349 uint32_t v; 350 int i; 351 352 if (phy != sc->age_phyaddr) 353 return -1; 354 355 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 356 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 357 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 358 DELAY(1); 359 v = CSR_READ_4(sc, AGE_MDIO); 360 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 361 break; 362 } 363 364 if (i == 0) { 365 printf("%s: phy read timeout: phy %d, reg %d\n", 366 device_xname(sc->sc_dev), phy, reg); 367 return ETIMEDOUT; 368 } 369 370 *val = (v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT; 371 return 0; 372 } 373 374 /* 375 * Write a PHY register on the MII of the L1. 376 */ 377 static int 378 age_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 379 { 380 struct age_softc *sc = device_private(dev); 381 uint32_t v; 382 int i; 383 384 if (phy != sc->age_phyaddr) 385 return -1; 386 387 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 388 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 389 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 390 391 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 392 DELAY(1); 393 v = CSR_READ_4(sc, AGE_MDIO); 394 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 395 break; 396 } 397 398 if (i == 0) { 399 printf("%s: phy write timeout: phy %d, reg %d\n", 400 device_xname(sc->sc_dev), phy, reg); 401 return ETIMEDOUT; 402 } 403 404 return 0; 405 } 406 407 /* 408 * Callback from MII layer when media changes. 409 */ 410 static void 411 age_miibus_statchg(struct ifnet *ifp) 412 { 413 struct age_softc *sc = ifp->if_softc; 414 struct mii_data *mii = &sc->sc_miibus; 415 416 if ((ifp->if_flags & IFF_RUNNING) == 0) 417 return; 418 419 sc->age_flags &= ~AGE_FLAG_LINK; 420 if ((mii->mii_media_status & IFM_AVALID) != 0) { 421 switch (IFM_SUBTYPE(mii->mii_media_active)) { 422 case IFM_10_T: 423 case IFM_100_TX: 424 case IFM_1000_T: 425 sc->age_flags |= AGE_FLAG_LINK; 426 break; 427 default: 428 break; 429 } 430 } 431 432 /* Stop Rx/Tx MACs. */ 433 age_stop_rxmac(sc); 434 age_stop_txmac(sc); 435 436 /* Program MACs with resolved speed/duplex/flow-control. */ 437 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 438 uint32_t reg; 439 440 age_mac_config(sc); 441 reg = CSR_READ_4(sc, AGE_MAC_CFG); 442 /* Restart DMA engine and Tx/Rx MAC. */ 443 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 444 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 445 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 446 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 447 } 448 } 449 450 /* 451 * Get the current interface media status. 452 */ 453 static void 454 age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 455 { 456 struct age_softc *sc = ifp->if_softc; 457 struct mii_data *mii = &sc->sc_miibus; 458 459 mii_pollstat(mii); 460 ifmr->ifm_status = mii->mii_media_status; 461 ifmr->ifm_active = mii->mii_media_active; 462 } 463 464 /* 465 * Set hardware to newly-selected media. 466 */ 467 static int 468 age_mediachange(struct ifnet *ifp) 469 { 470 struct age_softc *sc = ifp->if_softc; 471 struct mii_data *mii = &sc->sc_miibus; 472 int error; 473 474 if (mii->mii_instance != 0) { 475 struct mii_softc *miisc; 476 477 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 478 mii_phy_reset(miisc); 479 } 480 error = mii_mediachg(mii); 481 482 return error; 483 } 484 485 static int 486 age_intr(void *arg) 487 { 488 struct age_softc *sc = arg; 489 struct ifnet *ifp = &sc->sc_ec.ec_if; 490 struct cmb *cmb; 491 uint32_t status; 492 493 status = CSR_READ_4(sc, AGE_INTR_STATUS); 494 if (status == 0 || (status & AGE_INTRS) == 0) 495 return 0; 496 497 cmb = sc->age_rdata.age_cmb_block; 498 if (cmb == NULL) { 499 /* Happens when bringing up the interface 500 * w/o having a carrier. Ack the interrupt. 501 */ 502 CSR_WRITE_4(sc, AGE_INTR_STATUS, status); 503 return 0; 504 } 505 506 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 507 sc->age_cdata.age_cmb_block_map->dm_mapsize, 508 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 509 status = le32toh(cmb->intr_status); 510 /* ACK/reenable interrupts */ 511 CSR_WRITE_4(sc, AGE_INTR_STATUS, status); 512 while ((status & AGE_INTRS) != 0) { 513 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 514 TPD_CONS_SHIFT; 515 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 516 RRD_PROD_SHIFT; 517 518 /* Let hardware know CMB was served. */ 519 cmb->intr_status = 0; 520 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 521 sc->age_cdata.age_cmb_block_map->dm_mapsize, 522 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 523 524 if (ifp->if_flags & IFF_RUNNING) { 525 if (status & INTR_CMB_RX) 526 age_rxintr(sc, sc->age_rr_prod); 527 528 if (status & INTR_CMB_TX) 529 age_txintr(sc, sc->age_tpd_cons); 530 531 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 532 if (status & INTR_DMA_RD_TO_RST) 533 printf("%s: DMA read error! -- " 534 "resetting\n", 535 device_xname(sc->sc_dev)); 536 if (status & INTR_DMA_WR_TO_RST) 537 printf("%s: DMA write error! -- " 538 "resetting\n", 539 device_xname(sc->sc_dev)); 540 age_init(ifp); 541 } 542 543 if_schedule_deferred_start(ifp); 544 545 if (status & INTR_SMB) 546 age_stats_update(sc); 547 } 548 /* check if more interrupts did came in */ 549 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 550 sc->age_cdata.age_cmb_block_map->dm_mapsize, 551 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 552 status = le32toh(cmb->intr_status); 553 } 554 555 return 1; 556 } 557 558 static void 559 age_get_macaddr(struct age_softc *sc, uint8_t eaddr[]) 560 { 561 uint32_t ea[2], reg; 562 int i, vpdc; 563 564 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 565 if ((reg & SPI_VPD_ENB) != 0) { 566 /* Get VPD stored in TWSI EEPROM. */ 567 reg &= ~SPI_VPD_ENB; 568 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 569 } 570 571 if (pci_get_capability(sc->sc_pct, sc->sc_pcitag, 572 PCI_CAP_VPD, &vpdc, NULL)) { 573 /* 574 * PCI VPD capability found, let TWSI reload EEPROM. 575 * This will set Ethernet address of controller. 576 */ 577 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | 578 TWSI_CTRL_SW_LD_START); 579 for (i = 100; i > 0; i++) { 580 DELAY(1000); 581 reg = CSR_READ_4(sc, AGE_TWSI_CTRL); 582 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 583 break; 584 } 585 if (i == 0) 586 printf("%s: reloading EEPROM timeout!\n", 587 device_xname(sc->sc_dev)); 588 } else { 589 if (agedebug) 590 printf("%s: PCI VPD capability not found!\n", 591 device_xname(sc->sc_dev)); 592 } 593 594 ea[0] = CSR_READ_4(sc, AGE_PAR0); 595 ea[1] = CSR_READ_4(sc, AGE_PAR1); 596 597 eaddr[0] = (ea[1] >> 8) & 0xFF; 598 eaddr[1] = (ea[1] >> 0) & 0xFF; 599 eaddr[2] = (ea[0] >> 24) & 0xFF; 600 eaddr[3] = (ea[0] >> 16) & 0xFF; 601 eaddr[4] = (ea[0] >> 8) & 0xFF; 602 eaddr[5] = (ea[0] >> 0) & 0xFF; 603 } 604 605 static void 606 age_phy_reset(struct age_softc *sc) 607 { 608 uint16_t reg, pn; 609 int i, linkup; 610 611 /* Reset PHY. */ 612 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 613 DELAY(2000); 614 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 615 DELAY(2000); 616 617 #define ATPHY_DBG_ADDR 0x1D 618 #define ATPHY_DBG_DATA 0x1E 619 #define ATPHY_CDTC 0x16 620 #define PHY_CDTC_ENB 0x0001 621 #define PHY_CDTC_POFF 8 622 #define ATPHY_CDTS 0x1C 623 #define PHY_CDTS_STAT_OK 0x0000 624 #define PHY_CDTS_STAT_SHORT 0x0100 625 #define PHY_CDTS_STAT_OPEN 0x0200 626 #define PHY_CDTS_STAT_INVAL 0x0300 627 #define PHY_CDTS_STAT_MASK 0x0300 628 629 /* Check power saving mode. Magic from Linux. */ 630 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET); 631 for (linkup = 0, pn = 0; pn < 4; pn++) { 632 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, ATPHY_CDTC, 633 (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB); 634 for (i = 200; i > 0; i--) { 635 DELAY(1000); 636 age_miibus_readreg(sc->sc_dev, sc->age_phyaddr, 637 ATPHY_CDTC, ®); 638 if ((reg & PHY_CDTC_ENB) == 0) 639 break; 640 } 641 DELAY(1000); 642 age_miibus_readreg(sc->sc_dev, sc->age_phyaddr, 643 ATPHY_CDTS, ®); 644 if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) { 645 linkup++; 646 break; 647 } 648 } 649 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, MII_BMCR, 650 BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 651 if (linkup == 0) { 652 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, 653 ATPHY_DBG_ADDR, 0); 654 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, 655 ATPHY_DBG_DATA, 0x124E); 656 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, 657 ATPHY_DBG_ADDR, 1); 658 age_miibus_readreg(sc->sc_dev, sc->age_phyaddr, 659 ATPHY_DBG_DATA, ®); 660 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, 661 ATPHY_DBG_DATA, reg | 0x03); 662 /* XXX */ 663 DELAY(1500 * 1000); 664 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, 665 ATPHY_DBG_ADDR, 0); 666 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, 667 ATPHY_DBG_DATA, 0x024E); 668 } 669 670 #undef ATPHY_DBG_ADDR 671 #undef ATPHY_DBG_DATA 672 #undef ATPHY_CDTC 673 #undef PHY_CDTC_ENB 674 #undef PHY_CDTC_POFF 675 #undef ATPHY_CDTS 676 #undef PHY_CDTS_STAT_OK 677 #undef PHY_CDTS_STAT_SHORT 678 #undef PHY_CDTS_STAT_OPEN 679 #undef PHY_CDTS_STAT_INVAL 680 #undef PHY_CDTS_STAT_MASK 681 } 682 683 static int 684 age_dma_alloc(struct age_softc *sc) 685 { 686 struct age_txdesc *txd; 687 struct age_rxdesc *rxd; 688 int nsegs, error, i; 689 690 /* 691 * Create DMA stuffs for TX ring 692 */ 693 error = bus_dmamap_create(sc->sc_dmat, AGE_TX_RING_SZ, 1, 694 AGE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_tx_ring_map); 695 if (error) { 696 sc->age_cdata.age_tx_ring_map = NULL; 697 return ENOBUFS; 698 } 699 700 /* Allocate DMA'able memory for TX ring */ 701 error = bus_dmamem_alloc(sc->sc_dmat, AGE_TX_RING_SZ, 702 ETHER_ALIGN, 0, &sc->age_rdata.age_tx_ring_seg, 1, 703 &nsegs, BUS_DMA_NOWAIT); 704 if (error) { 705 printf("%s: could not allocate DMA'able memory for Tx ring, " 706 "error = %i\n", device_xname(sc->sc_dev), error); 707 return error; 708 } 709 710 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_tx_ring_seg, 711 nsegs, AGE_TX_RING_SZ, (void **)&sc->age_rdata.age_tx_ring, 712 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 713 if (error) 714 return ENOBUFS; 715 716 memset(sc->age_rdata.age_tx_ring, 0, AGE_TX_RING_SZ); 717 718 /* Load the DMA map for Tx ring. */ 719 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 720 sc->age_rdata.age_tx_ring, AGE_TX_RING_SZ, NULL, BUS_DMA_NOWAIT); 721 if (error) { 722 printf("%s: could not load DMA'able memory for Tx ring, " 723 "error = %i\n", device_xname(sc->sc_dev), error); 724 bus_dmamem_free(sc->sc_dmat, 725 &sc->age_rdata.age_tx_ring_seg, 1); 726 return error; 727 } 728 729 sc->age_rdata.age_tx_ring_paddr = 730 sc->age_cdata.age_tx_ring_map->dm_segs[0].ds_addr; 731 732 /* 733 * Create DMA stuffs for RX ring 734 */ 735 error = bus_dmamap_create(sc->sc_dmat, AGE_RX_RING_SZ, 1, 736 AGE_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_ring_map); 737 if (error) { 738 sc->age_cdata.age_rx_ring_map = NULL; 739 return ENOBUFS; 740 } 741 742 /* Allocate DMA'able memory for RX ring */ 743 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RX_RING_SZ, 744 ETHER_ALIGN, 0, &sc->age_rdata.age_rx_ring_seg, 1, 745 &nsegs, BUS_DMA_NOWAIT); 746 if (error) { 747 printf("%s: could not allocate DMA'able memory for Rx ring, " 748 "error = %i.\n", device_xname(sc->sc_dev), error); 749 return error; 750 } 751 752 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rx_ring_seg, 753 nsegs, AGE_RX_RING_SZ, (void **)&sc->age_rdata.age_rx_ring, 754 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 755 if (error) 756 return ENOBUFS; 757 758 memset(sc->age_rdata.age_rx_ring, 0, AGE_RX_RING_SZ); 759 760 /* Load the DMA map for Rx ring. */ 761 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 762 sc->age_rdata.age_rx_ring, AGE_RX_RING_SZ, NULL, BUS_DMA_NOWAIT); 763 if (error) { 764 printf("%s: could not load DMA'able memory for Rx ring, " 765 "error = %i.\n", device_xname(sc->sc_dev), error); 766 bus_dmamem_free(sc->sc_dmat, 767 &sc->age_rdata.age_rx_ring_seg, 1); 768 return error; 769 } 770 771 sc->age_rdata.age_rx_ring_paddr = 772 sc->age_cdata.age_rx_ring_map->dm_segs[0].ds_addr; 773 774 /* 775 * Create DMA stuffs for RX return ring 776 */ 777 error = bus_dmamap_create(sc->sc_dmat, AGE_RR_RING_SZ, 1, 778 AGE_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rr_ring_map); 779 if (error) { 780 sc->age_cdata.age_rr_ring_map = NULL; 781 return ENOBUFS; 782 } 783 784 /* Allocate DMA'able memory for RX return ring */ 785 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RR_RING_SZ, 786 ETHER_ALIGN, 0, &sc->age_rdata.age_rr_ring_seg, 1, 787 &nsegs, BUS_DMA_NOWAIT); 788 if (error) { 789 printf("%s: could not allocate DMA'able memory for Rx " 790 "return ring, error = %i.\n", 791 device_xname(sc->sc_dev), error); 792 return error; 793 } 794 795 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rr_ring_seg, 796 nsegs, AGE_RR_RING_SZ, (void **)&sc->age_rdata.age_rr_ring, 797 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 798 if (error) 799 return ENOBUFS; 800 801 memset(sc->age_rdata.age_rr_ring, 0, AGE_RR_RING_SZ); 802 803 /* Load the DMA map for Rx return ring. */ 804 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 805 sc->age_rdata.age_rr_ring, AGE_RR_RING_SZ, NULL, BUS_DMA_NOWAIT); 806 if (error) { 807 printf("%s: could not load DMA'able memory for Rx return ring, " 808 "error = %i\n", device_xname(sc->sc_dev), error); 809 bus_dmamem_free(sc->sc_dmat, 810 &sc->age_rdata.age_rr_ring_seg, 1); 811 return error; 812 } 813 814 sc->age_rdata.age_rr_ring_paddr = 815 sc->age_cdata.age_rr_ring_map->dm_segs[0].ds_addr; 816 817 /* 818 * Create DMA stuffs for CMB block 819 */ 820 error = bus_dmamap_create(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 1, 821 AGE_CMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 822 &sc->age_cdata.age_cmb_block_map); 823 if (error) { 824 sc->age_cdata.age_cmb_block_map = NULL; 825 return ENOBUFS; 826 } 827 828 /* Allocate DMA'able memory for CMB block */ 829 error = bus_dmamem_alloc(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 830 ETHER_ALIGN, 0, &sc->age_rdata.age_cmb_block_seg, 1, 831 &nsegs, BUS_DMA_NOWAIT); 832 if (error) { 833 printf("%s: could not allocate DMA'able memory for " 834 "CMB block, error = %i\n", device_xname(sc->sc_dev), error); 835 return error; 836 } 837 838 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_cmb_block_seg, 839 nsegs, AGE_CMB_BLOCK_SZ, (void **)&sc->age_rdata.age_cmb_block, 840 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 841 if (error) 842 return ENOBUFS; 843 844 memset(sc->age_rdata.age_cmb_block, 0, AGE_CMB_BLOCK_SZ); 845 846 /* Load the DMA map for CMB block. */ 847 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 848 sc->age_rdata.age_cmb_block, AGE_CMB_BLOCK_SZ, NULL, 849 BUS_DMA_NOWAIT); 850 if (error) { 851 printf("%s: could not load DMA'able memory for CMB block, " 852 "error = %i\n", device_xname(sc->sc_dev), error); 853 bus_dmamem_free(sc->sc_dmat, 854 &sc->age_rdata.age_cmb_block_seg, 1); 855 return error; 856 } 857 858 sc->age_rdata.age_cmb_block_paddr = 859 sc->age_cdata.age_cmb_block_map->dm_segs[0].ds_addr; 860 861 /* 862 * Create DMA stuffs for SMB block 863 */ 864 error = bus_dmamap_create(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 1, 865 AGE_SMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 866 &sc->age_cdata.age_smb_block_map); 867 if (error) { 868 sc->age_cdata.age_smb_block_map = NULL; 869 return ENOBUFS; 870 } 871 872 /* Allocate DMA'able memory for SMB block */ 873 error = bus_dmamem_alloc(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 874 ETHER_ALIGN, 0, &sc->age_rdata.age_smb_block_seg, 1, 875 &nsegs, BUS_DMA_NOWAIT); 876 if (error) { 877 printf("%s: could not allocate DMA'able memory for " 878 "SMB block, error = %i\n", device_xname(sc->sc_dev), error); 879 return error; 880 } 881 882 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_smb_block_seg, 883 nsegs, AGE_SMB_BLOCK_SZ, (void **)&sc->age_rdata.age_smb_block, 884 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 885 if (error) 886 return ENOBUFS; 887 888 memset(sc->age_rdata.age_smb_block, 0, AGE_SMB_BLOCK_SZ); 889 890 /* Load the DMA map for SMB block */ 891 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 892 sc->age_rdata.age_smb_block, AGE_SMB_BLOCK_SZ, NULL, 893 BUS_DMA_NOWAIT); 894 if (error) { 895 printf("%s: could not load DMA'able memory for SMB block, " 896 "error = %i\n", device_xname(sc->sc_dev), error); 897 bus_dmamem_free(sc->sc_dmat, 898 &sc->age_rdata.age_smb_block_seg, 1); 899 return error; 900 } 901 902 sc->age_rdata.age_smb_block_paddr = 903 sc->age_cdata.age_smb_block_map->dm_segs[0].ds_addr; 904 905 /* Create DMA maps for Tx buffers. */ 906 for (i = 0; i < AGE_TX_RING_CNT; i++) { 907 txd = &sc->age_cdata.age_txdesc[i]; 908 txd->tx_m = NULL; 909 txd->tx_dmamap = NULL; 910 error = bus_dmamap_create(sc->sc_dmat, AGE_TSO_MAXSIZE, 911 AGE_MAXTXSEGS, AGE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 912 &txd->tx_dmamap); 913 if (error) { 914 txd->tx_dmamap = NULL; 915 printf("%s: could not create Tx dmamap, error = %i.\n", 916 device_xname(sc->sc_dev), error); 917 return error; 918 } 919 } 920 921 /* Create DMA maps for Rx buffers. */ 922 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 923 BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_sparemap); 924 if (error) { 925 sc->age_cdata.age_rx_sparemap = NULL; 926 printf("%s: could not create spare Rx dmamap, error = %i.\n", 927 device_xname(sc->sc_dev), error); 928 return error; 929 } 930 for (i = 0; i < AGE_RX_RING_CNT; i++) { 931 rxd = &sc->age_cdata.age_rxdesc[i]; 932 rxd->rx_m = NULL; 933 rxd->rx_dmamap = NULL; 934 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 935 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 936 if (error) { 937 rxd->rx_dmamap = NULL; 938 printf("%s: could not create Rx dmamap, error = %i.\n", 939 device_xname(sc->sc_dev), error); 940 return error; 941 } 942 } 943 944 return 0; 945 } 946 947 static void 948 age_dma_free(struct age_softc *sc) 949 { 950 struct age_txdesc *txd; 951 struct age_rxdesc *rxd; 952 int i; 953 954 /* Tx buffers */ 955 for (i = 0; i < AGE_TX_RING_CNT; i++) { 956 txd = &sc->age_cdata.age_txdesc[i]; 957 if (txd->tx_dmamap != NULL) { 958 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 959 txd->tx_dmamap = NULL; 960 } 961 } 962 /* Rx buffers */ 963 for (i = 0; i < AGE_RX_RING_CNT; i++) { 964 rxd = &sc->age_cdata.age_rxdesc[i]; 965 if (rxd->rx_dmamap != NULL) { 966 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 967 rxd->rx_dmamap = NULL; 968 } 969 } 970 if (sc->age_cdata.age_rx_sparemap != NULL) { 971 bus_dmamap_destroy(sc->sc_dmat, sc->age_cdata.age_rx_sparemap); 972 sc->age_cdata.age_rx_sparemap = NULL; 973 } 974 975 /* Tx ring. */ 976 if (sc->age_cdata.age_tx_ring_map != NULL) 977 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_tx_ring_map); 978 if (sc->age_cdata.age_tx_ring_map != NULL && 979 sc->age_rdata.age_tx_ring != NULL) 980 bus_dmamem_free(sc->sc_dmat, 981 &sc->age_rdata.age_tx_ring_seg, 1); 982 sc->age_rdata.age_tx_ring = NULL; 983 sc->age_cdata.age_tx_ring_map = NULL; 984 985 /* Rx ring. */ 986 if (sc->age_cdata.age_rx_ring_map != NULL) 987 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rx_ring_map); 988 if (sc->age_cdata.age_rx_ring_map != NULL && 989 sc->age_rdata.age_rx_ring != NULL) 990 bus_dmamem_free(sc->sc_dmat, 991 &sc->age_rdata.age_rx_ring_seg, 1); 992 sc->age_rdata.age_rx_ring = NULL; 993 sc->age_cdata.age_rx_ring_map = NULL; 994 995 /* Rx return ring. */ 996 if (sc->age_cdata.age_rr_ring_map != NULL) 997 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rr_ring_map); 998 if (sc->age_cdata.age_rr_ring_map != NULL && 999 sc->age_rdata.age_rr_ring != NULL) 1000 bus_dmamem_free(sc->sc_dmat, 1001 &sc->age_rdata.age_rr_ring_seg, 1); 1002 sc->age_rdata.age_rr_ring = NULL; 1003 sc->age_cdata.age_rr_ring_map = NULL; 1004 1005 /* CMB block */ 1006 if (sc->age_cdata.age_cmb_block_map != NULL) 1007 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_cmb_block_map); 1008 if (sc->age_cdata.age_cmb_block_map != NULL && 1009 sc->age_rdata.age_cmb_block != NULL) 1010 bus_dmamem_free(sc->sc_dmat, 1011 &sc->age_rdata.age_cmb_block_seg, 1); 1012 sc->age_rdata.age_cmb_block = NULL; 1013 sc->age_cdata.age_cmb_block_map = NULL; 1014 1015 /* SMB block */ 1016 if (sc->age_cdata.age_smb_block_map != NULL) 1017 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_smb_block_map); 1018 if (sc->age_cdata.age_smb_block_map != NULL && 1019 sc->age_rdata.age_smb_block != NULL) 1020 bus_dmamem_free(sc->sc_dmat, 1021 &sc->age_rdata.age_smb_block_seg, 1); 1022 sc->age_rdata.age_smb_block = NULL; 1023 sc->age_cdata.age_smb_block_map = NULL; 1024 } 1025 1026 static void 1027 age_start(struct ifnet *ifp) 1028 { 1029 struct age_softc *sc = ifp->if_softc; 1030 struct mbuf *m_head; 1031 int enq; 1032 1033 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1034 return; 1035 if ((sc->age_flags & AGE_FLAG_LINK) == 0) 1036 return; 1037 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1038 return; 1039 1040 enq = 0; 1041 for (;;) { 1042 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1043 if (m_head == NULL) 1044 break; 1045 1046 /* 1047 * Pack the data into the transmit ring. If we 1048 * don't have room, set the OACTIVE flag and wait 1049 * for the NIC to drain the ring. 1050 */ 1051 if (age_encap(sc, &m_head)) { 1052 if (m_head == NULL) 1053 break; 1054 IF_PREPEND(&ifp->if_snd, m_head); 1055 ifp->if_flags |= IFF_OACTIVE; 1056 break; 1057 } 1058 enq = 1; 1059 1060 /* 1061 * If there's a BPF listener, bounce a copy of this frame 1062 * to him. 1063 */ 1064 bpf_mtap(ifp, m_head, BPF_D_OUT); 1065 } 1066 1067 if (enq) { 1068 /* Update mbox. */ 1069 AGE_COMMIT_MBOX(sc); 1070 /* Set a timeout in case the chip goes out to lunch. */ 1071 ifp->if_timer = AGE_TX_TIMEOUT; 1072 } 1073 } 1074 1075 static void 1076 age_watchdog(struct ifnet *ifp) 1077 { 1078 struct age_softc *sc = ifp->if_softc; 1079 1080 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1081 printf("%s: watchdog timeout (missed link)\n", 1082 device_xname(sc->sc_dev)); 1083 ifp->if_oerrors++; 1084 age_init(ifp); 1085 return; 1086 } 1087 1088 if (sc->age_cdata.age_tx_cnt == 0) { 1089 printf("%s: watchdog timeout (missed Tx interrupts) " 1090 "-- recovering\n", device_xname(sc->sc_dev)); 1091 age_start(ifp); 1092 return; 1093 } 1094 1095 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1096 ifp->if_oerrors++; 1097 age_init(ifp); 1098 age_start(ifp); 1099 } 1100 1101 static bool 1102 age_shutdown(device_t self, int howto) 1103 { 1104 struct age_softc *sc; 1105 struct ifnet *ifp; 1106 1107 sc = device_private(self); 1108 ifp = &sc->sc_ec.ec_if; 1109 age_stop(ifp, 1); 1110 1111 return true; 1112 } 1113 1114 1115 static int 1116 age_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1117 { 1118 struct age_softc *sc = ifp->if_softc; 1119 int s, error; 1120 1121 s = splnet(); 1122 1123 error = ether_ioctl(ifp, cmd, data); 1124 if (error == ENETRESET) { 1125 if (ifp->if_flags & IFF_RUNNING) 1126 age_rxfilter(sc); 1127 error = 0; 1128 } 1129 1130 splx(s); 1131 return error; 1132 } 1133 1134 static void 1135 age_mac_config(struct age_softc *sc) 1136 { 1137 struct mii_data *mii; 1138 uint32_t reg; 1139 1140 mii = &sc->sc_miibus; 1141 1142 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1143 reg &= ~MAC_CFG_FULL_DUPLEX; 1144 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1145 reg &= ~MAC_CFG_SPEED_MASK; 1146 1147 /* Reprogram MAC with resolved speed/duplex. */ 1148 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1149 case IFM_10_T: 1150 case IFM_100_TX: 1151 reg |= MAC_CFG_SPEED_10_100; 1152 break; 1153 case IFM_1000_T: 1154 reg |= MAC_CFG_SPEED_1000; 1155 break; 1156 } 1157 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1158 reg |= MAC_CFG_FULL_DUPLEX; 1159 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1160 reg |= MAC_CFG_TX_FC; 1161 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1162 reg |= MAC_CFG_RX_FC; 1163 } 1164 1165 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1166 } 1167 1168 static bool 1169 age_resume(device_t dv, const pmf_qual_t *qual) 1170 { 1171 struct age_softc *sc = device_private(dv); 1172 uint16_t cmd; 1173 1174 /* 1175 * Clear INTx emulation disable for hardware that 1176 * is set in resume event. From Linux. 1177 */ 1178 cmd = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 1179 if ((cmd & PCI_COMMAND_INTERRUPT_DISABLE) != 0) { 1180 cmd &= ~PCI_COMMAND_INTERRUPT_DISABLE; 1181 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 1182 PCI_COMMAND_STATUS_REG, cmd); 1183 } 1184 1185 return true; 1186 } 1187 1188 static int 1189 age_encap(struct age_softc *sc, struct mbuf **m_head) 1190 { 1191 struct age_txdesc *txd, *txd_last; 1192 struct tx_desc *desc; 1193 struct mbuf *m; 1194 bus_dmamap_t map; 1195 uint32_t cflags, poff, vtag; 1196 int error, i, nsegs, prod; 1197 1198 m = *m_head; 1199 cflags = vtag = 0; 1200 poff = 0; 1201 1202 prod = sc->age_cdata.age_tx_prod; 1203 txd = &sc->age_cdata.age_txdesc[prod]; 1204 txd_last = txd; 1205 map = txd->tx_dmamap; 1206 1207 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1208 1209 if (error == EFBIG) { 1210 error = 0; 1211 1212 *m_head = m_pullup(*m_head, MHLEN); 1213 if (*m_head == NULL) { 1214 printf("%s: can't defrag TX mbuf\n", 1215 device_xname(sc->sc_dev)); 1216 return ENOBUFS; 1217 } 1218 1219 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1220 BUS_DMA_NOWAIT); 1221 1222 if (error != 0) { 1223 printf("%s: could not load defragged TX mbuf\n", 1224 device_xname(sc->sc_dev)); 1225 m_freem(*m_head); 1226 *m_head = NULL; 1227 return error; 1228 } 1229 } else if (error) { 1230 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 1231 return error; 1232 } 1233 1234 nsegs = map->dm_nsegs; 1235 1236 if (nsegs == 0) { 1237 m_freem(*m_head); 1238 *m_head = NULL; 1239 return EIO; 1240 } 1241 1242 /* Check descriptor overrun. */ 1243 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1244 bus_dmamap_unload(sc->sc_dmat, map); 1245 return ENOBUFS; 1246 } 1247 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1248 BUS_DMASYNC_PREWRITE); 1249 1250 m = *m_head; 1251 /* Configure Tx IP/TCP/UDP checksum offload. */ 1252 if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1253 cflags |= AGE_TD_CSUM; 1254 if ((m->m_pkthdr.csum_flags & M_CSUM_TCPv4) != 0) 1255 cflags |= AGE_TD_TCPCSUM; 1256 if ((m->m_pkthdr.csum_flags & M_CSUM_UDPv4) != 0) 1257 cflags |= AGE_TD_UDPCSUM; 1258 /* Set checksum start offset. */ 1259 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1260 } 1261 1262 #if NVLAN > 0 1263 /* Configure VLAN hardware tag insertion. */ 1264 if (vlan_has_tag(m)) { 1265 vtag = AGE_TX_VLAN_TAG(htons(vlan_get_tag(m))); 1266 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1267 cflags |= AGE_TD_INSERT_VLAN_TAG; 1268 } 1269 #endif 1270 1271 desc = NULL; 1272 KASSERT(nsegs > 0); 1273 for (i = 0; ; i++) { 1274 desc = &sc->age_rdata.age_tx_ring[prod]; 1275 desc->addr = htole64(map->dm_segs[i].ds_addr); 1276 desc->len = 1277 htole32(AGE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 1278 desc->flags = htole32(cflags); 1279 sc->age_cdata.age_tx_cnt++; 1280 if (i == (nsegs - 1)) 1281 break; 1282 1283 /* sync this descriptor and go to the next one */ 1284 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 1285 prod * sizeof(struct tx_desc), sizeof(struct tx_desc), 1286 BUS_DMASYNC_PREWRITE); 1287 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1288 } 1289 1290 /* Set EOP on the last descriptor and sync it. */ 1291 desc->flags |= htole32(AGE_TD_EOP); 1292 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 1293 prod * sizeof(struct tx_desc), sizeof(struct tx_desc), 1294 BUS_DMASYNC_PREWRITE); 1295 1296 if (nsegs > 1) { 1297 /* Swap dmamap of the first and the last. */ 1298 txd = &sc->age_cdata.age_txdesc[prod]; 1299 map = txd_last->tx_dmamap; 1300 txd_last->tx_dmamap = txd->tx_dmamap; 1301 txd->tx_dmamap = map; 1302 txd->tx_m = m; 1303 KASSERT(txd_last->tx_m == NULL); 1304 } else { 1305 KASSERT(txd_last == &sc->age_cdata.age_txdesc[prod]); 1306 txd_last->tx_m = m; 1307 } 1308 1309 /* Update producer index. */ 1310 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1311 sc->age_cdata.age_tx_prod = prod; 1312 1313 return 0; 1314 } 1315 1316 static void 1317 age_txintr(struct age_softc *sc, int tpd_cons) 1318 { 1319 struct ifnet *ifp = &sc->sc_ec.ec_if; 1320 struct age_txdesc *txd; 1321 int cons, prog; 1322 1323 1324 if (sc->age_cdata.age_tx_cnt <= 0) { 1325 if (ifp->if_timer != 0) 1326 printf("timer running without packets\n"); 1327 if (sc->age_cdata.age_tx_cnt) 1328 printf("age_tx_cnt corrupted\n"); 1329 } 1330 1331 /* 1332 * Go through our Tx list and free mbufs for those 1333 * frames which have been transmitted. 1334 */ 1335 cons = sc->age_cdata.age_tx_cons; 1336 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 1337 if (sc->age_cdata.age_tx_cnt <= 0) 1338 break; 1339 prog++; 1340 ifp->if_flags &= ~IFF_OACTIVE; 1341 sc->age_cdata.age_tx_cnt--; 1342 txd = &sc->age_cdata.age_txdesc[cons]; 1343 /* 1344 * Clear Tx descriptors, it's not required but would 1345 * help debugging in case of Tx issues. 1346 */ 1347 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 1348 cons * sizeof(struct tx_desc), sizeof(struct tx_desc), 1349 BUS_DMASYNC_POSTWRITE); 1350 txd->tx_desc->addr = 0; 1351 txd->tx_desc->len = 0; 1352 txd->tx_desc->flags = 0; 1353 1354 if (txd->tx_m == NULL) 1355 continue; 1356 /* Reclaim transmitted mbufs. */ 1357 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1358 m_freem(txd->tx_m); 1359 txd->tx_m = NULL; 1360 } 1361 1362 if (prog > 0) { 1363 sc->age_cdata.age_tx_cons = cons; 1364 1365 /* 1366 * Unarm watchdog timer only when there are no pending 1367 * Tx descriptors in queue. 1368 */ 1369 if (sc->age_cdata.age_tx_cnt == 0) 1370 ifp->if_timer = 0; 1371 } 1372 } 1373 1374 /* Receive a frame. */ 1375 static void 1376 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 1377 { 1378 struct ifnet *ifp = &sc->sc_ec.ec_if; 1379 struct age_rxdesc *rxd; 1380 struct rx_desc *desc; 1381 struct mbuf *mp, *m; 1382 uint32_t status, index; 1383 int count, nsegs, pktlen; 1384 int rx_cons; 1385 1386 status = le32toh(rxrd->flags); 1387 index = le32toh(rxrd->index); 1388 rx_cons = AGE_RX_CONS(index); 1389 nsegs = AGE_RX_NSEGS(index); 1390 1391 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 1392 if ((status & AGE_RRD_ERROR) != 0 && 1393 (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 1394 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) { 1395 /* 1396 * We want to pass the following frames to upper 1397 * layer regardless of error status of Rx return 1398 * ring. 1399 * 1400 * o IP/TCP/UDP checksum is bad. 1401 * o frame length and protocol specific length 1402 * does not match. 1403 */ 1404 sc->age_cdata.age_rx_cons += nsegs; 1405 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1406 return; 1407 } 1408 1409 pktlen = 0; 1410 for (count = 0; count < nsegs; count++, 1411 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 1412 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 1413 mp = rxd->rx_m; 1414 desc = rxd->rx_desc; 1415 /* Add a new receive buffer to the ring. */ 1416 if (age_newbuf(sc, rxd, 0) != 0) { 1417 ifp->if_iqdrops++; 1418 /* Reuse Rx buffers. */ 1419 if (sc->age_cdata.age_rxhead != NULL) { 1420 m_freem(sc->age_cdata.age_rxhead); 1421 AGE_RXCHAIN_RESET(sc); 1422 } 1423 break; 1424 } 1425 1426 /* The length of the first mbuf is computed last. */ 1427 if (count != 0) { 1428 mp->m_len = AGE_RX_BYTES(le32toh(desc->len)); 1429 pktlen += mp->m_len; 1430 } 1431 1432 /* Chain received mbufs. */ 1433 if (sc->age_cdata.age_rxhead == NULL) { 1434 sc->age_cdata.age_rxhead = mp; 1435 sc->age_cdata.age_rxtail = mp; 1436 } else { 1437 m_remove_pkthdr(mp); 1438 sc->age_cdata.age_rxprev_tail = 1439 sc->age_cdata.age_rxtail; 1440 sc->age_cdata.age_rxtail->m_next = mp; 1441 sc->age_cdata.age_rxtail = mp; 1442 } 1443 1444 if (count == nsegs - 1) { 1445 /* 1446 * It seems that L1 controller has no way 1447 * to tell hardware to strip CRC bytes. 1448 */ 1449 sc->age_cdata.age_rxlen -= ETHER_CRC_LEN; 1450 if (nsegs > 1) { 1451 /* Remove the CRC bytes in chained mbufs. */ 1452 pktlen -= ETHER_CRC_LEN; 1453 if (mp->m_len <= ETHER_CRC_LEN) { 1454 sc->age_cdata.age_rxtail = 1455 sc->age_cdata.age_rxprev_tail; 1456 sc->age_cdata.age_rxtail->m_len -= 1457 (ETHER_CRC_LEN - mp->m_len); 1458 sc->age_cdata.age_rxtail->m_next = NULL; 1459 m_freem(mp); 1460 } else { 1461 mp->m_len -= ETHER_CRC_LEN; 1462 } 1463 } 1464 1465 m = sc->age_cdata.age_rxhead; 1466 KASSERT(m->m_flags & M_PKTHDR); 1467 m_set_rcvif(m, ifp); 1468 m->m_pkthdr.len = sc->age_cdata.age_rxlen; 1469 /* Set the first mbuf length. */ 1470 m->m_len = sc->age_cdata.age_rxlen - pktlen; 1471 1472 /* 1473 * Set checksum information. 1474 * It seems that L1 controller can compute partial 1475 * checksum. The partial checksum value can be used 1476 * to accelerate checksum computation for fragmented 1477 * TCP/UDP packets. Upper network stack already 1478 * takes advantage of the partial checksum value in 1479 * IP reassembly stage. But I'm not sure the 1480 * correctness of the partial hardware checksum 1481 * assistance due to lack of data sheet. If it is 1482 * proven to work on L1 I'll enable it. 1483 */ 1484 if (status & AGE_RRD_IPV4) { 1485 if (status & AGE_RRD_IPCSUM_NOK) 1486 m->m_pkthdr.csum_flags |= 1487 M_CSUM_IPv4_BAD; 1488 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 1489 (status & AGE_RRD_TCP_UDPCSUM_NOK)) { 1490 m->m_pkthdr.csum_flags |= 1491 M_CSUM_TCP_UDP_BAD; 1492 } 1493 /* 1494 * Don't mark bad checksum for TCP/UDP frames 1495 * as fragmented frames may always have set 1496 * bad checksummed bit of descriptor status. 1497 */ 1498 } 1499 #if NVLAN > 0 1500 /* Check for VLAN tagged frames. */ 1501 if (status & AGE_RRD_VLAN) { 1502 uint32_t vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 1503 vlan_set_tag(m, AGE_RX_VLAN_TAG(vtag)); 1504 } 1505 #endif 1506 1507 /* Pass it on. */ 1508 if_percpuq_enqueue(ifp->if_percpuq, m); 1509 1510 /* Reset mbuf chains. */ 1511 AGE_RXCHAIN_RESET(sc); 1512 } 1513 } 1514 1515 if (count != nsegs) { 1516 sc->age_cdata.age_rx_cons += nsegs; 1517 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1518 } else 1519 sc->age_cdata.age_rx_cons = rx_cons; 1520 } 1521 1522 static void 1523 age_rxintr(struct age_softc *sc, int rr_prod) 1524 { 1525 struct rx_rdesc *rxrd; 1526 int rr_cons, nsegs, pktlen, prog; 1527 1528 rr_cons = sc->age_cdata.age_rr_cons; 1529 if (rr_cons == rr_prod) 1530 return; 1531 1532 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1533 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1534 BUS_DMASYNC_POSTREAD); 1535 1536 for (prog = 0; rr_cons != rr_prod; prog++) { 1537 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 1538 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 1539 if (nsegs == 0) 1540 break; 1541 /* 1542 * Check number of segments against received bytes 1543 * Non-matching value would indicate that hardware 1544 * is still trying to update Rx return descriptors. 1545 * I'm not sure whether this check is really needed. 1546 */ 1547 pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 1548 if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) / 1549 (MCLBYTES - ETHER_ALIGN))) 1550 break; 1551 1552 /* Received a frame. */ 1553 age_rxeof(sc, rxrd); 1554 1555 /* Clear return ring. */ 1556 rxrd->index = 0; 1557 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 1558 } 1559 1560 if (prog > 0) { 1561 /* Update the consumer index. */ 1562 sc->age_cdata.age_rr_cons = rr_cons; 1563 1564 /* Sync descriptors. */ 1565 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1566 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1567 BUS_DMASYNC_PREWRITE); 1568 1569 /* Notify hardware availability of new Rx buffers. */ 1570 AGE_COMMIT_MBOX(sc); 1571 } 1572 } 1573 1574 static void 1575 age_tick(void *xsc) 1576 { 1577 struct age_softc *sc = xsc; 1578 struct mii_data *mii = &sc->sc_miibus; 1579 int s; 1580 1581 s = splnet(); 1582 mii_tick(mii); 1583 splx(s); 1584 1585 callout_schedule(&sc->sc_tick_ch, hz); 1586 } 1587 1588 static void 1589 age_reset(struct age_softc *sc) 1590 { 1591 uint32_t reg; 1592 int i; 1593 1594 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 1595 CSR_READ_4(sc, AGE_MASTER_CFG); 1596 DELAY(1000); 1597 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1598 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1599 break; 1600 DELAY(10); 1601 } 1602 1603 if (i == 0) 1604 printf("%s: reset timeout(0x%08x)!\n", device_xname(sc->sc_dev), 1605 reg); 1606 1607 /* Initialize PCIe module. From Linux. */ 1608 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1609 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1610 } 1611 1612 static int 1613 age_init(struct ifnet *ifp) 1614 { 1615 struct age_softc *sc = ifp->if_softc; 1616 struct mii_data *mii; 1617 uint8_t eaddr[ETHER_ADDR_LEN]; 1618 bus_addr_t paddr; 1619 uint32_t reg, fsize; 1620 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 1621 int error; 1622 1623 /* 1624 * Cancel any pending I/O. 1625 */ 1626 age_stop(ifp, 0); 1627 1628 /* 1629 * Reset the chip to a known state. 1630 */ 1631 age_reset(sc); 1632 1633 /* Initialize descriptors. */ 1634 error = age_init_rx_ring(sc); 1635 if (error != 0) { 1636 printf("%s: no memory for Rx buffers.\n", device_xname(sc->sc_dev)); 1637 age_stop(ifp, 0); 1638 return error; 1639 } 1640 age_init_rr_ring(sc); 1641 age_init_tx_ring(sc); 1642 age_init_cmb_block(sc); 1643 age_init_smb_block(sc); 1644 1645 /* Reprogram the station address. */ 1646 memcpy(eaddr, CLLADDR(ifp->if_sadl), sizeof(eaddr)); 1647 CSR_WRITE_4(sc, AGE_PAR0, 1648 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1649 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 1650 1651 /* Set descriptor base addresses. */ 1652 paddr = sc->age_rdata.age_tx_ring_paddr; 1653 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 1654 paddr = sc->age_rdata.age_rx_ring_paddr; 1655 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 1656 paddr = sc->age_rdata.age_rr_ring_paddr; 1657 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 1658 paddr = sc->age_rdata.age_tx_ring_paddr; 1659 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 1660 paddr = sc->age_rdata.age_cmb_block_paddr; 1661 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1662 paddr = sc->age_rdata.age_smb_block_paddr; 1663 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1664 1665 /* Set Rx/Rx return descriptor counter. */ 1666 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 1667 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 1668 DESC_RRD_CNT_MASK) | 1669 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 1670 1671 /* Set Tx descriptor counter. */ 1672 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 1673 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 1674 1675 /* Tell hardware that we're ready to load descriptors. */ 1676 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 1677 1678 /* 1679 * Initialize mailbox register. 1680 * Updated producer/consumer index information is exchanged 1681 * through this mailbox register. However Tx producer and 1682 * Rx return consumer/Rx producer are all shared such that 1683 * it's hard to separate code path between Tx and Rx without 1684 * locking. If L1 hardware have a separate mail box register 1685 * for Tx and Rx consumer/producer management we could have 1686 * indepent Tx/Rx handler which in turn Rx handler could have 1687 * been run without any locking. 1688 */ 1689 AGE_COMMIT_MBOX(sc); 1690 1691 /* Configure IPG/IFG parameters. */ 1692 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 1693 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 1694 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1695 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1696 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 1697 1698 /* Set parameters for half-duplex media. */ 1699 CSR_WRITE_4(sc, AGE_HDPX_CFG, 1700 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1701 HDPX_CFG_LCOL_MASK) | 1702 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1703 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1704 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1705 HDPX_CFG_ABEBT_MASK) | 1706 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1707 HDPX_CFG_JAMIPG_MASK)); 1708 1709 /* Configure interrupt moderation timer. */ 1710 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 1711 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 1712 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 1713 reg &= ~MASTER_MTIMER_ENB; 1714 if (AGE_USECS(sc->age_int_mod) == 0) 1715 reg &= ~MASTER_ITIMER_ENB; 1716 else 1717 reg |= MASTER_ITIMER_ENB; 1718 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 1719 if (agedebug) 1720 printf("%s: interrupt moderation is %d us.\n", 1721 device_xname(sc->sc_dev), sc->age_int_mod); 1722 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 1723 1724 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 1725 if (ifp->if_mtu < ETHERMTU) 1726 sc->age_max_frame_size = ETHERMTU; 1727 else 1728 sc->age_max_frame_size = ifp->if_mtu; 1729 sc->age_max_frame_size += ETHER_HDR_LEN + 1730 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 1731 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 1732 1733 /* Configure jumbo frame. */ 1734 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 1735 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 1736 (((fsize / sizeof(uint64_t)) << 1737 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 1738 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 1739 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 1740 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 1741 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 1742 1743 /* Configure flow-control parameters. From Linux. */ 1744 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 1745 /* 1746 * Magic workaround for old-L1. 1747 * Don't know which hw revision requires this magic. 1748 */ 1749 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1750 /* 1751 * Another magic workaround for flow-control mode 1752 * change. From Linux. 1753 */ 1754 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1755 } 1756 /* 1757 * TODO 1758 * Should understand pause parameter relationships between FIFO 1759 * size and number of Rx descriptors and Rx return descriptors. 1760 * 1761 * Magic parameters came from Linux. 1762 */ 1763 switch (sc->age_chip_rev) { 1764 case 0x8001: 1765 case 0x9001: 1766 case 0x9002: 1767 case 0x9003: 1768 rxf_hi = AGE_RX_RING_CNT / 16; 1769 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 1770 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 1771 rrd_lo = AGE_RR_RING_CNT / 16; 1772 break; 1773 default: 1774 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 1775 rxf_lo = reg / 16; 1776 if (rxf_lo < 192) 1777 rxf_lo = 192; 1778 rxf_hi = (reg * 7) / 8; 1779 if (rxf_hi < rxf_lo) 1780 rxf_hi = rxf_lo + 16; 1781 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 1782 rrd_lo = reg / 8; 1783 rrd_hi = (reg * 7) / 8; 1784 if (rrd_lo < 2) 1785 rrd_lo = 2; 1786 if (rrd_hi < rrd_lo) 1787 rrd_hi = rrd_lo + 3; 1788 break; 1789 } 1790 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 1791 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 1792 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 1793 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 1794 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 1795 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 1796 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 1797 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 1798 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 1799 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 1800 1801 /* Configure RxQ. */ 1802 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1803 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 1804 RXQ_CFG_RD_BURST_MASK) | 1805 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 1806 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 1807 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 1808 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 1809 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1810 1811 /* Configure TxQ. */ 1812 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1813 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1814 TXQ_CFG_TPD_BURST_MASK) | 1815 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 1816 TXQ_CFG_TX_FIFO_BURST_MASK) | 1817 ((TXQ_CFG_TPD_FETCH_DEFAULT << 1818 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 1819 TXQ_CFG_ENB); 1820 1821 /* Configure DMA parameters. */ 1822 CSR_WRITE_4(sc, AGE_DMA_CFG, 1823 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 1824 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 1825 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 1826 1827 /* Configure CMB DMA write threshold. */ 1828 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 1829 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 1830 CMB_WR_THRESH_RRD_MASK) | 1831 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 1832 CMB_WR_THRESH_TPD_MASK)); 1833 1834 /* Set CMB/SMB timer and enable them. */ 1835 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 1836 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 1837 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 1838 1839 /* Request SMB updates for every seconds. */ 1840 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 1841 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 1842 1843 /* 1844 * Disable all WOL bits as WOL can interfere normal Rx 1845 * operation. 1846 */ 1847 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1848 1849 /* 1850 * Configure Tx/Rx MACs. 1851 * - Auto-padding for short frames. 1852 * - Enable CRC generation. 1853 * Start with full-duplex/1000Mbps media. Actual reconfiguration 1854 * of MAC is followed after link establishment. 1855 */ 1856 CSR_WRITE_4(sc, AGE_MAC_CFG, 1857 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 1858 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 1859 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1860 MAC_CFG_PREAMBLE_MASK)); 1861 1862 /* Set up the receive filter. */ 1863 age_rxfilter(sc); 1864 age_rxvlan(sc); 1865 1866 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1867 reg |= MAC_CFG_RXCSUM_ENB; 1868 1869 /* Ack all pending interrupts and clear it. */ 1870 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 1871 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 1872 1873 /* Finally enable Tx/Rx MAC. */ 1874 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 1875 1876 sc->age_flags &= ~AGE_FLAG_LINK; 1877 1878 /* Switch to the current media. */ 1879 mii = &sc->sc_miibus; 1880 mii_mediachg(mii); 1881 1882 callout_schedule(&sc->sc_tick_ch, hz); 1883 1884 ifp->if_flags |= IFF_RUNNING; 1885 ifp->if_flags &= ~IFF_OACTIVE; 1886 1887 return 0; 1888 } 1889 1890 static void 1891 age_stop(struct ifnet *ifp, int disable) 1892 { 1893 struct age_softc *sc = ifp->if_softc; 1894 struct age_txdesc *txd; 1895 struct age_rxdesc *rxd; 1896 uint32_t reg; 1897 int i; 1898 1899 callout_stop(&sc->sc_tick_ch); 1900 1901 /* 1902 * Mark the interface down and cancel the watchdog timer. 1903 */ 1904 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1905 ifp->if_timer = 0; 1906 1907 sc->age_flags &= ~AGE_FLAG_LINK; 1908 1909 mii_down(&sc->sc_miibus); 1910 1911 /* 1912 * Disable interrupts. 1913 */ 1914 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 1915 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 1916 1917 /* Stop CMB/SMB updates. */ 1918 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 1919 1920 /* Stop Rx/Tx MAC. */ 1921 age_stop_rxmac(sc); 1922 age_stop_txmac(sc); 1923 1924 /* Stop DMA. */ 1925 CSR_WRITE_4(sc, AGE_DMA_CFG, 1926 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 1927 1928 /* Stop TxQ/RxQ. */ 1929 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1930 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 1931 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1932 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 1933 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1934 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1935 break; 1936 DELAY(10); 1937 } 1938 if (i == 0) 1939 printf("%s: stopping Rx/Tx MACs timed out(0x%08x)!\n", 1940 device_xname(sc->sc_dev), reg); 1941 1942 /* Reclaim Rx buffers that have been processed. */ 1943 if (sc->age_cdata.age_rxhead != NULL) 1944 m_freem(sc->age_cdata.age_rxhead); 1945 AGE_RXCHAIN_RESET(sc); 1946 1947 /* 1948 * Free RX and TX mbufs still in the queues. 1949 */ 1950 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1951 rxd = &sc->age_cdata.age_rxdesc[i]; 1952 if (rxd->rx_m != NULL) { 1953 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1954 m_freem(rxd->rx_m); 1955 rxd->rx_m = NULL; 1956 } 1957 } 1958 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1959 txd = &sc->age_cdata.age_txdesc[i]; 1960 if (txd->tx_m != NULL) { 1961 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1962 m_freem(txd->tx_m); 1963 txd->tx_m = NULL; 1964 } 1965 } 1966 } 1967 1968 static void 1969 age_stats_update(struct age_softc *sc) 1970 { 1971 struct ifnet *ifp = &sc->sc_ec.ec_if; 1972 struct age_stats *stat; 1973 struct smb *smb; 1974 1975 stat = &sc->age_stat; 1976 1977 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 1978 sc->age_cdata.age_smb_block_map->dm_mapsize, 1979 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1980 1981 smb = sc->age_rdata.age_smb_block; 1982 if (smb->updated == 0) 1983 return; 1984 1985 /* Rx stats. */ 1986 stat->rx_frames += smb->rx_frames; 1987 stat->rx_bcast_frames += smb->rx_bcast_frames; 1988 stat->rx_mcast_frames += smb->rx_mcast_frames; 1989 stat->rx_pause_frames += smb->rx_pause_frames; 1990 stat->rx_control_frames += smb->rx_control_frames; 1991 stat->rx_crcerrs += smb->rx_crcerrs; 1992 stat->rx_lenerrs += smb->rx_lenerrs; 1993 stat->rx_bytes += smb->rx_bytes; 1994 stat->rx_runts += smb->rx_runts; 1995 stat->rx_fragments += smb->rx_fragments; 1996 stat->rx_pkts_64 += smb->rx_pkts_64; 1997 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1998 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1999 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2000 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2001 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2002 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2003 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2004 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2005 stat->rx_desc_oflows += smb->rx_desc_oflows; 2006 stat->rx_alignerrs += smb->rx_alignerrs; 2007 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2008 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2009 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2010 2011 /* Tx stats. */ 2012 stat->tx_frames += smb->tx_frames; 2013 stat->tx_bcast_frames += smb->tx_bcast_frames; 2014 stat->tx_mcast_frames += smb->tx_mcast_frames; 2015 stat->tx_pause_frames += smb->tx_pause_frames; 2016 stat->tx_excess_defer += smb->tx_excess_defer; 2017 stat->tx_control_frames += smb->tx_control_frames; 2018 stat->tx_deferred += smb->tx_deferred; 2019 stat->tx_bytes += smb->tx_bytes; 2020 stat->tx_pkts_64 += smb->tx_pkts_64; 2021 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2022 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2023 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2024 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2025 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2026 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2027 stat->tx_single_colls += smb->tx_single_colls; 2028 stat->tx_multi_colls += smb->tx_multi_colls; 2029 stat->tx_late_colls += smb->tx_late_colls; 2030 stat->tx_excess_colls += smb->tx_excess_colls; 2031 stat->tx_underrun += smb->tx_underrun; 2032 stat->tx_desc_underrun += smb->tx_desc_underrun; 2033 stat->tx_lenerrs += smb->tx_lenerrs; 2034 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2035 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2036 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2037 2038 /* Update counters in ifnet. */ 2039 ifp->if_opackets += smb->tx_frames; 2040 2041 ifp->if_collisions += smb->tx_single_colls + 2042 smb->tx_multi_colls + smb->tx_late_colls + 2043 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 2044 2045 ifp->if_oerrors += smb->tx_excess_colls + 2046 smb->tx_late_colls + smb->tx_underrun + 2047 smb->tx_pkts_truncated; 2048 2049 ifp->if_ipackets += smb->rx_frames; 2050 2051 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2052 smb->rx_runts + smb->rx_pkts_truncated + 2053 smb->rx_fifo_oflows + smb->rx_desc_oflows + 2054 smb->rx_alignerrs; 2055 2056 /* Update done, clear. */ 2057 smb->updated = 0; 2058 2059 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2060 sc->age_cdata.age_smb_block_map->dm_mapsize, 2061 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2062 } 2063 2064 static void 2065 age_stop_txmac(struct age_softc *sc) 2066 { 2067 uint32_t reg; 2068 int i; 2069 2070 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2071 if ((reg & MAC_CFG_TX_ENB) != 0) { 2072 reg &= ~MAC_CFG_TX_ENB; 2073 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2074 } 2075 /* Stop Tx DMA engine. */ 2076 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2077 if ((reg & DMA_CFG_RD_ENB) != 0) { 2078 reg &= ~DMA_CFG_RD_ENB; 2079 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2080 } 2081 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2082 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2083 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2084 break; 2085 DELAY(10); 2086 } 2087 if (i == 0) 2088 printf("%s: stopping TxMAC timeout!\n", device_xname(sc->sc_dev)); 2089 } 2090 2091 static void 2092 age_stop_rxmac(struct age_softc *sc) 2093 { 2094 uint32_t reg; 2095 int i; 2096 2097 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2098 if ((reg & MAC_CFG_RX_ENB) != 0) { 2099 reg &= ~MAC_CFG_RX_ENB; 2100 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2101 } 2102 /* Stop Rx DMA engine. */ 2103 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2104 if ((reg & DMA_CFG_WR_ENB) != 0) { 2105 reg &= ~DMA_CFG_WR_ENB; 2106 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2107 } 2108 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2109 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2110 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2111 break; 2112 DELAY(10); 2113 } 2114 if (i == 0) 2115 printf("%s: stopping RxMAC timeout!\n", device_xname(sc->sc_dev)); 2116 } 2117 2118 static void 2119 age_init_tx_ring(struct age_softc *sc) 2120 { 2121 struct age_ring_data *rd; 2122 struct age_txdesc *txd; 2123 int i; 2124 2125 sc->age_cdata.age_tx_prod = 0; 2126 sc->age_cdata.age_tx_cons = 0; 2127 sc->age_cdata.age_tx_cnt = 0; 2128 2129 rd = &sc->age_rdata; 2130 memset(rd->age_tx_ring, 0, AGE_TX_RING_SZ); 2131 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2132 txd = &sc->age_cdata.age_txdesc[i]; 2133 txd->tx_desc = &rd->age_tx_ring[i]; 2134 txd->tx_m = NULL; 2135 } 2136 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 2137 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2138 } 2139 2140 static int 2141 age_init_rx_ring(struct age_softc *sc) 2142 { 2143 struct age_ring_data *rd; 2144 struct age_rxdesc *rxd; 2145 int i; 2146 2147 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 2148 rd = &sc->age_rdata; 2149 memset(rd->age_rx_ring, 0, AGE_RX_RING_SZ); 2150 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2151 rxd = &sc->age_cdata.age_rxdesc[i]; 2152 rxd->rx_m = NULL; 2153 rxd->rx_desc = &rd->age_rx_ring[i]; 2154 if (age_newbuf(sc, rxd, 1) != 0) 2155 return ENOBUFS; 2156 } 2157 2158 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 0, 2159 sc->age_cdata.age_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2160 2161 return 0; 2162 } 2163 2164 static void 2165 age_init_rr_ring(struct age_softc *sc) 2166 { 2167 struct age_ring_data *rd; 2168 2169 sc->age_cdata.age_rr_cons = 0; 2170 AGE_RXCHAIN_RESET(sc); 2171 2172 rd = &sc->age_rdata; 2173 memset(rd->age_rr_ring, 0, AGE_RR_RING_SZ); 2174 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 2175 sc->age_cdata.age_rr_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2176 } 2177 2178 static void 2179 age_init_cmb_block(struct age_softc *sc) 2180 { 2181 struct age_ring_data *rd; 2182 2183 rd = &sc->age_rdata; 2184 memset(rd->age_cmb_block, 0, AGE_CMB_BLOCK_SZ); 2185 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 2186 sc->age_cdata.age_cmb_block_map->dm_mapsize, 2187 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2188 } 2189 2190 static void 2191 age_init_smb_block(struct age_softc *sc) 2192 { 2193 struct age_ring_data *rd; 2194 2195 rd = &sc->age_rdata; 2196 memset(rd->age_smb_block, 0, AGE_SMB_BLOCK_SZ); 2197 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2198 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2199 } 2200 2201 static int 2202 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd, int init) 2203 { 2204 struct rx_desc *desc; 2205 struct mbuf *m; 2206 bus_dmamap_t map; 2207 int error; 2208 2209 MGETHDR(m, M_DONTWAIT, MT_DATA); 2210 if (m == NULL) 2211 return ENOBUFS; 2212 MCLGET(m, M_DONTWAIT); 2213 if (!(m->m_flags & M_EXT)) { 2214 m_freem(m); 2215 return ENOBUFS; 2216 } 2217 2218 m->m_len = m->m_pkthdr.len = MCLBYTES; 2219 m_adj(m, ETHER_ALIGN); 2220 2221 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2222 sc->age_cdata.age_rx_sparemap, m, BUS_DMA_NOWAIT); 2223 2224 if (error != 0) { 2225 m_freem(m); 2226 2227 if (init) 2228 printf("%s: can't load RX mbuf\n", device_xname(sc->sc_dev)); 2229 return error; 2230 } 2231 2232 if (rxd->rx_m != NULL) { 2233 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2234 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2235 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2236 } 2237 map = rxd->rx_dmamap; 2238 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 2239 sc->age_cdata.age_rx_sparemap = map; 2240 rxd->rx_m = m; 2241 2242 desc = rxd->rx_desc; 2243 desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 2244 desc->len = 2245 htole32((rxd->rx_dmamap->dm_segs[0].ds_len & AGE_RD_LEN_MASK) << 2246 AGE_RD_LEN_SHIFT); 2247 2248 return 0; 2249 } 2250 2251 static void 2252 age_rxvlan(struct age_softc *sc) 2253 { 2254 uint32_t reg; 2255 2256 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2257 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2258 if (sc->sc_ec.ec_capenable & ETHERCAP_VLAN_HWTAGGING) 2259 reg |= MAC_CFG_VLAN_TAG_STRIP; 2260 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2261 } 2262 2263 static void 2264 age_rxfilter(struct age_softc *sc) 2265 { 2266 struct ethercom *ec = &sc->sc_ec; 2267 struct ifnet *ifp = &sc->sc_ec.ec_if; 2268 struct ether_multi *enm; 2269 struct ether_multistep step; 2270 uint32_t crc; 2271 uint32_t mchash[2]; 2272 uint32_t rxcfg; 2273 2274 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 2275 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2276 ifp->if_flags &= ~IFF_ALLMULTI; 2277 2278 /* 2279 * Always accept broadcast frames. 2280 */ 2281 rxcfg |= MAC_CFG_BCAST; 2282 2283 if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 2284 ifp->if_flags |= IFF_ALLMULTI; 2285 if (ifp->if_flags & IFF_PROMISC) 2286 rxcfg |= MAC_CFG_PROMISC; 2287 else 2288 rxcfg |= MAC_CFG_ALLMULTI; 2289 mchash[0] = mchash[1] = 0xFFFFFFFF; 2290 } else { 2291 /* Program new filter. */ 2292 memset(mchash, 0, sizeof(mchash)); 2293 2294 ETHER_FIRST_MULTI(step, ec, enm); 2295 while (enm != NULL) { 2296 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2297 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2298 ETHER_NEXT_MULTI(step, enm); 2299 } 2300 } 2301 2302 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 2303 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 2304 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 2305 } 2306
Indexes created Fri Oct 03 02:09:57 GMT 2025