if_age.c revision 1.6.2.2
1 /* $NetBSD: if_age.c,v 1.6.2.2 2009/01/17 13:28:59 mjf Exp $ */ 2 /* $OpenBSD: if_age.c,v 1.1 2009/01/16 05:00:34 kevlo Exp $ */ 3 4 /*- 5 * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: if_age.c,v 1.6.2.2 2009/01/17 13:28:59 mjf Exp $"); 35 36 #include "bpfilter.h" 37 #include "vlan.h" 38 39 #include <sys/param.h> 40 #include <sys/proc.h> 41 #include <sys/endian.h> 42 #include <sys/systm.h> 43 #include <sys/types.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/queue.h> 47 #include <sys/kernel.h> 48 #include <sys/device.h> 49 #include <sys/callout.h> 50 #include <sys/socket.h> 51 52 #include <net/if.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #ifdef INET 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/in_var.h> 61 #include <netinet/ip.h> 62 #endif 63 64 #include <net/if_types.h> 65 #include <net/if_vlanvar.h> 66 67 #if NBPFILTER > 0 68 #include <net/bpf.h> 69 #endif 70 71 #include <sys/rnd.h> 72 73 #include <dev/mii/mii.h> 74 #include <dev/mii/miivar.h> 75 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/pcidevs.h> 79 80 #include <dev/pci/if_agereg.h> 81 82 static int age_match(device_t, cfdata_t, void *); 83 static void age_attach(device_t, device_t, void *); 84 static int age_detach(device_t, int); 85 86 static bool age_resume(device_t PMF_FN_PROTO); 87 88 static int age_miibus_readreg(device_t, int, int); 89 static void age_miibus_writereg(device_t, int, int, int); 90 static void age_miibus_statchg(device_t); 91 92 static int age_init(struct ifnet *); 93 static int age_ioctl(struct ifnet *, u_long, void *); 94 static void age_start(struct ifnet *); 95 static void age_watchdog(struct ifnet *); 96 static void age_mediastatus(struct ifnet *, struct ifmediareq *); 97 static int age_mediachange(struct ifnet *); 98 99 static int age_intr(void *); 100 static int age_read_vpd_word(struct age_softc *, uint32_t, uint32_t, uint32_t *); 101 static int age_dma_alloc(struct age_softc *); 102 static void age_dma_free(struct age_softc *); 103 static void age_get_macaddr(struct age_softc *, uint8_t[]); 104 static void age_phy_reset(struct age_softc *); 105 106 static int age_encap(struct age_softc *, struct mbuf **); 107 static void age_init_tx_ring(struct age_softc *); 108 static int age_init_rx_ring(struct age_softc *); 109 static void age_init_rr_ring(struct age_softc *); 110 static void age_init_cmb_block(struct age_softc *); 111 static void age_init_smb_block(struct age_softc *); 112 static int age_newbuf(struct age_softc *, struct age_rxdesc *, int); 113 static void age_mac_config(struct age_softc *); 114 static void age_txintr(struct age_softc *, int); 115 static void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 116 static void age_rxintr(struct age_softc *, int); 117 static void age_tick(void *); 118 static void age_reset(struct age_softc *); 119 static void age_stop(struct age_softc *); 120 static void age_stats_update(struct age_softc *); 121 static void age_stop_txmac(struct age_softc *); 122 static void age_stop_rxmac(struct age_softc *); 123 static void age_rxvlan(struct age_softc *sc); 124 static void age_rxfilter(struct age_softc *); 125 126 CFATTACH_DECL_NEW(age, sizeof(struct age_softc), 127 age_match, age_attach, age_detach, NULL); 128 129 int agedebug = 0; 130 #define DPRINTF(x) do { if (agedebug) printf x; } while (0) 131 132 #define AGE_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 133 134 static int 135 age_match(device_t dev, cfdata_t match, void *aux) 136 { 137 struct pci_attach_args *pa = aux; 138 139 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && 140 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_GIGA); 141 } 142 143 static void 144 age_attach(device_t parent, device_t self, void *aux) 145 { 146 struct age_softc *sc = device_private(self); 147 struct pci_attach_args *pa = aux; 148 pci_intr_handle_t ih; 149 const char *intrstr; 150 struct ifnet *ifp = &sc->sc_ec.ec_if; 151 pcireg_t memtype; 152 int error = 0; 153 154 aprint_naive("\n"); 155 aprint_normal(": Attansic/Atheros L1 Gigabit Ethernet\n"); 156 157 sc->sc_dev = self; 158 sc->sc_dmat = pa->pa_dmat; 159 sc->sc_pct = pa->pa_pc; 160 sc->sc_pcitag = pa->pa_tag; 161 162 /* 163 * Allocate IO memory 164 */ 165 memtype = pci_mapreg_type(sc->sc_pct, sc->sc_pcitag, AGE_PCIR_BAR); 166 switch (memtype) { 167 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 168 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 169 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 170 break; 171 default: 172 aprint_error_dev(self, "invalid base address register\n"); 173 break; 174 } 175 176 if (pci_mapreg_map(pa, AGE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 177 &sc->sc_mem_bh, NULL, &sc->sc_mem_size) != 0) { 178 aprint_error_dev(self, "could not map mem space\n"); 179 return; 180 } 181 182 if (pci_intr_map(pa, &ih) != 0) { 183 aprint_error_dev(self, "could not map interrupt\n"); 184 return; 185 } 186 187 /* 188 * Allocate IRQ 189 */ 190 intrstr = pci_intr_string(sc->sc_pct, ih); 191 sc->sc_irq_handle = pci_intr_establish(sc->sc_pct, ih, IPL_NET, 192 age_intr, sc); 193 if (sc->sc_irq_handle == NULL) { 194 aprint_error_dev(self, "could not establish interrupt"); 195 if (intrstr != NULL) 196 aprint_error(" at %s", intrstr); 197 aprint_error("\n"); 198 return; 199 } 200 aprint_normal_dev(self, "%s", intrstr); 201 202 /* Set PHY address. */ 203 sc->age_phyaddr = AGE_PHY_ADDR; 204 205 /* Reset PHY. */ 206 age_phy_reset(sc); 207 208 /* Reset the ethernet controller. */ 209 age_reset(sc); 210 211 /* Get PCI and chip id/revision. */ 212 sc->age_rev = PCI_REVISION(pa->pa_class); 213 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 214 MASTER_CHIP_REV_SHIFT; 215 216 aprint_debug_dev(self, "PCI device revision : 0x%04x\n", sc->age_rev); 217 aprint_debug_dev(self, "Chip id/revision : 0x%04x\n", sc->age_chip_rev); 218 219 if (agedebug) { 220 aprint_debug_dev(self, "%d Tx FIFO, %d Rx FIFO\n", 221 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 222 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 223 } 224 225 /* Set max allowable DMA size. */ 226 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 227 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 228 229 /* Allocate DMA stuffs */ 230 error = age_dma_alloc(sc); 231 if (error) 232 goto fail; 233 234 callout_init(&sc->sc_tick_ch, 0); 235 callout_setfunc(&sc->sc_tick_ch, age_tick, sc); 236 237 /* Load station address. */ 238 age_get_macaddr(sc, sc->sc_enaddr); 239 240 aprint_normal_dev(self, "Ethernet address %s\n", 241 ether_sprintf(sc->sc_enaddr)); 242 243 ifp->if_softc = sc; 244 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 245 ifp->if_init = age_init; 246 ifp->if_ioctl = age_ioctl; 247 ifp->if_start = age_start; 248 ifp->if_watchdog = age_watchdog; 249 ifp->if_baudrate = IF_Gbps(1); 250 IFQ_SET_MAXLEN(&ifp->if_snd, AGE_TX_RING_CNT - 1); 251 IFQ_SET_READY(&ifp->if_snd); 252 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 253 254 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 255 256 #ifdef AGE_CHECKSUM 257 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 258 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 259 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 260 #endif 261 262 #if NVLAN > 0 263 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 264 #endif 265 266 /* Set up MII bus. */ 267 sc->sc_miibus.mii_ifp = ifp; 268 sc->sc_miibus.mii_readreg = age_miibus_readreg; 269 sc->sc_miibus.mii_writereg = age_miibus_writereg; 270 sc->sc_miibus.mii_statchg = age_miibus_statchg; 271 272 ifmedia_init(&sc->sc_miibus.mii_media, 0, age_mediachange, 273 age_mediastatus); 274 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 275 MII_OFFSET_ANY, 0); 276 277 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 278 aprint_error_dev(self, "no PHY found!\n"); 279 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 280 0, NULL); 281 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 282 } else 283 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 284 285 if_attach(ifp); 286 ether_ifattach(ifp, sc->sc_enaddr); 287 288 if (!pmf_device_register(self, NULL, age_resume)) 289 aprint_error_dev(self, "couldn't establish power handler\n"); 290 else 291 pmf_class_network_register(self, ifp); 292 293 return; 294 fail: 295 age_detach(sc->sc_dev, 0); 296 } 297 298 static int 299 age_detach(device_t self, int flags) 300 { 301 struct age_softc *sc = device_private(self); 302 struct ifnet *ifp = &sc->sc_ec.ec_if; 303 int s; 304 305 s = splnet(); 306 age_stop(sc); 307 splx(s); 308 309 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 310 311 /* Delete all remaining media. */ 312 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 313 314 ether_ifdetach(ifp); 315 if_detach(ifp); 316 age_dma_free(sc); 317 318 if (sc->sc_irq_handle != NULL) { 319 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 320 sc->sc_irq_handle = NULL; 321 } 322 323 return (0); 324 } 325 326 /* 327 * Read a PHY register on the MII of the L1. 328 */ 329 static int 330 age_miibus_readreg(struct device *dev, int phy, int reg) 331 { 332 struct age_softc *sc = device_private(dev); 333 uint32_t v; 334 int i; 335 336 if (phy != sc->age_phyaddr) 337 return (0); 338 339 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 340 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 341 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 342 DELAY(1); 343 v = CSR_READ_4(sc, AGE_MDIO); 344 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 345 break; 346 } 347 348 if (i == 0) { 349 printf("%s: phy read timeout: phy %d, reg %d\n", 350 device_xname(sc->sc_dev), phy, reg); 351 return (0); 352 } 353 354 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 355 } 356 357 /* 358 * Write a PHY register on the MII of the L1. 359 */ 360 static void 361 age_miibus_writereg(struct device *dev, int phy, int reg, int val) 362 { 363 struct age_softc *sc = device_private(dev); 364 uint32_t v; 365 int i; 366 367 if (phy != sc->age_phyaddr) 368 return; 369 370 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 371 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 372 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 373 374 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 375 DELAY(1); 376 v = CSR_READ_4(sc, AGE_MDIO); 377 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 378 break; 379 } 380 381 if (i == 0) { 382 printf("%s: phy write timeout: phy %d, reg %d\n", 383 device_xname(sc->sc_dev), phy, reg); 384 } 385 } 386 387 /* 388 * Callback from MII layer when media changes. 389 */ 390 static void 391 age_miibus_statchg(device_t dev) 392 { 393 struct age_softc *sc = device_private(dev); 394 struct ifnet *ifp = &sc->sc_ec.ec_if; 395 struct mii_data *mii; 396 397 if ((ifp->if_flags & IFF_RUNNING) == 0) 398 return; 399 400 mii = &sc->sc_miibus; 401 402 sc->age_flags &= ~AGE_FLAG_LINK; 403 if ((mii->mii_media_status & IFM_AVALID) != 0) { 404 switch (IFM_SUBTYPE(mii->mii_media_active)) { 405 case IFM_10_T: 406 case IFM_100_TX: 407 case IFM_1000_T: 408 sc->age_flags |= AGE_FLAG_LINK; 409 break; 410 default: 411 break; 412 } 413 } 414 415 /* Stop Rx/Tx MACs. */ 416 age_stop_rxmac(sc); 417 age_stop_txmac(sc); 418 419 /* Program MACs with resolved speed/duplex/flow-control. */ 420 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 421 uint32_t reg; 422 423 age_mac_config(sc); 424 reg = CSR_READ_4(sc, AGE_MAC_CFG); 425 /* Restart DMA engine and Tx/Rx MAC. */ 426 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 427 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 428 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 429 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 430 } 431 } 432 433 /* 434 * Get the current interface media status. 435 */ 436 static void 437 age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 438 { 439 struct age_softc *sc = ifp->if_softc; 440 struct mii_data *mii = &sc->sc_miibus; 441 442 mii_pollstat(mii); 443 ifmr->ifm_status = mii->mii_media_status; 444 ifmr->ifm_active = mii->mii_media_active; 445 } 446 447 /* 448 * Set hardware to newly-selected media. 449 */ 450 static int 451 age_mediachange(struct ifnet *ifp) 452 { 453 struct age_softc *sc = ifp->if_softc; 454 struct mii_data *mii = &sc->sc_miibus; 455 int error; 456 457 if (mii->mii_instance != 0) { 458 struct mii_softc *miisc; 459 460 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 461 mii_phy_reset(miisc); 462 } 463 error = mii_mediachg(mii); 464 465 return (error); 466 } 467 468 static int 469 age_intr(void *arg) 470 { 471 struct age_softc *sc = arg; 472 struct ifnet *ifp = &sc->sc_ec.ec_if; 473 struct cmb *cmb; 474 uint32_t status; 475 476 status = CSR_READ_4(sc, AGE_INTR_STATUS); 477 if (status == 0 || (status & AGE_INTRS) == 0) 478 return (0); 479 480 /* Disable interrupts. */ 481 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 482 483 cmb = sc->age_rdata.age_cmb_block; 484 485 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 486 sc->age_cdata.age_cmb_block_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 487 status = le32toh(cmb->intr_status); 488 if ((status & AGE_INTRS) == 0) 489 goto back; 490 491 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 492 TPD_CONS_SHIFT; 493 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 494 RRD_PROD_SHIFT; 495 496 /* Let hardware know CMB was served. */ 497 cmb->intr_status = 0; 498 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 499 sc->age_cdata.age_cmb_block_map->dm_mapsize, 500 BUS_DMASYNC_PREWRITE); 501 502 if (ifp->if_flags & IFF_RUNNING) { 503 if (status & INTR_CMB_RX) 504 age_rxintr(sc, sc->age_rr_prod); 505 506 if (status & INTR_CMB_TX) 507 age_txintr(sc, sc->age_tpd_cons); 508 509 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 510 if (status & INTR_DMA_RD_TO_RST) 511 printf("%s: DMA read error! -- resetting\n", 512 device_xname(sc->sc_dev)); 513 if (status & INTR_DMA_WR_TO_RST) 514 printf("%s: DMA write error! -- resetting\n", 515 device_xname(sc->sc_dev)); 516 age_init(ifp); 517 } 518 519 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 520 age_start(ifp); 521 522 if (status & INTR_SMB) 523 age_stats_update(sc); 524 } 525 526 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 527 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 528 sc->age_cdata.age_cmb_block_map->dm_mapsize, 529 BUS_DMASYNC_POSTREAD); 530 531 back: 532 /* Re-enable interrupts. */ 533 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 534 535 return (1); 536 } 537 538 static int 539 age_read_vpd_word(struct age_softc *sc, uint32_t vpdc, uint32_t offset, 540 uint32_t *word) 541 { 542 int i; 543 pcireg_t rv; 544 545 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_VPD_ADDRESS(vpdc), 546 offset << PCI_VPD_ADDRESS_SHIFT); 547 for (i = AGE_TIMEOUT; i > 0; i--) { 548 DELAY(10); 549 rv = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 550 PCI_VPD_ADDRESS(vpdc)); 551 if ((rv & PCI_VPD_OPFLAG) == PCI_VPD_OPFLAG) 552 break; 553 } 554 if (i == 0) { 555 printf("%s: VPD read timeout!\n", device_xname(sc->sc_dev)); 556 *word = 0; 557 return ETIMEDOUT; 558 } 559 560 *word = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_VPD_DATAREG(vpdc)); 561 return 0; 562 } 563 564 static void 565 age_get_macaddr(struct age_softc *sc, uint8_t eaddr[]) 566 { 567 uint32_t ea[2], off, reg, word; 568 int vpd_error, match, vpdc; 569 570 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 571 if ((reg & SPI_VPD_ENB) != 0) { 572 /* Get VPD stored in TWSI EEPROM. */ 573 reg &= ~SPI_VPD_ENB; 574 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 575 } 576 577 vpd_error = 0; 578 ea[0] = ea[1] = 0; 579 if ((vpd_error = pci_get_capability(sc->sc_pct, sc->sc_pcitag, 580 PCI_CAP_VPD, &vpdc, NULL))) { 581 /* 582 * PCI VPD capability exists, but it seems that it's 583 * not in the standard form as stated in PCI VPD 584 * specification such that driver could not use 585 * pci_get_vpd_readonly(9) with keyword 'NA'. 586 * Search VPD data starting at address 0x0100. The data 587 * should be used as initializers to set AGE_PAR0, 588 * AGE_PAR1 register including other PCI configuration 589 * registers. 590 */ 591 word = 0; 592 match = 0; 593 reg = 0; 594 for (off = AGE_VPD_REG_CONF_START; off < AGE_VPD_REG_CONF_END; 595 off += sizeof(uint32_t)) { 596 vpd_error = age_read_vpd_word(sc, vpdc, off, &word); 597 if (vpd_error != 0) 598 break; 599 if (match != 0) { 600 switch (reg) { 601 case AGE_PAR0: 602 ea[0] = word; 603 break; 604 case AGE_PAR1: 605 ea[1] = word; 606 break; 607 default: 608 break; 609 } 610 match = 0; 611 } else if ((word & 0xFF) == AGE_VPD_REG_CONF_SIG) { 612 match = 1; 613 reg = word >> 16; 614 } else 615 break; 616 } 617 if (off >= AGE_VPD_REG_CONF_END) 618 vpd_error = ENOENT; 619 if (vpd_error == 0) { 620 /* 621 * Don't blindly trust ethernet address obtained 622 * from VPD. Check whether ethernet address is 623 * valid one. Otherwise fall-back to reading 624 * PAR register. 625 */ 626 ea[1] &= 0xFFFF; 627 if ((ea[0] == 0 && ea[1] == 0) || 628 (ea[0] == 0xFFFFFFFF && ea[1] == 0xFFFF)) { 629 if (agedebug) 630 printf("%s: invalid ethernet address " 631 "returned from VPD.\n", 632 device_xname(sc->sc_dev)); 633 vpd_error = EINVAL; 634 } 635 } 636 if (vpd_error != 0 && (agedebug)) 637 printf("%s: VPD access failure!\n", 638 device_xname(sc->sc_dev)); 639 } else { 640 if (agedebug) 641 printf("%s: PCI VPD capability not found!\n", 642 device_xname(sc->sc_dev)); 643 } 644 645 /* 646 * It seems that L1 also provides a way to extract ethernet 647 * address via SPI flash interface. Because SPI flash memory 648 * device of different vendors vary in their instruction 649 * codes for read ID instruction, it's very hard to get 650 * instructions codes without detailed information for the 651 * flash memory device used on ethernet controller. To simplify 652 * code, just read AGE_PAR0/AGE_PAR1 register to get ethernet 653 * address which is supposed to be set by hardware during 654 * power on reset. 655 */ 656 if (vpd_error != 0) { 657 /* 658 * VPD is mapped to SPI flash memory or BIOS set it. 659 */ 660 ea[0] = CSR_READ_4(sc, AGE_PAR0); 661 ea[1] = CSR_READ_4(sc, AGE_PAR1); 662 } 663 664 ea[1] &= 0xFFFF; 665 eaddr[0] = (ea[1] >> 8) & 0xFF; 666 eaddr[1] = (ea[1] >> 0) & 0xFF; 667 eaddr[2] = (ea[0] >> 24) & 0xFF; 668 eaddr[3] = (ea[0] >> 16) & 0xFF; 669 eaddr[4] = (ea[0] >> 8) & 0xFF; 670 eaddr[5] = (ea[0] >> 0) & 0xFF; 671 } 672 673 static void 674 age_phy_reset(struct age_softc *sc) 675 { 676 /* Reset PHY. */ 677 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 678 DELAY(1000); 679 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 680 DELAY(1000); 681 } 682 683 static int 684 age_dma_alloc(struct age_softc *sc) 685 { 686 struct age_txdesc *txd; 687 struct age_rxdesc *rxd; 688 int nsegs, error, i; 689 690 /* 691 * Create DMA stuffs for TX ring 692 */ 693 error = bus_dmamap_create(sc->sc_dmat, AGE_TX_RING_SZ, 1, 694 AGE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_tx_ring_map); 695 if (error) 696 return (ENOBUFS); 697 698 /* Allocate DMA'able memory for TX ring */ 699 error = bus_dmamem_alloc(sc->sc_dmat, AGE_TX_RING_SZ, 700 PAGE_SIZE, 0, &sc->age_rdata.age_tx_ring_seg, 1, 701 &nsegs, BUS_DMA_WAITOK); 702 if (error) { 703 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 704 device_xname(sc->sc_dev)); 705 return error; 706 } 707 708 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_tx_ring_seg, 709 nsegs, AGE_TX_RING_SZ, (void **)&sc->age_rdata.age_tx_ring, 710 BUS_DMA_NOWAIT); 711 if (error) 712 return (ENOBUFS); 713 714 memset(sc->age_rdata.age_tx_ring, 0, AGE_TX_RING_SZ); 715 716 /* Load the DMA map for Tx ring. */ 717 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 718 sc->age_rdata.age_tx_ring, AGE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 719 if (error) { 720 printf("%s: could not load DMA'able memory for Tx ring.\n", 721 device_xname(sc->sc_dev)); 722 bus_dmamem_free(sc->sc_dmat, 723 (bus_dma_segment_t *)&sc->age_rdata.age_tx_ring, 1); 724 return error; 725 } 726 727 sc->age_rdata.age_tx_ring_paddr = 728 sc->age_cdata.age_tx_ring_map->dm_segs[0].ds_addr; 729 730 /* 731 * Create DMA stuffs for RX ring 732 */ 733 error = bus_dmamap_create(sc->sc_dmat, AGE_RX_RING_SZ, 1, 734 AGE_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_ring_map); 735 if (error) 736 return (ENOBUFS); 737 738 /* Allocate DMA'able memory for RX ring */ 739 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RX_RING_SZ, 740 PAGE_SIZE, 0, &sc->age_rdata.age_rx_ring_seg, 1, 741 &nsegs, BUS_DMA_WAITOK); 742 if (error) { 743 printf("%s: could not allocate DMA'able memory for Rx ring.\n", 744 device_xname(sc->sc_dev)); 745 return error; 746 } 747 748 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rx_ring_seg, 749 nsegs, AGE_RX_RING_SZ, (void **)&sc->age_rdata.age_rx_ring, 750 BUS_DMA_NOWAIT); 751 if (error) 752 return (ENOBUFS); 753 754 memset(sc->age_rdata.age_rx_ring, 0, AGE_RX_RING_SZ); 755 756 /* Load the DMA map for Rx ring. */ 757 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 758 sc->age_rdata.age_rx_ring, AGE_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 759 if (error) { 760 printf("%s: could not load DMA'able memory for Rx ring.\n", 761 device_xname(sc->sc_dev)); 762 bus_dmamem_free(sc->sc_dmat, 763 (bus_dma_segment_t *)sc->age_rdata.age_rx_ring, 1); 764 return error; 765 } 766 767 sc->age_rdata.age_rx_ring_paddr = 768 sc->age_cdata.age_rx_ring_map->dm_segs[0].ds_addr; 769 770 /* 771 * Create DMA stuffs for RX return ring 772 */ 773 error = bus_dmamap_create(sc->sc_dmat, AGE_RR_RING_SZ, 1, 774 AGE_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rr_ring_map); 775 if (error) 776 return (ENOBUFS); 777 778 /* Allocate DMA'able memory for RX return ring */ 779 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RR_RING_SZ, 780 PAGE_SIZE, 0, &sc->age_rdata.age_rr_ring_seg, 1, 781 &nsegs, BUS_DMA_WAITOK); 782 if (error) { 783 printf("%s: could not allocate DMA'able memory for Rx " 784 "return ring.\n", device_xname(sc->sc_dev)); 785 return error; 786 } 787 788 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rr_ring_seg, 789 nsegs, AGE_RR_RING_SZ, (void **)&sc->age_rdata.age_rr_ring, 790 BUS_DMA_NOWAIT); 791 if (error) 792 return (ENOBUFS); 793 794 memset(sc->age_rdata.age_rr_ring, 0, AGE_RR_RING_SZ); 795 796 /* Load the DMA map for Rx return ring. */ 797 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 798 sc->age_rdata.age_rr_ring, AGE_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 799 if (error) { 800 printf("%s: could not load DMA'able memory for Rx return ring." 801 "\n", device_xname(sc->sc_dev)); 802 bus_dmamem_free(sc->sc_dmat, 803 (bus_dma_segment_t *)&sc->age_rdata.age_rr_ring, 1); 804 return error; 805 } 806 807 sc->age_rdata.age_rr_ring_paddr = 808 sc->age_cdata.age_rr_ring_map->dm_segs[0].ds_addr; 809 810 /* 811 * Create DMA stuffs for CMB block 812 */ 813 error = bus_dmamap_create(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 1, 814 AGE_CMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 815 &sc->age_cdata.age_cmb_block_map); 816 if (error) 817 return (ENOBUFS); 818 819 /* Allocate DMA'able memory for CMB block */ 820 error = bus_dmamem_alloc(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 821 PAGE_SIZE, 0, &sc->age_rdata.age_cmb_block_seg, 1, 822 &nsegs, BUS_DMA_WAITOK); 823 if (error) { 824 printf("%s: could not allocate DMA'able memory for " 825 "CMB block\n", device_xname(sc->sc_dev)); 826 return error; 827 } 828 829 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_cmb_block_seg, 830 nsegs, AGE_CMB_BLOCK_SZ, (void **)&sc->age_rdata.age_cmb_block, 831 BUS_DMA_NOWAIT); 832 if (error) 833 return (ENOBUFS); 834 835 memset(sc->age_rdata.age_cmb_block, 0, AGE_CMB_BLOCK_SZ); 836 837 /* Load the DMA map for CMB block. */ 838 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 839 sc->age_rdata.age_cmb_block, AGE_CMB_BLOCK_SZ, NULL, 840 BUS_DMA_WAITOK); 841 if (error) { 842 printf("%s: could not load DMA'able memory for CMB block\n", 843 device_xname(sc->sc_dev)); 844 bus_dmamem_free(sc->sc_dmat, 845 (bus_dma_segment_t *)&sc->age_rdata.age_cmb_block, 1); 846 return error; 847 } 848 849 sc->age_rdata.age_cmb_block_paddr = 850 sc->age_cdata.age_cmb_block_map->dm_segs[0].ds_addr; 851 852 /* 853 * Create DMA stuffs for SMB block 854 */ 855 error = bus_dmamap_create(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 1, 856 AGE_SMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 857 &sc->age_cdata.age_smb_block_map); 858 if (error) 859 return (ENOBUFS); 860 861 /* Allocate DMA'able memory for SMB block */ 862 error = bus_dmamem_alloc(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 863 PAGE_SIZE, 0, &sc->age_rdata.age_smb_block_seg, 1, 864 &nsegs, BUS_DMA_WAITOK); 865 if (error) { 866 printf("%s: could not allocate DMA'able memory for " 867 "SMB block\n", device_xname(sc->sc_dev)); 868 return error; 869 } 870 871 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_smb_block_seg, 872 nsegs, AGE_SMB_BLOCK_SZ, (void **)&sc->age_rdata.age_smb_block, 873 BUS_DMA_NOWAIT); 874 if (error) 875 return (ENOBUFS); 876 877 memset(sc->age_rdata.age_smb_block, 0, AGE_SMB_BLOCK_SZ); 878 879 /* Load the DMA map for SMB block */ 880 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 881 sc->age_rdata.age_smb_block, AGE_SMB_BLOCK_SZ, NULL, 882 BUS_DMA_WAITOK); 883 if (error) { 884 printf("%s: could not load DMA'able memory for SMB block\n", 885 device_xname(sc->sc_dev)); 886 bus_dmamem_free(sc->sc_dmat, 887 (bus_dma_segment_t *)&sc->age_rdata.age_smb_block, 1); 888 return error; 889 } 890 891 sc->age_rdata.age_smb_block_paddr = 892 sc->age_cdata.age_smb_block_map->dm_segs[0].ds_addr; 893 894 /* Create DMA maps for Tx buffers. */ 895 for (i = 0; i < AGE_TX_RING_CNT; i++) { 896 txd = &sc->age_cdata.age_txdesc[i]; 897 txd->tx_m = NULL; 898 txd->tx_dmamap = NULL; 899 error = bus_dmamap_create(sc->sc_dmat, AGE_TSO_MAXSIZE, 900 AGE_MAXTXSEGS, AGE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 901 &txd->tx_dmamap); 902 if (error) { 903 printf("%s: could not create Tx dmamap.\n", 904 device_xname(sc->sc_dev)); 905 return error; 906 } 907 } 908 909 /* Create DMA maps for Rx buffers. */ 910 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 911 BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_sparemap); 912 if (error) { 913 printf("%s: could not create spare Rx dmamap.\n", 914 device_xname(sc->sc_dev)); 915 return error; 916 } 917 for (i = 0; i < AGE_RX_RING_CNT; i++) { 918 rxd = &sc->age_cdata.age_rxdesc[i]; 919 rxd->rx_m = NULL; 920 rxd->rx_dmamap = NULL; 921 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 922 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 923 if (error) { 924 printf("%s: could not create Rx dmamap.\n", 925 device_xname(sc->sc_dev)); 926 return error; 927 } 928 } 929 930 return (0); 931 } 932 933 static void 934 age_dma_free(struct age_softc *sc) 935 { 936 struct age_txdesc *txd; 937 struct age_rxdesc *rxd; 938 int i; 939 940 /* Tx buffers */ 941 for (i = 0; i < AGE_TX_RING_CNT; i++) { 942 txd = &sc->age_cdata.age_txdesc[i]; 943 if (txd->tx_dmamap != NULL) { 944 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 945 txd->tx_dmamap = NULL; 946 } 947 } 948 /* Rx buffers */ 949 for (i = 0; i < AGE_RX_RING_CNT; i++) { 950 rxd = &sc->age_cdata.age_rxdesc[i]; 951 if (rxd->rx_dmamap != NULL) { 952 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 953 rxd->rx_dmamap = NULL; 954 } 955 } 956 if (sc->age_cdata.age_rx_sparemap != NULL) { 957 bus_dmamap_destroy(sc->sc_dmat, sc->age_cdata.age_rx_sparemap); 958 sc->age_cdata.age_rx_sparemap = NULL; 959 } 960 961 /* Tx ring. */ 962 if (sc->age_cdata.age_tx_ring_map != NULL) 963 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_tx_ring_map); 964 if (sc->age_cdata.age_tx_ring_map != NULL && 965 sc->age_rdata.age_tx_ring != NULL) 966 bus_dmamem_free(sc->sc_dmat, 967 (bus_dma_segment_t *)sc->age_rdata.age_tx_ring, 1); 968 sc->age_rdata.age_tx_ring = NULL; 969 sc->age_cdata.age_tx_ring_map = NULL; 970 971 /* Rx ring. */ 972 if (sc->age_cdata.age_rx_ring_map != NULL) 973 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rx_ring_map); 974 if (sc->age_cdata.age_rx_ring_map != NULL && 975 sc->age_rdata.age_rx_ring != NULL) 976 bus_dmamem_free(sc->sc_dmat, 977 (bus_dma_segment_t *)sc->age_rdata.age_rx_ring, 1); 978 sc->age_rdata.age_rx_ring = NULL; 979 sc->age_cdata.age_rx_ring_map = NULL; 980 981 /* Rx return ring. */ 982 if (sc->age_cdata.age_rr_ring_map != NULL) 983 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rr_ring_map); 984 if (sc->age_cdata.age_rr_ring_map != NULL && 985 sc->age_rdata.age_rr_ring != NULL) 986 bus_dmamem_free(sc->sc_dmat, 987 (bus_dma_segment_t *)sc->age_rdata.age_rr_ring, 1); 988 sc->age_rdata.age_rr_ring = NULL; 989 sc->age_cdata.age_rr_ring_map = NULL; 990 991 /* CMB block */ 992 if (sc->age_cdata.age_cmb_block_map != NULL) 993 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_cmb_block_map); 994 if (sc->age_cdata.age_cmb_block_map != NULL && 995 sc->age_rdata.age_cmb_block != NULL) 996 bus_dmamem_free(sc->sc_dmat, 997 (bus_dma_segment_t *)sc->age_rdata.age_cmb_block, 1); 998 sc->age_rdata.age_cmb_block = NULL; 999 sc->age_cdata.age_cmb_block_map = NULL; 1000 1001 /* SMB block */ 1002 if (sc->age_cdata.age_smb_block_map != NULL) 1003 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_smb_block_map); 1004 if (sc->age_cdata.age_smb_block_map != NULL && 1005 sc->age_rdata.age_smb_block != NULL) 1006 bus_dmamem_free(sc->sc_dmat, 1007 (bus_dma_segment_t *)sc->age_rdata.age_smb_block, 1); 1008 } 1009 1010 static void 1011 age_start(struct ifnet *ifp) 1012 { 1013 struct age_softc *sc = ifp->if_softc; 1014 struct mbuf *m_head; 1015 int enq; 1016 1017 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1018 return; 1019 1020 enq = 0; 1021 for (;;) { 1022 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1023 if (m_head == NULL) 1024 break; 1025 1026 /* 1027 * Pack the data into the transmit ring. If we 1028 * don't have room, set the OACTIVE flag and wait 1029 * for the NIC to drain the ring. 1030 */ 1031 if (age_encap(sc, &m_head)) { 1032 if (m_head == NULL) 1033 break; 1034 ifp->if_flags |= IFF_OACTIVE; 1035 break; 1036 } 1037 enq = 1; 1038 1039 #if NBPFILTER > 0 1040 /* 1041 * If there's a BPF listener, bounce a copy of this frame 1042 * to him. 1043 */ 1044 if (ifp->if_bpf != NULL) 1045 bpf_mtap(ifp->if_bpf, m_head); 1046 #endif 1047 } 1048 1049 if (enq) { 1050 /* Update mbox. */ 1051 AGE_COMMIT_MBOX(sc); 1052 /* Set a timeout in case the chip goes out to lunch. */ 1053 ifp->if_timer = AGE_TX_TIMEOUT; 1054 } 1055 } 1056 1057 static void 1058 age_watchdog(struct ifnet *ifp) 1059 { 1060 struct age_softc *sc = ifp->if_softc; 1061 1062 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1063 printf("%s: watchdog timeout (missed link)\n", 1064 device_xname(sc->sc_dev)); 1065 ifp->if_oerrors++; 1066 age_init(ifp); 1067 return; 1068 } 1069 1070 if (sc->age_cdata.age_tx_cnt == 0) { 1071 printf("%s: watchdog timeout (missed Tx interrupts) " 1072 "-- recovering\n", device_xname(sc->sc_dev)); 1073 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1074 age_start(ifp); 1075 return; 1076 } 1077 1078 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1079 ifp->if_oerrors++; 1080 age_init(ifp); 1081 1082 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1083 age_start(ifp); 1084 } 1085 1086 static int 1087 age_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1088 { 1089 struct age_softc *sc = ifp->if_softc; 1090 struct mii_data *mii = &sc->sc_miibus; 1091 struct ifreq *ifr = (struct ifreq *)data; 1092 int s, error = 0; 1093 1094 s = splnet(); 1095 1096 switch (cmd) { 1097 case SIOCSIFADDR: 1098 ifp->if_flags |= IFF_UP; 1099 if (!(ifp->if_flags & IFF_RUNNING)) 1100 age_init(ifp); 1101 #ifdef INET 1102 if (ifa->ifa_addr->sa_family == AF_INET) 1103 arp_ifinit(&sc->sc_ec, ifa); 1104 #endif 1105 break; 1106 1107 case SIOCSIFFLAGS: 1108 error = ifioctl_common(ifp, cmd, data); 1109 if (error) 1110 break; 1111 if (ifp->if_flags & IFF_UP) { 1112 if (ifp->if_flags & IFF_RUNNING) 1113 age_rxfilter(sc); 1114 else 1115 age_init(ifp); 1116 } else { 1117 if (ifp->if_flags & IFF_RUNNING) 1118 age_stop(sc); 1119 } 1120 sc->age_if_flags = ifp->if_flags; 1121 break; 1122 1123 case SIOCADDMULTI: 1124 case SIOCDELMULTI: 1125 error = ether_ioctl(ifp, cmd, data); 1126 break; 1127 1128 case SIOCSIFMEDIA: 1129 case SIOCGIFMEDIA: 1130 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1131 break; 1132 default: 1133 error = ether_ioctl(ifp, cmd, data); 1134 break; 1135 } 1136 1137 if (error == ENETRESET) { 1138 if (ifp->if_flags & IFF_RUNNING) 1139 age_rxfilter(sc); 1140 error = 0; 1141 } 1142 1143 splx(s); 1144 return (error); 1145 } 1146 1147 static void 1148 age_mac_config(struct age_softc *sc) 1149 { 1150 struct mii_data *mii; 1151 uint32_t reg; 1152 1153 mii = &sc->sc_miibus; 1154 1155 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1156 reg &= ~MAC_CFG_FULL_DUPLEX; 1157 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1158 reg &= ~MAC_CFG_SPEED_MASK; 1159 1160 /* Reprogram MAC with resolved speed/duplex. */ 1161 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1162 case IFM_10_T: 1163 case IFM_100_TX: 1164 reg |= MAC_CFG_SPEED_10_100; 1165 break; 1166 case IFM_1000_T: 1167 reg |= MAC_CFG_SPEED_1000; 1168 break; 1169 } 1170 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1171 reg |= MAC_CFG_FULL_DUPLEX; 1172 #ifdef notyet 1173 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1174 reg |= MAC_CFG_TX_FC; 1175 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1176 reg |= MAC_CFG_RX_FC; 1177 #endif 1178 } 1179 1180 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1181 } 1182 1183 static bool 1184 age_resume(device_t dv PMF_FN_ARGS) 1185 { 1186 struct age_softc *sc = device_private(dv); 1187 uint16_t cmd; 1188 1189 /* 1190 * Clear INTx emulation disable for hardware that 1191 * is set in resume event. From Linux. 1192 */ 1193 cmd = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 1194 if ((cmd & 0x0400) != 0) { 1195 cmd &= ~0x0400; 1196 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 1197 PCI_COMMAND_STATUS_REG, cmd); 1198 } 1199 1200 return true; 1201 } 1202 1203 static int 1204 age_encap(struct age_softc *sc, struct mbuf **m_head) 1205 { 1206 struct age_txdesc *txd, *txd_last; 1207 struct tx_desc *desc; 1208 struct mbuf *m; 1209 bus_dmamap_t map; 1210 uint32_t cflags, poff, vtag; 1211 int error, i, nsegs, prod; 1212 struct m_tag *mtag; 1213 1214 m = *m_head; 1215 cflags = vtag = 0; 1216 poff = 0; 1217 1218 prod = sc->age_cdata.age_tx_prod; 1219 txd = &sc->age_cdata.age_txdesc[prod]; 1220 txd_last = txd; 1221 map = txd->tx_dmamap; 1222 1223 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1224 1225 if (error != 0) { 1226 bus_dmamap_unload(sc->sc_dmat, map); 1227 error = EFBIG; 1228 } 1229 if (error == EFBIG) { 1230 error = 0; 1231 1232 MGETHDR(m, M_DONTWAIT, MT_DATA); 1233 if (m == NULL) { 1234 printf("%s: can't defrag TX mbuf\n", 1235 device_xname(sc->sc_dev)); 1236 m_freem(*m_head); 1237 *m_head = NULL; 1238 return (ENOBUFS); 1239 } 1240 1241 MCLGET(m, M_DONTWAIT); 1242 if (!(m->m_flags & M_EXT)) { 1243 m_freem(m); 1244 *m_head = NULL; 1245 return (ENOBUFS); 1246 } 1247 m->m_len = m->m_pkthdr.len; 1248 *m_head = m; 1249 1250 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1251 BUS_DMA_NOWAIT); 1252 1253 if (error != 0) { 1254 printf("%s: could not load defragged TX mbuf\n", 1255 device_xname(sc->sc_dev)); 1256 if (!error) { 1257 bus_dmamap_unload(sc->sc_dmat, map); 1258 error = EFBIG; 1259 } 1260 m_freem(*m_head); 1261 *m_head = NULL; 1262 return (error); 1263 } 1264 } else if (error) { 1265 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 1266 return (error); 1267 } 1268 1269 nsegs = map->dm_nsegs; 1270 1271 if (nsegs == 0) { 1272 m_freem(*m_head); 1273 *m_head = NULL; 1274 return (EIO); 1275 } 1276 1277 /* Check descriptor overrun. */ 1278 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1279 bus_dmamap_unload(sc->sc_dmat, map); 1280 return (ENOBUFS); 1281 } 1282 1283 m = *m_head; 1284 /* Configure Tx IP/TCP/UDP checksum offload. */ 1285 if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1286 cflags |= AGE_TD_CSUM; 1287 if ((m->m_pkthdr.csum_flags & M_CSUM_TCPv4) != 0) 1288 cflags |= AGE_TD_TCPCSUM; 1289 if ((m->m_pkthdr.csum_flags & M_CSUM_UDPv4) != 0) 1290 cflags |= AGE_TD_UDPCSUM; 1291 /* Set checksum start offset. */ 1292 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1293 } 1294 1295 #if NVLAN > 0 1296 /* Configure VLAN hardware tag insertion. */ 1297 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m))) { 1298 vtag = AGE_TX_VLAN_TAG(htons(VLAN_TAG_VALUE(mtag))); 1299 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1300 cflags |= AGE_TD_INSERT_VLAN_TAG; 1301 } 1302 #endif 1303 1304 desc = NULL; 1305 for (i = 0; i < nsegs; i++) { 1306 desc = &sc->age_rdata.age_tx_ring[prod]; 1307 desc->addr = htole64(map->dm_segs[i].ds_addr); 1308 desc->len = 1309 htole32(AGE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 1310 desc->flags = htole32(cflags); 1311 sc->age_cdata.age_tx_cnt++; 1312 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1313 } 1314 1315 /* Update producer index. */ 1316 sc->age_cdata.age_tx_prod = prod; 1317 1318 /* Set EOP on the last descriptor. */ 1319 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1320 desc = &sc->age_rdata.age_tx_ring[prod]; 1321 desc->flags |= htole32(AGE_TD_EOP); 1322 1323 /* Swap dmamap of the first and the last. */ 1324 txd = &sc->age_cdata.age_txdesc[prod]; 1325 map = txd_last->tx_dmamap; 1326 txd_last->tx_dmamap = txd->tx_dmamap; 1327 txd->tx_dmamap = map; 1328 txd->tx_m = m; 1329 1330 /* Sync descriptors. */ 1331 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1332 BUS_DMASYNC_PREWRITE); 1333 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1334 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1335 1336 return (0); 1337 } 1338 1339 static void 1340 age_txintr(struct age_softc *sc, int tpd_cons) 1341 { 1342 struct ifnet *ifp = &sc->sc_ec.ec_if; 1343 struct age_txdesc *txd; 1344 int cons, prog; 1345 1346 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1347 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1348 1349 /* 1350 * Go through our Tx list and free mbufs for those 1351 * frames which have been transmitted. 1352 */ 1353 cons = sc->age_cdata.age_tx_cons; 1354 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 1355 if (sc->age_cdata.age_tx_cnt <= 0) 1356 break; 1357 prog++; 1358 ifp->if_flags &= ~IFF_OACTIVE; 1359 sc->age_cdata.age_tx_cnt--; 1360 txd = &sc->age_cdata.age_txdesc[cons]; 1361 /* 1362 * Clear Tx descriptors, it's not required but would 1363 * help debugging in case of Tx issues. 1364 */ 1365 txd->tx_desc->addr = 0; 1366 txd->tx_desc->len = 0; 1367 txd->tx_desc->flags = 0; 1368 1369 if (txd->tx_m == NULL) 1370 continue; 1371 /* Reclaim transmitted mbufs. */ 1372 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1373 m_freem(txd->tx_m); 1374 txd->tx_m = NULL; 1375 } 1376 1377 if (prog > 0) { 1378 sc->age_cdata.age_tx_cons = cons; 1379 1380 /* 1381 * Unarm watchdog timer only when there are no pending 1382 * Tx descriptors in queue. 1383 */ 1384 if (sc->age_cdata.age_tx_cnt == 0) 1385 ifp->if_timer = 0; 1386 1387 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1388 sc->age_cdata.age_tx_ring_map->dm_mapsize, 1389 BUS_DMASYNC_PREWRITE); 1390 } 1391 } 1392 1393 /* Receive a frame. */ 1394 static void 1395 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 1396 { 1397 struct ifnet *ifp = &sc->sc_ec.ec_if; 1398 struct age_rxdesc *rxd; 1399 struct rx_desc *desc; 1400 struct mbuf *mp, *m; 1401 uint32_t status, index, vtag; 1402 int count, nsegs, pktlen; 1403 int rx_cons; 1404 1405 status = le32toh(rxrd->flags); 1406 index = le32toh(rxrd->index); 1407 rx_cons = AGE_RX_CONS(index); 1408 nsegs = AGE_RX_NSEGS(index); 1409 1410 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 1411 if ((status & AGE_RRD_ERROR) != 0 && 1412 (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 1413 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) { 1414 /* 1415 * We want to pass the following frames to upper 1416 * layer regardless of error status of Rx return 1417 * ring. 1418 * 1419 * o IP/TCP/UDP checksum is bad. 1420 * o frame length and protocol specific length 1421 * does not match. 1422 */ 1423 sc->age_cdata.age_rx_cons += nsegs; 1424 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1425 return; 1426 } 1427 1428 pktlen = 0; 1429 for (count = 0; count < nsegs; count++, 1430 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 1431 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 1432 mp = rxd->rx_m; 1433 desc = rxd->rx_desc; 1434 /* Add a new receive buffer to the ring. */ 1435 if (age_newbuf(sc, rxd, 0) != 0) { 1436 ifp->if_iqdrops++; 1437 /* Reuse Rx buffers. */ 1438 if (sc->age_cdata.age_rxhead != NULL) { 1439 m_freem(sc->age_cdata.age_rxhead); 1440 AGE_RXCHAIN_RESET(sc); 1441 } 1442 break; 1443 } 1444 1445 /* The length of the first mbuf is computed last. */ 1446 if (count != 0) { 1447 mp->m_len = AGE_RX_BYTES(le32toh(desc->len)); 1448 pktlen += mp->m_len; 1449 } 1450 1451 /* Chain received mbufs. */ 1452 if (sc->age_cdata.age_rxhead == NULL) { 1453 sc->age_cdata.age_rxhead = mp; 1454 sc->age_cdata.age_rxtail = mp; 1455 } else { 1456 mp->m_flags &= ~M_PKTHDR; 1457 sc->age_cdata.age_rxprev_tail = 1458 sc->age_cdata.age_rxtail; 1459 sc->age_cdata.age_rxtail->m_next = mp; 1460 sc->age_cdata.age_rxtail = mp; 1461 } 1462 1463 if (count == nsegs - 1) { 1464 /* 1465 * It seems that L1 controller has no way 1466 * to tell hardware to strip CRC bytes. 1467 */ 1468 sc->age_cdata.age_rxlen -= ETHER_CRC_LEN; 1469 if (nsegs > 1) { 1470 /* Remove the CRC bytes in chained mbufs. */ 1471 pktlen -= ETHER_CRC_LEN; 1472 if (mp->m_len <= ETHER_CRC_LEN) { 1473 sc->age_cdata.age_rxtail = 1474 sc->age_cdata.age_rxprev_tail; 1475 sc->age_cdata.age_rxtail->m_len -= 1476 (ETHER_CRC_LEN - mp->m_len); 1477 sc->age_cdata.age_rxtail->m_next = NULL; 1478 m_freem(mp); 1479 } else { 1480 mp->m_len -= ETHER_CRC_LEN; 1481 } 1482 } 1483 1484 m = sc->age_cdata.age_rxhead; 1485 m->m_flags |= M_PKTHDR; 1486 m->m_pkthdr.rcvif = ifp; 1487 m->m_pkthdr.len = sc->age_cdata.age_rxlen; 1488 /* Set the first mbuf length. */ 1489 m->m_len = sc->age_cdata.age_rxlen - pktlen; 1490 1491 /* 1492 * Set checksum information. 1493 * It seems that L1 controller can compute partial 1494 * checksum. The partial checksum value can be used 1495 * to accelerate checksum computation for fragmented 1496 * TCP/UDP packets. Upper network stack already 1497 * takes advantage of the partial checksum value in 1498 * IP reassembly stage. But I'm not sure the 1499 * correctness of the partial hardware checksum 1500 * assistance due to lack of data sheet. If it is 1501 * proven to work on L1 I'll enable it. 1502 */ 1503 if (status & AGE_RRD_IPV4) { 1504 if (!(status & AGE_RRD_IPCSUM_NOK)) 1505 m->m_pkthdr.csum_flags |= 1506 M_CSUM_IPv4_BAD; 1507 if (!((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 1508 (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0)) { 1509 m->m_pkthdr.csum_flags |= 1510 M_CSUM_TCP_UDP_BAD; 1511 } 1512 /* 1513 * Don't mark bad checksum for TCP/UDP frames 1514 * as fragmented frames may always have set 1515 * bad checksummed bit of descriptor status. 1516 */ 1517 } 1518 #if NVLAN > 0 1519 /* Check for VLAN tagged frames. */ 1520 if (status & AGE_RRD_VLAN) { 1521 vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 1522 VLAN_INPUT_TAG(ifp, m, AGE_RX_VLAN_TAG(vtag), 1523 continue); 1524 } 1525 #endif 1526 1527 #if NBPFILTER > 0 1528 if (ifp->if_bpf) 1529 bpf_mtap(ifp->if_bpf, m); 1530 #endif 1531 /* Pass it on. */ 1532 ether_input(ifp, m); 1533 1534 /* Reset mbuf chains. */ 1535 AGE_RXCHAIN_RESET(sc); 1536 } 1537 } 1538 1539 if (count != nsegs) { 1540 sc->age_cdata.age_rx_cons += nsegs; 1541 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1542 } else 1543 sc->age_cdata.age_rx_cons = rx_cons; 1544 } 1545 1546 static void 1547 age_rxintr(struct age_softc *sc, int rr_prod) 1548 { 1549 struct rx_rdesc *rxrd; 1550 int rr_cons, nsegs, pktlen, prog; 1551 1552 rr_cons = sc->age_cdata.age_rr_cons; 1553 if (rr_cons == rr_prod) 1554 return; 1555 1556 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1557 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1558 BUS_DMASYNC_POSTREAD); 1559 1560 for (prog = 0; rr_cons != rr_prod; prog++) { 1561 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 1562 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 1563 if (nsegs == 0) 1564 break; 1565 /* 1566 * Check number of segments against received bytes 1567 * Non-matching value would indicate that hardware 1568 * is still trying to update Rx return descriptors. 1569 * I'm not sure whether this check is really needed. 1570 */ 1571 pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 1572 if (nsegs != ((pktlen + (MCLBYTES - ETHER_HDR_LEN - ETHER_CRC_LEN)) / 1573 (MCLBYTES - ETHER_HDR_LEN))) 1574 break; 1575 1576 /* Received a frame. */ 1577 age_rxeof(sc, rxrd); 1578 1579 /* Clear return ring. */ 1580 rxrd->index = 0; 1581 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 1582 } 1583 1584 if (prog > 0) { 1585 /* Update the consumer index. */ 1586 sc->age_cdata.age_rr_cons = rr_cons; 1587 1588 /* Sync descriptors. */ 1589 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1590 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1591 BUS_DMASYNC_PREWRITE); 1592 1593 /* Notify hardware availability of new Rx buffers. */ 1594 AGE_COMMIT_MBOX(sc); 1595 } 1596 } 1597 1598 static void 1599 age_tick(void *xsc) 1600 { 1601 struct age_softc *sc = xsc; 1602 struct mii_data *mii = &sc->sc_miibus; 1603 int s; 1604 1605 s = splnet(); 1606 mii_tick(mii); 1607 splx(s); 1608 1609 callout_schedule(&sc->sc_tick_ch, hz); 1610 } 1611 1612 static void 1613 age_reset(struct age_softc *sc) 1614 { 1615 uint32_t reg; 1616 int i; 1617 1618 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 1619 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1620 DELAY(1); 1621 if ((CSR_READ_4(sc, AGE_MASTER_CFG) & MASTER_RESET) == 0) 1622 break; 1623 } 1624 if (i == 0) 1625 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 1626 1627 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1628 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1629 break; 1630 DELAY(10); 1631 } 1632 1633 if (i == 0) 1634 printf("%s: reset timeout(0x%08x)!\n", device_xname(sc->sc_dev), 1635 reg); 1636 1637 /* Initialize PCIe module. From Linux. */ 1638 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1639 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1640 } 1641 1642 static int 1643 age_init(struct ifnet *ifp) 1644 { 1645 struct age_softc *sc = ifp->if_softc; 1646 struct mii_data *mii; 1647 uint8_t eaddr[ETHER_ADDR_LEN]; 1648 bus_addr_t paddr; 1649 uint32_t reg, fsize; 1650 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 1651 int error; 1652 1653 /* 1654 * Cancel any pending I/O. 1655 */ 1656 age_stop(sc); 1657 1658 /* 1659 * Reset the chip to a known state. 1660 */ 1661 age_reset(sc); 1662 1663 /* Initialize descriptors. */ 1664 error = age_init_rx_ring(sc); 1665 if (error != 0) { 1666 printf("%s: no memory for Rx buffers.\n", device_xname(sc->sc_dev)); 1667 age_stop(sc); 1668 return (error); 1669 } 1670 age_init_rr_ring(sc); 1671 age_init_tx_ring(sc); 1672 age_init_cmb_block(sc); 1673 age_init_smb_block(sc); 1674 1675 /* Reprogram the station address. */ 1676 memcpy(eaddr, CLLADDR(ifp->if_sadl), sizeof(eaddr)); 1677 CSR_WRITE_4(sc, AGE_PAR0, 1678 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1679 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 1680 1681 /* Set descriptor base addresses. */ 1682 paddr = sc->age_rdata.age_tx_ring_paddr; 1683 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 1684 paddr = sc->age_rdata.age_rx_ring_paddr; 1685 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 1686 paddr = sc->age_rdata.age_rr_ring_paddr; 1687 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 1688 paddr = sc->age_rdata.age_tx_ring_paddr; 1689 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 1690 paddr = sc->age_rdata.age_cmb_block_paddr; 1691 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1692 paddr = sc->age_rdata.age_smb_block_paddr; 1693 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1694 1695 /* Set Rx/Rx return descriptor counter. */ 1696 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 1697 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 1698 DESC_RRD_CNT_MASK) | 1699 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 1700 1701 /* Set Tx descriptor counter. */ 1702 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 1703 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 1704 1705 /* Tell hardware that we're ready to load descriptors. */ 1706 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 1707 1708 /* 1709 * Initialize mailbox register. 1710 * Updated producer/consumer index information is exchanged 1711 * through this mailbox register. However Tx producer and 1712 * Rx return consumer/Rx producer are all shared such that 1713 * it's hard to separate code path between Tx and Rx without 1714 * locking. If L1 hardware have a separate mail box register 1715 * for Tx and Rx consumer/producer management we could have 1716 * indepent Tx/Rx handler which in turn Rx handler could have 1717 * been run without any locking. 1718 */ 1719 AGE_COMMIT_MBOX(sc); 1720 1721 /* Configure IPG/IFG parameters. */ 1722 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 1723 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 1724 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1725 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1726 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 1727 1728 /* Set parameters for half-duplex media. */ 1729 CSR_WRITE_4(sc, AGE_HDPX_CFG, 1730 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1731 HDPX_CFG_LCOL_MASK) | 1732 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1733 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1734 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1735 HDPX_CFG_ABEBT_MASK) | 1736 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1737 HDPX_CFG_JAMIPG_MASK)); 1738 1739 /* Configure interrupt moderation timer. */ 1740 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 1741 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 1742 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 1743 reg &= ~MASTER_MTIMER_ENB; 1744 if (AGE_USECS(sc->age_int_mod) == 0) 1745 reg &= ~MASTER_ITIMER_ENB; 1746 else 1747 reg |= MASTER_ITIMER_ENB; 1748 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 1749 if (agedebug) 1750 printf("%s: interrupt moderation is %d us.\n", 1751 device_xname(sc->sc_dev), sc->age_int_mod); 1752 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 1753 1754 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 1755 if (ifp->if_mtu < ETHERMTU) 1756 sc->age_max_frame_size = ETHERMTU; 1757 else 1758 sc->age_max_frame_size = ifp->if_mtu; 1759 sc->age_max_frame_size += ETHER_HDR_LEN + 1760 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 1761 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 1762 1763 /* Configure jumbo frame. */ 1764 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 1765 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 1766 (((fsize / sizeof(uint64_t)) << 1767 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 1768 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 1769 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 1770 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 1771 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 1772 1773 /* Configure flow-control parameters. From Linux. */ 1774 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 1775 /* 1776 * Magic workaround for old-L1. 1777 * Don't know which hw revision requires this magic. 1778 */ 1779 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1780 /* 1781 * Another magic workaround for flow-control mode 1782 * change. From Linux. 1783 */ 1784 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1785 } 1786 /* 1787 * TODO 1788 * Should understand pause parameter relationships between FIFO 1789 * size and number of Rx descriptors and Rx return descriptors. 1790 * 1791 * Magic parameters came from Linux. 1792 */ 1793 switch (sc->age_chip_rev) { 1794 case 0x8001: 1795 case 0x9001: 1796 case 0x9002: 1797 case 0x9003: 1798 rxf_hi = AGE_RX_RING_CNT / 16; 1799 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 1800 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 1801 rrd_lo = AGE_RR_RING_CNT / 16; 1802 break; 1803 default: 1804 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 1805 rxf_lo = reg / 16; 1806 if (rxf_lo < 192) 1807 rxf_lo = 192; 1808 rxf_hi = (reg * 7) / 8; 1809 if (rxf_hi < rxf_lo) 1810 rxf_hi = rxf_lo + 16; 1811 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 1812 rrd_lo = reg / 8; 1813 rrd_hi = (reg * 7) / 8; 1814 if (rrd_lo < 2) 1815 rrd_lo = 2; 1816 if (rrd_hi < rrd_lo) 1817 rrd_hi = rrd_lo + 3; 1818 break; 1819 } 1820 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 1821 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 1822 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 1823 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 1824 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 1825 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 1826 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 1827 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 1828 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 1829 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 1830 1831 /* Configure RxQ. */ 1832 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1833 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 1834 RXQ_CFG_RD_BURST_MASK) | 1835 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 1836 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 1837 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 1838 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 1839 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1840 1841 /* Configure TxQ. */ 1842 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1843 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1844 TXQ_CFG_TPD_BURST_MASK) | 1845 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 1846 TXQ_CFG_TX_FIFO_BURST_MASK) | 1847 ((TXQ_CFG_TPD_FETCH_DEFAULT << 1848 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 1849 TXQ_CFG_ENB); 1850 1851 /* Configure DMA parameters. */ 1852 CSR_WRITE_4(sc, AGE_DMA_CFG, 1853 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 1854 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 1855 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 1856 1857 /* Configure CMB DMA write threshold. */ 1858 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 1859 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 1860 CMB_WR_THRESH_RRD_MASK) | 1861 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 1862 CMB_WR_THRESH_TPD_MASK)); 1863 1864 /* Set CMB/SMB timer and enable them. */ 1865 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 1866 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 1867 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 1868 1869 /* Request SMB updates for every seconds. */ 1870 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 1871 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 1872 1873 /* 1874 * Disable all WOL bits as WOL can interfere normal Rx 1875 * operation. 1876 */ 1877 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1878 1879 /* 1880 * Configure Tx/Rx MACs. 1881 * - Auto-padding for short frames. 1882 * - Enable CRC generation. 1883 * Start with full-duplex/1000Mbps media. Actual reconfiguration 1884 * of MAC is followed after link establishment. 1885 */ 1886 CSR_WRITE_4(sc, AGE_MAC_CFG, 1887 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 1888 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 1889 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1890 MAC_CFG_PREAMBLE_MASK)); 1891 1892 /* Set up the receive filter. */ 1893 age_rxfilter(sc); 1894 age_rxvlan(sc); 1895 1896 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1897 reg |= MAC_CFG_RXCSUM_ENB; 1898 1899 /* Ack all pending interrupts and clear it. */ 1900 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 1901 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 1902 1903 /* Finally enable Tx/Rx MAC. */ 1904 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 1905 1906 sc->age_flags &= ~AGE_FLAG_LINK; 1907 1908 /* Switch to the current media. */ 1909 mii = &sc->sc_miibus; 1910 mii_mediachg(mii); 1911 1912 callout_schedule(&sc->sc_tick_ch, hz); 1913 1914 ifp->if_flags |= IFF_RUNNING; 1915 ifp->if_flags &= ~IFF_OACTIVE; 1916 1917 return (0); 1918 } 1919 1920 static void 1921 age_stop(struct age_softc *sc) 1922 { 1923 struct ifnet *ifp = &sc->sc_ec.ec_if; 1924 struct age_txdesc *txd; 1925 struct age_rxdesc *rxd; 1926 uint32_t reg; 1927 int i; 1928 1929 callout_stop(&sc->sc_tick_ch); 1930 1931 /* 1932 * Mark the interface down and cancel the watchdog timer. 1933 */ 1934 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1935 ifp->if_timer = 0; 1936 1937 sc->age_flags &= ~AGE_FLAG_LINK; 1938 1939 /* 1940 * Disable interrupts. 1941 */ 1942 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 1943 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 1944 1945 /* Stop CMB/SMB updates. */ 1946 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 1947 1948 /* Stop Rx/Tx MAC. */ 1949 age_stop_rxmac(sc); 1950 age_stop_txmac(sc); 1951 1952 /* Stop DMA. */ 1953 CSR_WRITE_4(sc, AGE_DMA_CFG, 1954 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 1955 1956 /* Stop TxQ/RxQ. */ 1957 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1958 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 1959 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1960 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 1961 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1962 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1963 break; 1964 DELAY(10); 1965 } 1966 if (i == 0) 1967 printf("%s: stopping Rx/Tx MACs timed out(0x%08x)!\n", 1968 device_xname(sc->sc_dev), reg); 1969 1970 /* Reclaim Rx buffers that have been processed. */ 1971 if (sc->age_cdata.age_rxhead != NULL) 1972 m_freem(sc->age_cdata.age_rxhead); 1973 AGE_RXCHAIN_RESET(sc); 1974 1975 /* 1976 * Free RX and TX mbufs still in the queues. 1977 */ 1978 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1979 rxd = &sc->age_cdata.age_rxdesc[i]; 1980 if (rxd->rx_m != NULL) { 1981 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1982 m_freem(rxd->rx_m); 1983 rxd->rx_m = NULL; 1984 } 1985 } 1986 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1987 txd = &sc->age_cdata.age_txdesc[i]; 1988 if (txd->tx_m != NULL) { 1989 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1990 m_freem(txd->tx_m); 1991 txd->tx_m = NULL; 1992 } 1993 } 1994 } 1995 1996 static void 1997 age_stats_update(struct age_softc *sc) 1998 { 1999 struct ifnet *ifp = &sc->sc_ec.ec_if; 2000 struct age_stats *stat; 2001 struct smb *smb; 2002 2003 stat = &sc->age_stat; 2004 2005 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2006 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2007 2008 smb = sc->age_rdata.age_smb_block; 2009 if (smb->updated == 0) 2010 return; 2011 2012 /* Rx stats. */ 2013 stat->rx_frames += smb->rx_frames; 2014 stat->rx_bcast_frames += smb->rx_bcast_frames; 2015 stat->rx_mcast_frames += smb->rx_mcast_frames; 2016 stat->rx_pause_frames += smb->rx_pause_frames; 2017 stat->rx_control_frames += smb->rx_control_frames; 2018 stat->rx_crcerrs += smb->rx_crcerrs; 2019 stat->rx_lenerrs += smb->rx_lenerrs; 2020 stat->rx_bytes += smb->rx_bytes; 2021 stat->rx_runts += smb->rx_runts; 2022 stat->rx_fragments += smb->rx_fragments; 2023 stat->rx_pkts_64 += smb->rx_pkts_64; 2024 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2025 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2026 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2027 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2028 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2029 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2030 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2031 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2032 stat->rx_desc_oflows += smb->rx_desc_oflows; 2033 stat->rx_alignerrs += smb->rx_alignerrs; 2034 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2035 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2036 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2037 2038 /* Tx stats. */ 2039 stat->tx_frames += smb->tx_frames; 2040 stat->tx_bcast_frames += smb->tx_bcast_frames; 2041 stat->tx_mcast_frames += smb->tx_mcast_frames; 2042 stat->tx_pause_frames += smb->tx_pause_frames; 2043 stat->tx_excess_defer += smb->tx_excess_defer; 2044 stat->tx_control_frames += smb->tx_control_frames; 2045 stat->tx_deferred += smb->tx_deferred; 2046 stat->tx_bytes += smb->tx_bytes; 2047 stat->tx_pkts_64 += smb->tx_pkts_64; 2048 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2049 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2050 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2051 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2052 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2053 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2054 stat->tx_single_colls += smb->tx_single_colls; 2055 stat->tx_multi_colls += smb->tx_multi_colls; 2056 stat->tx_late_colls += smb->tx_late_colls; 2057 stat->tx_excess_colls += smb->tx_excess_colls; 2058 stat->tx_underrun += smb->tx_underrun; 2059 stat->tx_desc_underrun += smb->tx_desc_underrun; 2060 stat->tx_lenerrs += smb->tx_lenerrs; 2061 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2062 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2063 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2064 2065 /* Update counters in ifnet. */ 2066 ifp->if_opackets += smb->tx_frames; 2067 2068 ifp->if_collisions += smb->tx_single_colls + 2069 smb->tx_multi_colls + smb->tx_late_colls + 2070 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 2071 2072 ifp->if_oerrors += smb->tx_excess_colls + 2073 smb->tx_late_colls + smb->tx_underrun + 2074 smb->tx_pkts_truncated; 2075 2076 ifp->if_ipackets += smb->rx_frames; 2077 2078 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2079 smb->rx_runts + smb->rx_pkts_truncated + 2080 smb->rx_fifo_oflows + smb->rx_desc_oflows + 2081 smb->rx_alignerrs; 2082 2083 /* Update done, clear. */ 2084 smb->updated = 0; 2085 2086 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2087 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2088 } 2089 2090 static void 2091 age_stop_txmac(struct age_softc *sc) 2092 { 2093 uint32_t reg; 2094 int i; 2095 2096 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2097 if ((reg & MAC_CFG_TX_ENB) != 0) { 2098 reg &= ~MAC_CFG_TX_ENB; 2099 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2100 } 2101 /* Stop Tx DMA engine. */ 2102 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2103 if ((reg & DMA_CFG_RD_ENB) != 0) { 2104 reg &= ~DMA_CFG_RD_ENB; 2105 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2106 } 2107 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2108 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2109 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2110 break; 2111 DELAY(10); 2112 } 2113 if (i == 0) 2114 printf("%s: stopping TxMAC timeout!\n", device_xname(sc->sc_dev)); 2115 } 2116 2117 static void 2118 age_stop_rxmac(struct age_softc *sc) 2119 { 2120 uint32_t reg; 2121 int i; 2122 2123 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2124 if ((reg & MAC_CFG_RX_ENB) != 0) { 2125 reg &= ~MAC_CFG_RX_ENB; 2126 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2127 } 2128 /* Stop Rx DMA engine. */ 2129 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2130 if ((reg & DMA_CFG_WR_ENB) != 0) { 2131 reg &= ~DMA_CFG_WR_ENB; 2132 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2133 } 2134 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2135 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2136 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2137 break; 2138 DELAY(10); 2139 } 2140 if (i == 0) 2141 printf("%s: stopping RxMAC timeout!\n", device_xname(sc->sc_dev)); 2142 } 2143 2144 static void 2145 age_init_tx_ring(struct age_softc *sc) 2146 { 2147 struct age_ring_data *rd; 2148 struct age_txdesc *txd; 2149 int i; 2150 2151 sc->age_cdata.age_tx_prod = 0; 2152 sc->age_cdata.age_tx_cons = 0; 2153 sc->age_cdata.age_tx_cnt = 0; 2154 2155 rd = &sc->age_rdata; 2156 memset(rd->age_tx_ring, 0, AGE_TX_RING_SZ); 2157 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2158 txd = &sc->age_cdata.age_txdesc[i]; 2159 txd->tx_desc = &rd->age_tx_ring[i]; 2160 txd->tx_m = NULL; 2161 } 2162 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 2163 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2164 } 2165 2166 static int 2167 age_init_rx_ring(struct age_softc *sc) 2168 { 2169 struct age_ring_data *rd; 2170 struct age_rxdesc *rxd; 2171 int i; 2172 2173 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 2174 rd = &sc->age_rdata; 2175 memset(rd->age_rx_ring, 0, AGE_RX_RING_SZ); 2176 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2177 rxd = &sc->age_cdata.age_rxdesc[i]; 2178 rxd->rx_m = NULL; 2179 rxd->rx_desc = &rd->age_rx_ring[i]; 2180 if (age_newbuf(sc, rxd, 1) != 0) 2181 return (ENOBUFS); 2182 } 2183 2184 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 0, 2185 sc->age_cdata.age_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2186 2187 return (0); 2188 } 2189 2190 static void 2191 age_init_rr_ring(struct age_softc *sc) 2192 { 2193 struct age_ring_data *rd; 2194 2195 sc->age_cdata.age_rr_cons = 0; 2196 AGE_RXCHAIN_RESET(sc); 2197 2198 rd = &sc->age_rdata; 2199 memset(rd->age_rr_ring, 0, AGE_RR_RING_SZ); 2200 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 2201 sc->age_cdata.age_rr_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2202 } 2203 2204 static void 2205 age_init_cmb_block(struct age_softc *sc) 2206 { 2207 struct age_ring_data *rd; 2208 2209 rd = &sc->age_rdata; 2210 memset(rd->age_cmb_block, 0, AGE_CMB_BLOCK_SZ); 2211 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 2212 sc->age_cdata.age_cmb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2213 } 2214 2215 static void 2216 age_init_smb_block(struct age_softc *sc) 2217 { 2218 struct age_ring_data *rd; 2219 2220 rd = &sc->age_rdata; 2221 memset(rd->age_smb_block, 0, AGE_SMB_BLOCK_SZ); 2222 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2223 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2224 } 2225 2226 static int 2227 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd, int init) 2228 { 2229 struct rx_desc *desc; 2230 struct mbuf *m; 2231 bus_dmamap_t map; 2232 int error; 2233 2234 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 2235 if (m == NULL) 2236 return (ENOBUFS); 2237 MCLGET(m, init ? M_WAITOK : M_DONTWAIT); 2238 if (!(m->m_flags & M_EXT)) { 2239 m_freem(m); 2240 return (ENOBUFS); 2241 } 2242 2243 m->m_len = m->m_pkthdr.len = MCLBYTES; 2244 m_adj(m, PAGE_SIZE); 2245 2246 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2247 sc->age_cdata.age_rx_sparemap, m, BUS_DMA_NOWAIT); 2248 2249 if (error != 0) { 2250 if (!error) { 2251 bus_dmamap_unload(sc->sc_dmat, 2252 sc->age_cdata.age_rx_sparemap); 2253 error = EFBIG; 2254 printf("%s: too many segments?!\n", 2255 device_xname(sc->sc_dev)); 2256 } 2257 m_freem(m); 2258 2259 if (init) 2260 printf("%s: can't load RX mbuf\n", device_xname(sc->sc_dev)); 2261 return (error); 2262 } 2263 2264 if (rxd->rx_m != NULL) { 2265 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2266 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2267 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2268 } 2269 map = rxd->rx_dmamap; 2270 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 2271 sc->age_cdata.age_rx_sparemap = map; 2272 rxd->rx_m = m; 2273 2274 desc = rxd->rx_desc; 2275 desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 2276 desc->len = 2277 htole32((rxd->rx_dmamap->dm_segs[0].ds_len & AGE_RD_LEN_MASK) << 2278 AGE_RD_LEN_SHIFT); 2279 2280 return (0); 2281 } 2282 2283 static void 2284 age_rxvlan(struct age_softc *sc) 2285 { 2286 uint32_t reg; 2287 2288 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2289 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2290 if (sc->sc_ec.ec_capabilities & ETHERCAP_VLAN_HWTAGGING) 2291 reg |= MAC_CFG_VLAN_TAG_STRIP; 2292 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2293 } 2294 2295 static void 2296 age_rxfilter(struct age_softc *sc) 2297 { 2298 struct ethercom *ec = &sc->sc_ec; 2299 struct ifnet *ifp = &sc->sc_ec.ec_if; 2300 struct ether_multi *enm; 2301 struct ether_multistep step; 2302 uint32_t crc; 2303 uint32_t mchash[2]; 2304 uint32_t rxcfg; 2305 2306 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 2307 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2308 2309 if (ifp->if_flags & IFF_BROADCAST) 2310 rxcfg |= MAC_CFG_BCAST; 2311 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 2312 if (ifp->if_flags & IFF_PROMISC) 2313 rxcfg |= MAC_CFG_PROMISC; 2314 if (ifp->if_flags & IFF_ALLMULTI) 2315 rxcfg |= MAC_CFG_ALLMULTI; 2316 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF); 2317 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF); 2318 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 2319 return; 2320 } 2321 2322 /* Program new filter. */ 2323 memset(mchash, 0, sizeof(mchash)); 2324 2325 ETHER_FIRST_MULTI(step, ec, enm); 2326 while (enm != NULL) { 2327 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 2328 enm->enm_addrlo), ETHER_ADDR_LEN); 2329 2330 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2331 ETHER_NEXT_MULTI(step, enm); 2332 } 2333 2334 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 2335 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 2336 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 2337 } 2338
Indexes created Fri Oct 03 02:09:57 GMT 2025