if_age.c revision 1.72
1 /* $NetBSD: if_age.c,v 1.72 2022/08/22 16:18:44 thorpej Exp $ */ 2 /* $OpenBSD: if_age.c,v 1.1 2009/01/16 05:00:34 kevlo Exp $ */ 3 4 /*- 5 * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: if_age.c,v 1.72 2022/08/22 16:18:44 thorpej Exp $"); 35 36 #include "vlan.h" 37 38 #include <sys/param.h> 39 #include <sys/proc.h> 40 #include <sys/endian.h> 41 #include <sys/systm.h> 42 #include <sys/types.h> 43 #include <sys/sockio.h> 44 #include <sys/mbuf.h> 45 #include <sys/queue.h> 46 #include <sys/kernel.h> 47 #include <sys/device.h> 48 #include <sys/callout.h> 49 #include <sys/socket.h> 50 51 #include <net/if.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 #include <net/if_ether.h> 55 56 #ifdef INET 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <netinet/ip.h> 61 #endif 62 63 #include <net/if_types.h> 64 #include <net/if_vlanvar.h> 65 66 #include <net/bpf.h> 67 68 #include <dev/mii/mii.h> 69 #include <dev/mii/miivar.h> 70 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcivar.h> 73 #include <dev/pci/pcidevs.h> 74 75 #include <dev/pci/if_agereg.h> 76 77 static int age_match(device_t, cfdata_t, void *); 78 static void age_attach(device_t, device_t, void *); 79 static int age_detach(device_t, int); 80 81 static bool age_resume(device_t, const pmf_qual_t *); 82 83 static int age_miibus_readreg(device_t, int, int, uint16_t *); 84 static int age_miibus_writereg(device_t, int, int, uint16_t); 85 static void age_miibus_statchg(struct ifnet *); 86 87 static int age_init(struct ifnet *); 88 static int age_ioctl(struct ifnet *, u_long, void *); 89 static void age_start(struct ifnet *); 90 static void age_watchdog(struct ifnet *); 91 static bool age_shutdown(device_t, int); 92 static void age_mediastatus(struct ifnet *, struct ifmediareq *); 93 static int age_mediachange(struct ifnet *); 94 95 static int age_intr(void *); 96 static int age_dma_alloc(struct age_softc *); 97 static void age_dma_free(struct age_softc *); 98 static void age_get_macaddr(struct age_softc *, uint8_t[]); 99 static void age_phy_reset(struct age_softc *); 100 101 static int age_encap(struct age_softc *, struct mbuf *); 102 static void age_init_tx_ring(struct age_softc *); 103 static int age_init_rx_ring(struct age_softc *); 104 static void age_init_rr_ring(struct age_softc *); 105 static void age_init_cmb_block(struct age_softc *); 106 static void age_init_smb_block(struct age_softc *); 107 static int age_newbuf(struct age_softc *, struct age_rxdesc *, int); 108 static void age_mac_config(struct age_softc *); 109 static void age_txintr(struct age_softc *, int); 110 static void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 111 static void age_rxintr(struct age_softc *, int); 112 static void age_tick(void *); 113 static void age_reset(struct age_softc *); 114 static void age_stop(struct ifnet *, int); 115 static void age_stats_update(struct age_softc *); 116 static void age_stop_txmac(struct age_softc *); 117 static void age_stop_rxmac(struct age_softc *); 118 static void age_rxvlan(struct age_softc *sc); 119 static void age_rxfilter(struct age_softc *); 120 121 CFATTACH_DECL_NEW(age, sizeof(struct age_softc), 122 age_match, age_attach, age_detach, NULL); 123 124 int agedebug = 0; 125 #define DPRINTF(x) do { if (agedebug) printf x; } while (0) 126 127 #define AGE_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 128 129 static int 130 age_match(device_t dev, cfdata_t match, void *aux) 131 { 132 struct pci_attach_args *pa = aux; 133 134 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && 135 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_GIGA); 136 } 137 138 static void 139 age_attach(device_t parent, device_t self, void *aux) 140 { 141 struct age_softc *sc = device_private(self); 142 struct pci_attach_args *pa = aux; 143 pci_intr_handle_t ih; 144 const char *intrstr; 145 struct ifnet *ifp = &sc->sc_ec.ec_if; 146 struct mii_data * const mii = &sc->sc_miibus; 147 pcireg_t memtype; 148 int error = 0; 149 char intrbuf[PCI_INTRSTR_LEN]; 150 151 aprint_naive("\n"); 152 aprint_normal(": Attansic/Atheros L1 Gigabit Ethernet\n"); 153 154 sc->sc_dev = self; 155 sc->sc_pct = pa->pa_pc; 156 sc->sc_pcitag = pa->pa_tag; 157 158 if (pci_dma64_available(pa)) 159 sc->sc_dmat = pa->pa_dmat64; 160 else 161 sc->sc_dmat = pa->pa_dmat; 162 163 /* 164 * Allocate IO memory 165 */ 166 memtype = pci_mapreg_type(sc->sc_pct, sc->sc_pcitag, AGE_PCIR_BAR); 167 switch (memtype) { 168 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 169 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 170 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 171 break; 172 default: 173 aprint_error_dev(self, "invalid base address register\n"); 174 break; 175 } 176 177 if (pci_mapreg_map(pa, AGE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 178 &sc->sc_mem_bh, NULL, &sc->sc_mem_size) != 0) { 179 aprint_error_dev(self, "could not map mem space\n"); 180 return; 181 } 182 183 if (pci_intr_map(pa, &ih) != 0) { 184 aprint_error_dev(self, "could not map interrupt\n"); 185 goto fail; 186 } 187 188 /* 189 * Allocate IRQ 190 */ 191 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf)); 192 sc->sc_irq_handle = pci_intr_establish_xname(sc->sc_pct, ih, IPL_NET, 193 age_intr, sc, device_xname(self)); 194 if (sc->sc_irq_handle == NULL) { 195 aprint_error_dev(self, "could not establish interrupt"); 196 if (intrstr != NULL) 197 aprint_error(" at %s", intrstr); 198 aprint_error("\n"); 199 goto fail; 200 } 201 aprint_normal_dev(self, "%s\n", intrstr); 202 203 /* Set PHY address. */ 204 sc->age_phyaddr = AGE_PHY_ADDR; 205 206 /* Reset PHY. */ 207 age_phy_reset(sc); 208 209 /* Reset the ethernet controller. */ 210 age_reset(sc); 211 212 /* Get PCI and chip id/revision. */ 213 sc->age_rev = PCI_REVISION(pa->pa_class); 214 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 215 MASTER_CHIP_REV_SHIFT; 216 217 aprint_debug_dev(self, "PCI device revision : 0x%04x\n", sc->age_rev); 218 aprint_debug_dev(self, "Chip id/revision : 0x%04x\n", sc->age_chip_rev); 219 220 if (agedebug) { 221 aprint_debug_dev(self, "%d Tx FIFO, %d Rx FIFO\n", 222 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 223 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 224 } 225 226 /* Set max allowable DMA size. */ 227 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 228 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 229 230 /* Allocate DMA stuffs */ 231 error = age_dma_alloc(sc); 232 if (error) 233 goto fail; 234 235 callout_init(&sc->sc_tick_ch, 0); 236 callout_setfunc(&sc->sc_tick_ch, age_tick, sc); 237 238 /* Load station address. */ 239 age_get_macaddr(sc, sc->sc_enaddr); 240 241 aprint_normal_dev(self, "Ethernet address %s\n", 242 ether_sprintf(sc->sc_enaddr)); 243 244 ifp->if_softc = sc; 245 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 246 ifp->if_init = age_init; 247 ifp->if_ioctl = age_ioctl; 248 ifp->if_start = age_start; 249 ifp->if_stop = age_stop; 250 ifp->if_watchdog = age_watchdog; 251 ifp->if_baudrate = IF_Gbps(1); 252 IFQ_SET_MAXLEN(&ifp->if_snd, AGE_TX_RING_CNT - 1); 253 IFQ_SET_READY(&ifp->if_snd); 254 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 255 256 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 257 258 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Rx | 259 IFCAP_CSUM_TCPv4_Rx | 260 IFCAP_CSUM_UDPv4_Rx; 261 #ifdef AGE_CHECKSUM 262 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | 263 IFCAP_CSUM_TCPv4_Tx | 264 IFCAP_CSUM_UDPv4_Tx; 265 #endif 266 267 #if NVLAN > 0 268 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 269 sc->sc_ec.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 270 #endif 271 272 /* Set up MII bus. */ 273 mii->mii_ifp = ifp; 274 mii->mii_readreg = age_miibus_readreg; 275 mii->mii_writereg = age_miibus_writereg; 276 mii->mii_statchg = age_miibus_statchg; 277 278 sc->sc_ec.ec_mii = mii; 279 ifmedia_init(&mii->mii_media, 0, age_mediachange, age_mediastatus); 280 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 281 MII_OFFSET_ANY, MIIF_DOPAUSE); 282 283 if (LIST_FIRST(&mii->mii_phys) == NULL) { 284 aprint_error_dev(self, "no PHY found!\n"); 285 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 286 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 287 } else 288 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 289 290 if_attach(ifp); 291 if_deferred_start_init(ifp, NULL); 292 ether_ifattach(ifp, sc->sc_enaddr); 293 294 if (pmf_device_register1(self, NULL, age_resume, age_shutdown)) 295 pmf_class_network_register(self, ifp); 296 else 297 aprint_error_dev(self, "couldn't establish power handler\n"); 298 299 return; 300 301 fail: 302 age_dma_free(sc); 303 if (sc->sc_irq_handle != NULL) { 304 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 305 sc->sc_irq_handle = NULL; 306 } 307 if (sc->sc_mem_size) { 308 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 309 sc->sc_mem_size = 0; 310 } 311 } 312 313 static int 314 age_detach(device_t self, int flags) 315 { 316 struct age_softc *sc = device_private(self); 317 struct ifnet *ifp = &sc->sc_ec.ec_if; 318 int s; 319 320 pmf_device_deregister(self); 321 s = splnet(); 322 age_stop(ifp, 0); 323 splx(s); 324 325 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 326 327 ether_ifdetach(ifp); 328 if_detach(ifp); 329 age_dma_free(sc); 330 331 /* Delete all remaining media. */ 332 ifmedia_fini(&sc->sc_miibus.mii_media); 333 334 if (sc->sc_irq_handle != NULL) { 335 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 336 sc->sc_irq_handle = NULL; 337 } 338 if (sc->sc_mem_size) { 339 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 340 sc->sc_mem_size = 0; 341 } 342 return 0; 343 } 344 345 /* 346 * Read a PHY register on the MII of the L1. 347 */ 348 static int 349 age_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 350 { 351 struct age_softc *sc = device_private(dev); 352 uint32_t v; 353 int i; 354 355 if (phy != sc->age_phyaddr) 356 return -1; 357 358 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 359 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 360 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 361 DELAY(1); 362 v = CSR_READ_4(sc, AGE_MDIO); 363 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 364 break; 365 } 366 367 if (i == 0) { 368 printf("%s: phy read timeout: phy %d, reg %d\n", 369 device_xname(sc->sc_dev), phy, reg); 370 return ETIMEDOUT; 371 } 372 373 *val = (v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT; 374 return 0; 375 } 376 377 /* 378 * Write a PHY register on the MII of the L1. 379 */ 380 static int 381 age_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 382 { 383 struct age_softc *sc = device_private(dev); 384 uint32_t v; 385 int i; 386 387 if (phy != sc->age_phyaddr) 388 return -1; 389 390 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 391 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 392 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 393 394 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 395 DELAY(1); 396 v = CSR_READ_4(sc, AGE_MDIO); 397 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 398 break; 399 } 400 401 if (i == 0) { 402 printf("%s: phy write timeout: phy %d, reg %d\n", 403 device_xname(sc->sc_dev), phy, reg); 404 return ETIMEDOUT; 405 } 406 407 return 0; 408 } 409 410 /* 411 * Callback from MII layer when media changes. 412 */ 413 static void 414 age_miibus_statchg(struct ifnet *ifp) 415 { 416 struct age_softc *sc = ifp->if_softc; 417 struct mii_data *mii = &sc->sc_miibus; 418 419 if ((ifp->if_flags & IFF_RUNNING) == 0) 420 return; 421 422 sc->age_flags &= ~AGE_FLAG_LINK; 423 if ((mii->mii_media_status & IFM_AVALID) != 0) { 424 switch (IFM_SUBTYPE(mii->mii_media_active)) { 425 case IFM_10_T: 426 case IFM_100_TX: 427 case IFM_1000_T: 428 sc->age_flags |= AGE_FLAG_LINK; 429 break; 430 default: 431 break; 432 } 433 } 434 435 /* Stop Rx/Tx MACs. */ 436 age_stop_rxmac(sc); 437 age_stop_txmac(sc); 438 439 /* Program MACs with resolved speed/duplex/flow-control. */ 440 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 441 uint32_t reg; 442 443 age_mac_config(sc); 444 reg = CSR_READ_4(sc, AGE_MAC_CFG); 445 /* Restart DMA engine and Tx/Rx MAC. */ 446 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 447 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 448 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 449 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 450 } 451 } 452 453 /* 454 * Get the current interface media status. 455 */ 456 static void 457 age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 458 { 459 struct age_softc *sc = ifp->if_softc; 460 struct mii_data *mii = &sc->sc_miibus; 461 462 mii_pollstat(mii); 463 ifmr->ifm_status = mii->mii_media_status; 464 ifmr->ifm_active = mii->mii_media_active; 465 } 466 467 /* 468 * Set hardware to newly-selected media. 469 */ 470 static int 471 age_mediachange(struct ifnet *ifp) 472 { 473 struct age_softc *sc = ifp->if_softc; 474 struct mii_data *mii = &sc->sc_miibus; 475 int error; 476 477 if (mii->mii_instance != 0) { 478 struct mii_softc *miisc; 479 480 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 481 mii_phy_reset(miisc); 482 } 483 error = mii_mediachg(mii); 484 485 return error; 486 } 487 488 static int 489 age_intr(void *arg) 490 { 491 struct age_softc *sc = arg; 492 struct ifnet *ifp = &sc->sc_ec.ec_if; 493 struct cmb *cmb; 494 uint32_t status; 495 496 status = CSR_READ_4(sc, AGE_INTR_STATUS); 497 if (status == 0 || (status & AGE_INTRS) == 0) 498 return 0; 499 500 cmb = sc->age_rdata.age_cmb_block; 501 if (cmb == NULL) { 502 /* Happens when bringing up the interface 503 * w/o having a carrier. Ack the interrupt. 504 */ 505 CSR_WRITE_4(sc, AGE_INTR_STATUS, status); 506 return 0; 507 } 508 509 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 510 sc->age_cdata.age_cmb_block_map->dm_mapsize, 511 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 512 status = le32toh(cmb->intr_status); 513 /* ACK/reenable interrupts */ 514 CSR_WRITE_4(sc, AGE_INTR_STATUS, status); 515 while ((status & AGE_INTRS) != 0) { 516 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 517 TPD_CONS_SHIFT; 518 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 519 RRD_PROD_SHIFT; 520 521 /* Let hardware know CMB was served. */ 522 cmb->intr_status = 0; 523 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 524 sc->age_cdata.age_cmb_block_map->dm_mapsize, 525 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 526 527 if (ifp->if_flags & IFF_RUNNING) { 528 if (status & INTR_CMB_RX) 529 age_rxintr(sc, sc->age_rr_prod); 530 531 if (status & INTR_CMB_TX) 532 age_txintr(sc, sc->age_tpd_cons); 533 534 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 535 if (status & INTR_DMA_RD_TO_RST) 536 printf("%s: DMA read error! -- " 537 "resetting\n", 538 device_xname(sc->sc_dev)); 539 if (status & INTR_DMA_WR_TO_RST) 540 printf("%s: DMA write error! -- " 541 "resetting\n", 542 device_xname(sc->sc_dev)); 543 age_init(ifp); 544 } 545 546 if_schedule_deferred_start(ifp); 547 548 if (status & INTR_SMB) 549 age_stats_update(sc); 550 } 551 /* check if more interrupts did came in */ 552 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 553 sc->age_cdata.age_cmb_block_map->dm_mapsize, 554 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 555 status = le32toh(cmb->intr_status); 556 } 557 558 return 1; 559 } 560 561 static void 562 age_get_macaddr(struct age_softc *sc, uint8_t eaddr[]) 563 { 564 uint32_t ea[2], reg; 565 int i, vpdc; 566 567 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 568 if ((reg & SPI_VPD_ENB) != 0) { 569 /* Get VPD stored in TWSI EEPROM. */ 570 reg &= ~SPI_VPD_ENB; 571 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 572 } 573 574 if (pci_get_capability(sc->sc_pct, sc->sc_pcitag, 575 PCI_CAP_VPD, &vpdc, NULL)) { 576 /* 577 * PCI VPD capability found, let TWSI reload EEPROM. 578 * This will set Ethernet address of controller. 579 */ 580 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | 581 TWSI_CTRL_SW_LD_START); 582 for (i = 100; i > 0; i--) { 583 DELAY(1000); 584 reg = CSR_READ_4(sc, AGE_TWSI_CTRL); 585 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 586 break; 587 } 588 if (i == 0) 589 printf("%s: reloading EEPROM timeout!\n", 590 device_xname(sc->sc_dev)); 591 } else { 592 if (agedebug) 593 printf("%s: PCI VPD capability not found!\n", 594 device_xname(sc->sc_dev)); 595 } 596 597 ea[0] = CSR_READ_4(sc, AGE_PAR0); 598 ea[1] = CSR_READ_4(sc, AGE_PAR1); 599 600 eaddr[0] = (ea[1] >> 8) & 0xFF; 601 eaddr[1] = (ea[1] >> 0) & 0xFF; 602 eaddr[2] = (ea[0] >> 24) & 0xFF; 603 eaddr[3] = (ea[0] >> 16) & 0xFF; 604 eaddr[4] = (ea[0] >> 8) & 0xFF; 605 eaddr[5] = (ea[0] >> 0) & 0xFF; 606 } 607 608 static void 609 age_phy_reset(struct age_softc *sc) 610 { 611 uint16_t reg, pn; 612 int i, linkup; 613 614 /* Reset PHY. */ 615 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 616 DELAY(2000); 617 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 618 DELAY(2000); 619 620 #define ATPHY_DBG_ADDR 0x1D 621 #define ATPHY_DBG_DATA 0x1E 622 #define ATPHY_CDTC 0x16 623 #define PHY_CDTC_ENB 0x0001 624 #define PHY_CDTC_POFF 8 625 #define ATPHY_CDTS 0x1C 626 #define PHY_CDTS_STAT_OK 0x0000 627 #define PHY_CDTS_STAT_SHORT 0x0100 628 #define PHY_CDTS_STAT_OPEN 0x0200 629 #define PHY_CDTS_STAT_INVAL 0x0300 630 #define PHY_CDTS_STAT_MASK 0x0300 631 632 /* Check power saving mode. Magic from Linux. */ 633 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET); 634 for (linkup = 0, pn = 0; pn < 4; pn++) { 635 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, ATPHY_CDTC, 636 (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB); 637 for (i = 200; i > 0; i--) { 638 DELAY(1000); 639 age_miibus_readreg(sc->sc_dev, sc->age_phyaddr, 640 ATPHY_CDTC, ®); 641 if ((reg & PHY_CDTC_ENB) == 0) 642 break; 643 } 644 DELAY(1000); 645 age_miibus_readreg(sc->sc_dev, sc->age_phyaddr, 646 ATPHY_CDTS, ®); 647 if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) { 648 linkup++; 649 break; 650 } 651 } 652 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, MII_BMCR, 653 BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 654 if (linkup == 0) { 655 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, 656 ATPHY_DBG_ADDR, 0); 657 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, 658 ATPHY_DBG_DATA, 0x124E); 659 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, 660 ATPHY_DBG_ADDR, 1); 661 age_miibus_readreg(sc->sc_dev, sc->age_phyaddr, 662 ATPHY_DBG_DATA, ®); 663 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, 664 ATPHY_DBG_DATA, reg | 0x03); 665 /* XXX */ 666 DELAY(1500 * 1000); 667 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, 668 ATPHY_DBG_ADDR, 0); 669 age_miibus_writereg(sc->sc_dev, sc->age_phyaddr, 670 ATPHY_DBG_DATA, 0x024E); 671 } 672 673 #undef ATPHY_DBG_ADDR 674 #undef ATPHY_DBG_DATA 675 #undef ATPHY_CDTC 676 #undef PHY_CDTC_ENB 677 #undef PHY_CDTC_POFF 678 #undef ATPHY_CDTS 679 #undef PHY_CDTS_STAT_OK 680 #undef PHY_CDTS_STAT_SHORT 681 #undef PHY_CDTS_STAT_OPEN 682 #undef PHY_CDTS_STAT_INVAL 683 #undef PHY_CDTS_STAT_MASK 684 } 685 686 static int 687 age_dma_alloc(struct age_softc *sc) 688 { 689 struct age_txdesc *txd; 690 struct age_rxdesc *rxd; 691 int nsegs, error, i; 692 693 /* 694 * Create DMA stuffs for TX ring 695 */ 696 error = bus_dmamap_create(sc->sc_dmat, AGE_TX_RING_SZ, 1, 697 AGE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_tx_ring_map); 698 if (error) { 699 sc->age_cdata.age_tx_ring_map = NULL; 700 return ENOBUFS; 701 } 702 703 /* Allocate DMA'able memory for TX ring */ 704 error = bus_dmamem_alloc(sc->sc_dmat, AGE_TX_RING_SZ, 705 PAGE_SIZE, 0, &sc->age_rdata.age_tx_ring_seg, 1, 706 &nsegs, BUS_DMA_NOWAIT); 707 if (error) { 708 printf("%s: could not allocate DMA'able memory for Tx ring, " 709 "error = %i\n", device_xname(sc->sc_dev), error); 710 return error; 711 } 712 713 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_tx_ring_seg, 714 nsegs, AGE_TX_RING_SZ, (void **)&sc->age_rdata.age_tx_ring, 715 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 716 if (error) 717 return ENOBUFS; 718 719 memset(sc->age_rdata.age_tx_ring, 0, AGE_TX_RING_SZ); 720 721 /* Load the DMA map for Tx ring. */ 722 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 723 sc->age_rdata.age_tx_ring, AGE_TX_RING_SZ, NULL, BUS_DMA_NOWAIT); 724 if (error) { 725 printf("%s: could not load DMA'able memory for Tx ring, " 726 "error = %i\n", device_xname(sc->sc_dev), error); 727 bus_dmamem_free(sc->sc_dmat, 728 &sc->age_rdata.age_tx_ring_seg, 1); 729 return error; 730 } 731 732 sc->age_rdata.age_tx_ring_paddr = 733 sc->age_cdata.age_tx_ring_map->dm_segs[0].ds_addr; 734 735 /* 736 * Create DMA stuffs for RX ring 737 */ 738 error = bus_dmamap_create(sc->sc_dmat, AGE_RX_RING_SZ, 1, 739 AGE_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_ring_map); 740 if (error) { 741 sc->age_cdata.age_rx_ring_map = NULL; 742 return ENOBUFS; 743 } 744 745 /* Allocate DMA'able memory for RX ring */ 746 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RX_RING_SZ, 747 PAGE_SIZE, 0, &sc->age_rdata.age_rx_ring_seg, 1, 748 &nsegs, BUS_DMA_NOWAIT); 749 if (error) { 750 printf("%s: could not allocate DMA'able memory for Rx ring, " 751 "error = %i.\n", device_xname(sc->sc_dev), error); 752 return error; 753 } 754 755 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rx_ring_seg, 756 nsegs, AGE_RX_RING_SZ, (void **)&sc->age_rdata.age_rx_ring, 757 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 758 if (error) 759 return ENOBUFS; 760 761 memset(sc->age_rdata.age_rx_ring, 0, AGE_RX_RING_SZ); 762 763 /* Load the DMA map for Rx ring. */ 764 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 765 sc->age_rdata.age_rx_ring, AGE_RX_RING_SZ, NULL, BUS_DMA_NOWAIT); 766 if (error) { 767 printf("%s: could not load DMA'able memory for Rx ring, " 768 "error = %i.\n", device_xname(sc->sc_dev), error); 769 bus_dmamem_free(sc->sc_dmat, 770 &sc->age_rdata.age_rx_ring_seg, 1); 771 return error; 772 } 773 774 sc->age_rdata.age_rx_ring_paddr = 775 sc->age_cdata.age_rx_ring_map->dm_segs[0].ds_addr; 776 777 /* 778 * Create DMA stuffs for RX return ring 779 */ 780 error = bus_dmamap_create(sc->sc_dmat, AGE_RR_RING_SZ, 1, 781 AGE_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rr_ring_map); 782 if (error) { 783 sc->age_cdata.age_rr_ring_map = NULL; 784 return ENOBUFS; 785 } 786 787 /* Allocate DMA'able memory for RX return ring */ 788 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RR_RING_SZ, 789 PAGE_SIZE, 0, &sc->age_rdata.age_rr_ring_seg, 1, 790 &nsegs, BUS_DMA_NOWAIT); 791 if (error) { 792 printf("%s: could not allocate DMA'able memory for Rx " 793 "return ring, error = %i.\n", 794 device_xname(sc->sc_dev), error); 795 return error; 796 } 797 798 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rr_ring_seg, 799 nsegs, AGE_RR_RING_SZ, (void **)&sc->age_rdata.age_rr_ring, 800 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 801 if (error) 802 return ENOBUFS; 803 804 memset(sc->age_rdata.age_rr_ring, 0, AGE_RR_RING_SZ); 805 806 /* Load the DMA map for Rx return ring. */ 807 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 808 sc->age_rdata.age_rr_ring, AGE_RR_RING_SZ, NULL, BUS_DMA_NOWAIT); 809 if (error) { 810 printf("%s: could not load DMA'able memory for Rx return ring, " 811 "error = %i\n", device_xname(sc->sc_dev), error); 812 bus_dmamem_free(sc->sc_dmat, 813 &sc->age_rdata.age_rr_ring_seg, 1); 814 return error; 815 } 816 817 sc->age_rdata.age_rr_ring_paddr = 818 sc->age_cdata.age_rr_ring_map->dm_segs[0].ds_addr; 819 820 /* 821 * Create DMA stuffs for CMB block 822 */ 823 error = bus_dmamap_create(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 1, 824 AGE_CMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 825 &sc->age_cdata.age_cmb_block_map); 826 if (error) { 827 sc->age_cdata.age_cmb_block_map = NULL; 828 return ENOBUFS; 829 } 830 831 /* Allocate DMA'able memory for CMB block */ 832 error = bus_dmamem_alloc(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 833 PAGE_SIZE, 0, &sc->age_rdata.age_cmb_block_seg, 1, 834 &nsegs, BUS_DMA_NOWAIT); 835 if (error) { 836 printf("%s: could not allocate DMA'able memory for " 837 "CMB block, error = %i\n", device_xname(sc->sc_dev), error); 838 return error; 839 } 840 841 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_cmb_block_seg, 842 nsegs, AGE_CMB_BLOCK_SZ, (void **)&sc->age_rdata.age_cmb_block, 843 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 844 if (error) 845 return ENOBUFS; 846 847 memset(sc->age_rdata.age_cmb_block, 0, AGE_CMB_BLOCK_SZ); 848 849 /* Load the DMA map for CMB block. */ 850 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 851 sc->age_rdata.age_cmb_block, AGE_CMB_BLOCK_SZ, NULL, 852 BUS_DMA_NOWAIT); 853 if (error) { 854 printf("%s: could not load DMA'able memory for CMB block, " 855 "error = %i\n", device_xname(sc->sc_dev), error); 856 bus_dmamem_free(sc->sc_dmat, 857 &sc->age_rdata.age_cmb_block_seg, 1); 858 return error; 859 } 860 861 sc->age_rdata.age_cmb_block_paddr = 862 sc->age_cdata.age_cmb_block_map->dm_segs[0].ds_addr; 863 864 /* 865 * Create DMA stuffs for SMB block 866 */ 867 error = bus_dmamap_create(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 1, 868 AGE_SMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 869 &sc->age_cdata.age_smb_block_map); 870 if (error) { 871 sc->age_cdata.age_smb_block_map = NULL; 872 return ENOBUFS; 873 } 874 875 /* Allocate DMA'able memory for SMB block */ 876 error = bus_dmamem_alloc(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 877 PAGE_SIZE, 0, &sc->age_rdata.age_smb_block_seg, 1, 878 &nsegs, BUS_DMA_NOWAIT); 879 if (error) { 880 printf("%s: could not allocate DMA'able memory for " 881 "SMB block, error = %i\n", device_xname(sc->sc_dev), error); 882 return error; 883 } 884 885 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_smb_block_seg, 886 nsegs, AGE_SMB_BLOCK_SZ, (void **)&sc->age_rdata.age_smb_block, 887 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 888 if (error) 889 return ENOBUFS; 890 891 memset(sc->age_rdata.age_smb_block, 0, AGE_SMB_BLOCK_SZ); 892 893 /* Load the DMA map for SMB block */ 894 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 895 sc->age_rdata.age_smb_block, AGE_SMB_BLOCK_SZ, NULL, 896 BUS_DMA_NOWAIT); 897 if (error) { 898 printf("%s: could not load DMA'able memory for SMB block, " 899 "error = %i\n", device_xname(sc->sc_dev), error); 900 bus_dmamem_free(sc->sc_dmat, 901 &sc->age_rdata.age_smb_block_seg, 1); 902 return error; 903 } 904 905 sc->age_rdata.age_smb_block_paddr = 906 sc->age_cdata.age_smb_block_map->dm_segs[0].ds_addr; 907 908 /* 909 * All of the memory we allocated above needs to be within 910 * the same 4GB segment. Make sure this is so. 911 * 912 * XXX We don't care WHAT 4GB segment they're in, just that 913 * XXX they're all in the same one. Need some bus_dma API 914 * XXX help to make this easier to enforce when we actually 915 * XXX perform the allocation. 916 */ 917 if (! (AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr) == 918 AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr) 919 920 && AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr) == 921 AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr) 922 923 && AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr) == 924 AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr) 925 926 && AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr) == 927 AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr))) { 928 aprint_error_dev(sc->sc_dev, 929 "control data allocation constraints failed\n"); 930 return ENOBUFS; 931 } 932 933 /* Create DMA maps for Tx buffers. */ 934 for (i = 0; i < AGE_TX_RING_CNT; i++) { 935 txd = &sc->age_cdata.age_txdesc[i]; 936 txd->tx_m = NULL; 937 txd->tx_dmamap = NULL; 938 error = bus_dmamap_create(sc->sc_dmat, AGE_TSO_MAXSIZE, 939 AGE_MAXTXSEGS, AGE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 940 &txd->tx_dmamap); 941 if (error) { 942 txd->tx_dmamap = NULL; 943 printf("%s: could not create Tx dmamap, error = %i.\n", 944 device_xname(sc->sc_dev), error); 945 return error; 946 } 947 } 948 949 /* Create DMA maps for Rx buffers. */ 950 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 951 BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_sparemap); 952 if (error) { 953 sc->age_cdata.age_rx_sparemap = NULL; 954 printf("%s: could not create spare Rx dmamap, error = %i.\n", 955 device_xname(sc->sc_dev), error); 956 return error; 957 } 958 for (i = 0; i < AGE_RX_RING_CNT; i++) { 959 rxd = &sc->age_cdata.age_rxdesc[i]; 960 rxd->rx_m = NULL; 961 rxd->rx_dmamap = NULL; 962 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 963 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 964 if (error) { 965 rxd->rx_dmamap = NULL; 966 printf("%s: could not create Rx dmamap, error = %i.\n", 967 device_xname(sc->sc_dev), error); 968 return error; 969 } 970 } 971 972 return 0; 973 } 974 975 static void 976 age_dma_free(struct age_softc *sc) 977 { 978 struct age_txdesc *txd; 979 struct age_rxdesc *rxd; 980 int i; 981 982 /* Tx buffers */ 983 for (i = 0; i < AGE_TX_RING_CNT; i++) { 984 txd = &sc->age_cdata.age_txdesc[i]; 985 if (txd->tx_dmamap != NULL) { 986 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 987 txd->tx_dmamap = NULL; 988 } 989 } 990 /* Rx buffers */ 991 for (i = 0; i < AGE_RX_RING_CNT; i++) { 992 rxd = &sc->age_cdata.age_rxdesc[i]; 993 if (rxd->rx_dmamap != NULL) { 994 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 995 rxd->rx_dmamap = NULL; 996 } 997 } 998 if (sc->age_cdata.age_rx_sparemap != NULL) { 999 bus_dmamap_destroy(sc->sc_dmat, sc->age_cdata.age_rx_sparemap); 1000 sc->age_cdata.age_rx_sparemap = NULL; 1001 } 1002 1003 /* Tx ring. */ 1004 if (sc->age_cdata.age_tx_ring_map != NULL) 1005 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_tx_ring_map); 1006 if (sc->age_cdata.age_tx_ring_map != NULL && 1007 sc->age_rdata.age_tx_ring != NULL) 1008 bus_dmamem_free(sc->sc_dmat, 1009 &sc->age_rdata.age_tx_ring_seg, 1); 1010 sc->age_rdata.age_tx_ring = NULL; 1011 sc->age_cdata.age_tx_ring_map = NULL; 1012 1013 /* Rx ring. */ 1014 if (sc->age_cdata.age_rx_ring_map != NULL) 1015 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rx_ring_map); 1016 if (sc->age_cdata.age_rx_ring_map != NULL && 1017 sc->age_rdata.age_rx_ring != NULL) 1018 bus_dmamem_free(sc->sc_dmat, 1019 &sc->age_rdata.age_rx_ring_seg, 1); 1020 sc->age_rdata.age_rx_ring = NULL; 1021 sc->age_cdata.age_rx_ring_map = NULL; 1022 1023 /* Rx return ring. */ 1024 if (sc->age_cdata.age_rr_ring_map != NULL) 1025 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rr_ring_map); 1026 if (sc->age_cdata.age_rr_ring_map != NULL && 1027 sc->age_rdata.age_rr_ring != NULL) 1028 bus_dmamem_free(sc->sc_dmat, 1029 &sc->age_rdata.age_rr_ring_seg, 1); 1030 sc->age_rdata.age_rr_ring = NULL; 1031 sc->age_cdata.age_rr_ring_map = NULL; 1032 1033 /* CMB block */ 1034 if (sc->age_cdata.age_cmb_block_map != NULL) 1035 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_cmb_block_map); 1036 if (sc->age_cdata.age_cmb_block_map != NULL && 1037 sc->age_rdata.age_cmb_block != NULL) 1038 bus_dmamem_free(sc->sc_dmat, 1039 &sc->age_rdata.age_cmb_block_seg, 1); 1040 sc->age_rdata.age_cmb_block = NULL; 1041 sc->age_cdata.age_cmb_block_map = NULL; 1042 1043 /* SMB block */ 1044 if (sc->age_cdata.age_smb_block_map != NULL) 1045 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_smb_block_map); 1046 if (sc->age_cdata.age_smb_block_map != NULL && 1047 sc->age_rdata.age_smb_block != NULL) 1048 bus_dmamem_free(sc->sc_dmat, 1049 &sc->age_rdata.age_smb_block_seg, 1); 1050 sc->age_rdata.age_smb_block = NULL; 1051 sc->age_cdata.age_smb_block_map = NULL; 1052 } 1053 1054 static void 1055 age_start(struct ifnet *ifp) 1056 { 1057 struct age_softc *sc = ifp->if_softc; 1058 struct mbuf *m_head; 1059 int enq, error; 1060 1061 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1062 return; 1063 if ((sc->age_flags & AGE_FLAG_LINK) == 0) 1064 return; 1065 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1066 return; 1067 1068 enq = 0; 1069 for (;;) { 1070 IFQ_POLL(&ifp->if_snd, m_head); 1071 if (m_head == NULL) 1072 break; 1073 1074 /* 1075 * Pack the data into the transmit ring. If we 1076 * don't have room, set the OACTIVE flag and wait 1077 * for the NIC to drain the ring. 1078 */ 1079 if ((error = age_encap(sc, m_head)) != 0) { 1080 if (error == EFBIG) { 1081 /* This is fatal for the packet. */ 1082 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1083 m_freem(m_head); 1084 if_statinc(ifp, if_oerrors); 1085 continue; 1086 } 1087 ifp->if_flags |= IFF_OACTIVE; 1088 break; 1089 } 1090 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1091 enq = 1; 1092 1093 /* 1094 * If there's a BPF listener, bounce a copy of this frame 1095 * to him. 1096 */ 1097 bpf_mtap(ifp, m_head, BPF_D_OUT); 1098 } 1099 1100 if (enq) { 1101 /* Update mbox. */ 1102 AGE_COMMIT_MBOX(sc); 1103 /* Set a timeout in case the chip goes out to lunch. */ 1104 ifp->if_timer = AGE_TX_TIMEOUT; 1105 } 1106 } 1107 1108 static void 1109 age_watchdog(struct ifnet *ifp) 1110 { 1111 struct age_softc *sc = ifp->if_softc; 1112 1113 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1114 printf("%s: watchdog timeout (missed link)\n", 1115 device_xname(sc->sc_dev)); 1116 if_statinc(ifp, if_oerrors); 1117 age_init(ifp); 1118 return; 1119 } 1120 1121 if (sc->age_cdata.age_tx_cnt == 0) { 1122 printf("%s: watchdog timeout (missed Tx interrupts) " 1123 "-- recovering\n", device_xname(sc->sc_dev)); 1124 age_start(ifp); 1125 return; 1126 } 1127 1128 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1129 if_statinc(ifp, if_oerrors); 1130 age_init(ifp); 1131 age_start(ifp); 1132 } 1133 1134 static bool 1135 age_shutdown(device_t self, int howto) 1136 { 1137 struct age_softc *sc; 1138 struct ifnet *ifp; 1139 1140 sc = device_private(self); 1141 ifp = &sc->sc_ec.ec_if; 1142 age_stop(ifp, 1); 1143 1144 return true; 1145 } 1146 1147 static int 1148 age_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1149 { 1150 struct age_softc *sc = ifp->if_softc; 1151 int s, error; 1152 1153 s = splnet(); 1154 1155 error = ether_ioctl(ifp, cmd, data); 1156 if (error == ENETRESET) { 1157 if (ifp->if_flags & IFF_RUNNING) 1158 age_rxfilter(sc); 1159 error = 0; 1160 } 1161 1162 splx(s); 1163 return error; 1164 } 1165 1166 static void 1167 age_mac_config(struct age_softc *sc) 1168 { 1169 struct mii_data *mii; 1170 uint32_t reg; 1171 1172 mii = &sc->sc_miibus; 1173 1174 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1175 reg &= ~MAC_CFG_FULL_DUPLEX; 1176 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1177 reg &= ~MAC_CFG_SPEED_MASK; 1178 1179 /* Reprogram MAC with resolved speed/duplex. */ 1180 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1181 case IFM_10_T: 1182 case IFM_100_TX: 1183 reg |= MAC_CFG_SPEED_10_100; 1184 break; 1185 case IFM_1000_T: 1186 reg |= MAC_CFG_SPEED_1000; 1187 break; 1188 } 1189 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1190 reg |= MAC_CFG_FULL_DUPLEX; 1191 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1192 reg |= MAC_CFG_TX_FC; 1193 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1194 reg |= MAC_CFG_RX_FC; 1195 } 1196 1197 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1198 } 1199 1200 static bool 1201 age_resume(device_t dv, const pmf_qual_t *qual) 1202 { 1203 struct age_softc *sc = device_private(dv); 1204 uint16_t cmd; 1205 1206 /* 1207 * Clear INTx emulation disable for hardware that 1208 * is set in resume event. From Linux. 1209 */ 1210 cmd = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 1211 if ((cmd & PCI_COMMAND_INTERRUPT_DISABLE) != 0) { 1212 cmd &= ~PCI_COMMAND_INTERRUPT_DISABLE; 1213 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 1214 PCI_COMMAND_STATUS_REG, cmd); 1215 } 1216 1217 return true; 1218 } 1219 1220 static int 1221 age_encap(struct age_softc *sc, struct mbuf * const m) 1222 { 1223 struct age_txdesc *txd, *txd_last; 1224 struct tx_desc *desc; 1225 bus_dmamap_t map; 1226 uint32_t cflags, poff, vtag; 1227 int error, i, nsegs, prod; 1228 1229 cflags = vtag = 0; 1230 poff = 0; 1231 1232 prod = sc->age_cdata.age_tx_prod; 1233 txd = &sc->age_cdata.age_txdesc[prod]; 1234 txd_last = txd; 1235 map = txd->tx_dmamap; 1236 1237 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT); 1238 if (error == EFBIG) { 1239 struct mbuf *mnew = m_defrag(m, M_NOWAIT); 1240 if (mnew != NULL) { 1241 KASSERT(m == mnew); 1242 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, mnew, 1243 BUS_DMA_NOWAIT); 1244 } else { 1245 /* Just drop if we can't defrag. */ 1246 error = EFBIG; 1247 } 1248 if (error) { 1249 if (error == EFBIG) { 1250 printf("%s: Tx packet consumes too many " 1251 "DMA segments, dropping...\n", 1252 device_xname(sc->sc_dev)); 1253 } 1254 return error; 1255 } 1256 } else if (error) { 1257 return error; 1258 } 1259 1260 nsegs = map->dm_nsegs; 1261 KASSERT(nsegs != 0); 1262 1263 /* Check descriptor overrun. */ 1264 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1265 bus_dmamap_unload(sc->sc_dmat, map); 1266 return ENOBUFS; 1267 } 1268 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1269 BUS_DMASYNC_PREWRITE); 1270 1271 /* Configure Tx IP/TCP/UDP checksum offload. */ 1272 if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1273 cflags |= AGE_TD_CSUM; 1274 if ((m->m_pkthdr.csum_flags & M_CSUM_TCPv4) != 0) 1275 cflags |= AGE_TD_TCPCSUM; 1276 if ((m->m_pkthdr.csum_flags & M_CSUM_UDPv4) != 0) 1277 cflags |= AGE_TD_UDPCSUM; 1278 /* Set checksum start offset. */ 1279 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1280 } 1281 1282 #if NVLAN > 0 1283 /* Configure VLAN hardware tag insertion. */ 1284 if (vlan_has_tag(m)) { 1285 vtag = AGE_TX_VLAN_TAG(htons(vlan_get_tag(m))); 1286 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1287 cflags |= AGE_TD_INSERT_VLAN_TAG; 1288 } 1289 #endif 1290 1291 desc = NULL; 1292 KASSERT(nsegs > 0); 1293 for (i = 0; ; i++) { 1294 desc = &sc->age_rdata.age_tx_ring[prod]; 1295 desc->addr = htole64(map->dm_segs[i].ds_addr); 1296 desc->len = 1297 htole32(AGE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 1298 desc->flags = htole32(cflags); 1299 sc->age_cdata.age_tx_cnt++; 1300 if (i == (nsegs - 1)) 1301 break; 1302 1303 /* Sync this descriptor and go to the next one */ 1304 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 1305 prod * sizeof(struct tx_desc), sizeof(struct tx_desc), 1306 BUS_DMASYNC_PREWRITE); 1307 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1308 } 1309 1310 /* Set EOP on the last descriptor and sync it. */ 1311 desc->flags |= htole32(AGE_TD_EOP); 1312 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 1313 prod * sizeof(struct tx_desc), sizeof(struct tx_desc), 1314 BUS_DMASYNC_PREWRITE); 1315 1316 if (nsegs > 1) { 1317 /* Swap dmamap of the first and the last. */ 1318 txd = &sc->age_cdata.age_txdesc[prod]; 1319 map = txd_last->tx_dmamap; 1320 txd_last->tx_dmamap = txd->tx_dmamap; 1321 txd->tx_dmamap = map; 1322 txd->tx_m = m; 1323 KASSERT(txd_last->tx_m == NULL); 1324 } else { 1325 KASSERT(txd_last == &sc->age_cdata.age_txdesc[prod]); 1326 txd_last->tx_m = m; 1327 } 1328 1329 /* Update producer index. */ 1330 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1331 sc->age_cdata.age_tx_prod = prod; 1332 1333 return 0; 1334 } 1335 1336 static void 1337 age_txintr(struct age_softc *sc, int tpd_cons) 1338 { 1339 struct ifnet *ifp = &sc->sc_ec.ec_if; 1340 struct age_txdesc *txd; 1341 int cons, prog; 1342 1343 if (sc->age_cdata.age_tx_cnt <= 0) { 1344 if (ifp->if_timer != 0) 1345 printf("timer running without packets\n"); 1346 if (sc->age_cdata.age_tx_cnt) 1347 printf("age_tx_cnt corrupted\n"); 1348 } 1349 1350 /* 1351 * Go through our Tx list and free mbufs for those 1352 * frames which have been transmitted. 1353 */ 1354 cons = sc->age_cdata.age_tx_cons; 1355 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 1356 if (sc->age_cdata.age_tx_cnt <= 0) 1357 break; 1358 prog++; 1359 ifp->if_flags &= ~IFF_OACTIVE; 1360 sc->age_cdata.age_tx_cnt--; 1361 txd = &sc->age_cdata.age_txdesc[cons]; 1362 /* 1363 * Clear Tx descriptors, it's not required but would 1364 * help debugging in case of Tx issues. 1365 */ 1366 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 1367 cons * sizeof(struct tx_desc), sizeof(struct tx_desc), 1368 BUS_DMASYNC_POSTWRITE); 1369 txd->tx_desc->addr = 0; 1370 txd->tx_desc->len = 0; 1371 txd->tx_desc->flags = 0; 1372 1373 if (txd->tx_m == NULL) 1374 continue; 1375 /* Reclaim transmitted mbufs. */ 1376 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1377 m_freem(txd->tx_m); 1378 txd->tx_m = NULL; 1379 } 1380 1381 if (prog > 0) { 1382 sc->age_cdata.age_tx_cons = cons; 1383 1384 /* 1385 * Unarm watchdog timer only when there are no pending 1386 * Tx descriptors in queue. 1387 */ 1388 if (sc->age_cdata.age_tx_cnt == 0) 1389 ifp->if_timer = 0; 1390 } 1391 } 1392 1393 /* Receive a frame. */ 1394 static void 1395 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 1396 { 1397 struct ifnet *ifp = &sc->sc_ec.ec_if; 1398 struct age_rxdesc *rxd; 1399 struct rx_desc *desc; 1400 struct mbuf *mp, *m; 1401 uint32_t status, index; 1402 int count, nsegs, pktlen; 1403 int rx_cons; 1404 1405 status = le32toh(rxrd->flags); 1406 index = le32toh(rxrd->index); 1407 rx_cons = AGE_RX_CONS(index); 1408 nsegs = AGE_RX_NSEGS(index); 1409 1410 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 1411 if ((status & AGE_RRD_ERROR) != 0 && 1412 (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 1413 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) { 1414 /* 1415 * We want to pass the following frames to upper 1416 * layer regardless of error status of Rx return 1417 * ring. 1418 * 1419 * o IP/TCP/UDP checksum is bad. 1420 * o frame length and protocol specific length 1421 * does not match. 1422 */ 1423 sc->age_cdata.age_rx_cons += nsegs; 1424 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1425 return; 1426 } 1427 1428 pktlen = 0; 1429 for (count = 0; count < nsegs; count++, 1430 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 1431 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 1432 mp = rxd->rx_m; 1433 desc = rxd->rx_desc; 1434 /* Add a new receive buffer to the ring. */ 1435 if (age_newbuf(sc, rxd, 0) != 0) { 1436 if_statinc(ifp, if_iqdrops); 1437 /* Reuse Rx buffers. */ 1438 if (sc->age_cdata.age_rxhead != NULL) { 1439 m_freem(sc->age_cdata.age_rxhead); 1440 AGE_RXCHAIN_RESET(sc); 1441 } 1442 break; 1443 } 1444 1445 /* The length of the first mbuf is computed last. */ 1446 if (count != 0) { 1447 mp->m_len = AGE_RX_BYTES(le32toh(desc->len)); 1448 pktlen += mp->m_len; 1449 } 1450 1451 /* Chain received mbufs. */ 1452 if (sc->age_cdata.age_rxhead == NULL) { 1453 sc->age_cdata.age_rxhead = mp; 1454 sc->age_cdata.age_rxtail = mp; 1455 } else { 1456 m_remove_pkthdr(mp); 1457 sc->age_cdata.age_rxprev_tail = 1458 sc->age_cdata.age_rxtail; 1459 sc->age_cdata.age_rxtail->m_next = mp; 1460 sc->age_cdata.age_rxtail = mp; 1461 } 1462 1463 if (count == nsegs - 1) { 1464 /* 1465 * It seems that L1 controller has no way 1466 * to tell hardware to strip CRC bytes. 1467 */ 1468 sc->age_cdata.age_rxlen -= ETHER_CRC_LEN; 1469 if (nsegs > 1) { 1470 /* Remove the CRC bytes in chained mbufs. */ 1471 pktlen -= ETHER_CRC_LEN; 1472 if (mp->m_len <= ETHER_CRC_LEN) { 1473 sc->age_cdata.age_rxtail = 1474 sc->age_cdata.age_rxprev_tail; 1475 sc->age_cdata.age_rxtail->m_len -= 1476 (ETHER_CRC_LEN - mp->m_len); 1477 sc->age_cdata.age_rxtail->m_next = NULL; 1478 m_freem(mp); 1479 } else { 1480 mp->m_len -= ETHER_CRC_LEN; 1481 } 1482 } 1483 1484 m = sc->age_cdata.age_rxhead; 1485 KASSERT(m->m_flags & M_PKTHDR); 1486 m_set_rcvif(m, ifp); 1487 m->m_pkthdr.len = sc->age_cdata.age_rxlen; 1488 /* Set the first mbuf length. */ 1489 m->m_len = sc->age_cdata.age_rxlen - pktlen; 1490 1491 /* 1492 * Set checksum information. 1493 * It seems that L1 controller can compute partial 1494 * checksum. The partial checksum value can be used 1495 * to accelerate checksum computation for fragmented 1496 * TCP/UDP packets. Upper network stack already 1497 * takes advantage of the partial checksum value in 1498 * IP reassembly stage. But I'm not sure the 1499 * correctness of the partial hardware checksum 1500 * assistance due to lack of data sheet. If it is 1501 * proven to work on L1 I'll enable it. 1502 */ 1503 if (status & AGE_RRD_IPV4) { 1504 if (status & AGE_RRD_IPCSUM_NOK) 1505 m->m_pkthdr.csum_flags |= 1506 M_CSUM_IPv4_BAD; 1507 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 1508 (status & AGE_RRD_TCP_UDPCSUM_NOK)) { 1509 m->m_pkthdr.csum_flags |= 1510 M_CSUM_TCP_UDP_BAD; 1511 } 1512 /* 1513 * Don't mark bad checksum for TCP/UDP frames 1514 * as fragmented frames may always have set 1515 * bad checksummed bit of descriptor status. 1516 */ 1517 } 1518 #if NVLAN > 0 1519 /* Check for VLAN tagged frames. */ 1520 if (status & AGE_RRD_VLAN) { 1521 uint32_t vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 1522 vlan_set_tag(m, AGE_RX_VLAN_TAG(vtag)); 1523 } 1524 #endif 1525 1526 /* Pass it on. */ 1527 if_percpuq_enqueue(ifp->if_percpuq, m); 1528 1529 /* Reset mbuf chains. */ 1530 AGE_RXCHAIN_RESET(sc); 1531 } 1532 } 1533 1534 if (count != nsegs) { 1535 sc->age_cdata.age_rx_cons += nsegs; 1536 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1537 } else 1538 sc->age_cdata.age_rx_cons = rx_cons; 1539 } 1540 1541 static void 1542 age_rxintr(struct age_softc *sc, int rr_prod) 1543 { 1544 struct rx_rdesc *rxrd; 1545 int rr_cons, nsegs, pktlen, prog; 1546 1547 rr_cons = sc->age_cdata.age_rr_cons; 1548 if (rr_cons == rr_prod) 1549 return; 1550 1551 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1552 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1553 BUS_DMASYNC_POSTREAD); 1554 1555 for (prog = 0; rr_cons != rr_prod; prog++) { 1556 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 1557 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 1558 if (nsegs == 0) 1559 break; 1560 /* 1561 * Check number of segments against received bytes 1562 * Non-matching value would indicate that hardware 1563 * is still trying to update Rx return descriptors. 1564 * I'm not sure whether this check is really needed. 1565 */ 1566 pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 1567 if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) / 1568 (MCLBYTES - ETHER_ALIGN))) 1569 break; 1570 1571 /* Received a frame. */ 1572 age_rxeof(sc, rxrd); 1573 1574 /* Clear return ring. */ 1575 rxrd->index = 0; 1576 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 1577 } 1578 1579 if (prog > 0) { 1580 /* Update the consumer index. */ 1581 sc->age_cdata.age_rr_cons = rr_cons; 1582 1583 /* Sync descriptors. */ 1584 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1585 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1586 BUS_DMASYNC_PREWRITE); 1587 1588 /* Notify hardware availability of new Rx buffers. */ 1589 AGE_COMMIT_MBOX(sc); 1590 } 1591 } 1592 1593 static void 1594 age_tick(void *xsc) 1595 { 1596 struct age_softc *sc = xsc; 1597 struct mii_data *mii = &sc->sc_miibus; 1598 int s; 1599 1600 s = splnet(); 1601 mii_tick(mii); 1602 splx(s); 1603 1604 callout_schedule(&sc->sc_tick_ch, hz); 1605 } 1606 1607 static void 1608 age_reset(struct age_softc *sc) 1609 { 1610 uint32_t reg; 1611 int i; 1612 1613 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 1614 CSR_READ_4(sc, AGE_MASTER_CFG); 1615 DELAY(1000); 1616 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1617 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1618 break; 1619 DELAY(10); 1620 } 1621 1622 if (i == 0) 1623 printf("%s: reset timeout(0x%08x)!\n", device_xname(sc->sc_dev), 1624 reg); 1625 1626 /* Initialize PCIe module. From Linux. */ 1627 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1628 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1629 } 1630 1631 static int 1632 age_init(struct ifnet *ifp) 1633 { 1634 struct age_softc *sc = ifp->if_softc; 1635 struct mii_data *mii; 1636 uint8_t eaddr[ETHER_ADDR_LEN]; 1637 bus_addr_t paddr; 1638 uint32_t reg, fsize; 1639 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 1640 int error; 1641 1642 /* 1643 * Cancel any pending I/O. 1644 */ 1645 age_stop(ifp, 0); 1646 1647 /* 1648 * Reset the chip to a known state. 1649 */ 1650 age_reset(sc); 1651 1652 /* Initialize descriptors. */ 1653 error = age_init_rx_ring(sc); 1654 if (error != 0) { 1655 printf("%s: no memory for Rx buffers.\n", device_xname(sc->sc_dev)); 1656 age_stop(ifp, 0); 1657 return error; 1658 } 1659 age_init_rr_ring(sc); 1660 age_init_tx_ring(sc); 1661 age_init_cmb_block(sc); 1662 age_init_smb_block(sc); 1663 1664 /* Reprogram the station address. */ 1665 memcpy(eaddr, CLLADDR(ifp->if_sadl), sizeof(eaddr)); 1666 CSR_WRITE_4(sc, AGE_PAR0, 1667 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1668 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 1669 1670 /* Set descriptor base addresses. */ 1671 paddr = sc->age_rdata.age_tx_ring_paddr; 1672 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 1673 paddr = sc->age_rdata.age_rx_ring_paddr; 1674 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 1675 paddr = sc->age_rdata.age_rr_ring_paddr; 1676 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 1677 paddr = sc->age_rdata.age_tx_ring_paddr; 1678 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 1679 paddr = sc->age_rdata.age_cmb_block_paddr; 1680 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1681 paddr = sc->age_rdata.age_smb_block_paddr; 1682 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1683 1684 /* Set Rx/Rx return descriptor counter. */ 1685 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 1686 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 1687 DESC_RRD_CNT_MASK) | 1688 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 1689 1690 /* Set Tx descriptor counter. */ 1691 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 1692 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 1693 1694 /* Tell hardware that we're ready to load descriptors. */ 1695 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 1696 1697 /* 1698 * Initialize mailbox register. 1699 * Updated producer/consumer index information is exchanged 1700 * through this mailbox register. However Tx producer and 1701 * Rx return consumer/Rx producer are all shared such that 1702 * it's hard to separate code path between Tx and Rx without 1703 * locking. If L1 hardware have a separate mail box register 1704 * for Tx and Rx consumer/producer management we could have 1705 * independent Tx/Rx handler which in turn Rx handler could have 1706 * been run without any locking. 1707 */ 1708 AGE_COMMIT_MBOX(sc); 1709 1710 /* Configure IPG/IFG parameters. */ 1711 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 1712 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 1713 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1714 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1715 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 1716 1717 /* Set parameters for half-duplex media. */ 1718 CSR_WRITE_4(sc, AGE_HDPX_CFG, 1719 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1720 HDPX_CFG_LCOL_MASK) | 1721 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1722 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1723 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1724 HDPX_CFG_ABEBT_MASK) | 1725 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1726 HDPX_CFG_JAMIPG_MASK)); 1727 1728 /* Configure interrupt moderation timer. */ 1729 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 1730 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 1731 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 1732 reg &= ~MASTER_MTIMER_ENB; 1733 if (AGE_USECS(sc->age_int_mod) == 0) 1734 reg &= ~MASTER_ITIMER_ENB; 1735 else 1736 reg |= MASTER_ITIMER_ENB; 1737 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 1738 if (agedebug) 1739 printf("%s: interrupt moderation is %d us.\n", 1740 device_xname(sc->sc_dev), sc->age_int_mod); 1741 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 1742 1743 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 1744 if (ifp->if_mtu < ETHERMTU) 1745 sc->age_max_frame_size = ETHERMTU; 1746 else 1747 sc->age_max_frame_size = ifp->if_mtu; 1748 sc->age_max_frame_size += ETHER_HDR_LEN + 1749 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 1750 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 1751 1752 /* Configure jumbo frame. */ 1753 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 1754 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 1755 (((fsize / sizeof(uint64_t)) << 1756 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 1757 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 1758 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 1759 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 1760 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 1761 1762 /* Configure flow-control parameters. From Linux. */ 1763 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 1764 /* 1765 * Magic workaround for old-L1. 1766 * Don't know which hw revision requires this magic. 1767 */ 1768 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1769 /* 1770 * Another magic workaround for flow-control mode 1771 * change. From Linux. 1772 */ 1773 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1774 } 1775 /* 1776 * TODO 1777 * Should understand pause parameter relationships between FIFO 1778 * size and number of Rx descriptors and Rx return descriptors. 1779 * 1780 * Magic parameters came from Linux. 1781 */ 1782 switch (sc->age_chip_rev) { 1783 case 0x8001: 1784 case 0x9001: 1785 case 0x9002: 1786 case 0x9003: 1787 rxf_hi = AGE_RX_RING_CNT / 16; 1788 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 1789 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 1790 rrd_lo = AGE_RR_RING_CNT / 16; 1791 break; 1792 default: 1793 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 1794 rxf_lo = reg / 16; 1795 if (rxf_lo < 192) 1796 rxf_lo = 192; 1797 rxf_hi = (reg * 7) / 8; 1798 if (rxf_hi < rxf_lo) 1799 rxf_hi = rxf_lo + 16; 1800 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 1801 rrd_lo = reg / 8; 1802 rrd_hi = (reg * 7) / 8; 1803 if (rrd_lo < 2) 1804 rrd_lo = 2; 1805 if (rrd_hi < rrd_lo) 1806 rrd_hi = rrd_lo + 3; 1807 break; 1808 } 1809 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 1810 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 1811 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 1812 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 1813 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 1814 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 1815 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 1816 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 1817 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 1818 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 1819 1820 /* Configure RxQ. */ 1821 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1822 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 1823 RXQ_CFG_RD_BURST_MASK) | 1824 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 1825 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 1826 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 1827 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 1828 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1829 1830 /* Configure TxQ. */ 1831 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1832 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1833 TXQ_CFG_TPD_BURST_MASK) | 1834 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 1835 TXQ_CFG_TX_FIFO_BURST_MASK) | 1836 ((TXQ_CFG_TPD_FETCH_DEFAULT << 1837 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 1838 TXQ_CFG_ENB); 1839 1840 /* Configure DMA parameters. */ 1841 CSR_WRITE_4(sc, AGE_DMA_CFG, 1842 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 1843 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 1844 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 1845 1846 /* Configure CMB DMA write threshold. */ 1847 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 1848 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 1849 CMB_WR_THRESH_RRD_MASK) | 1850 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 1851 CMB_WR_THRESH_TPD_MASK)); 1852 1853 /* Set CMB/SMB timer and enable them. */ 1854 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 1855 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 1856 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 1857 1858 /* Request SMB updates for every seconds. */ 1859 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 1860 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 1861 1862 /* 1863 * Disable all WOL bits as WOL can interfere normal Rx 1864 * operation. 1865 */ 1866 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1867 1868 /* 1869 * Configure Tx/Rx MACs. 1870 * - Auto-padding for short frames. 1871 * - Enable CRC generation. 1872 * Start with full-duplex/1000Mbps media. Actual reconfiguration 1873 * of MAC is followed after link establishment. 1874 */ 1875 CSR_WRITE_4(sc, AGE_MAC_CFG, 1876 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 1877 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 1878 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1879 MAC_CFG_PREAMBLE_MASK)); 1880 1881 /* Set up the receive filter. */ 1882 age_rxfilter(sc); 1883 age_rxvlan(sc); 1884 1885 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1886 reg |= MAC_CFG_RXCSUM_ENB; 1887 1888 /* Ack all pending interrupts and clear it. */ 1889 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 1890 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 1891 1892 /* Finally enable Tx/Rx MAC. */ 1893 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 1894 1895 sc->age_flags &= ~AGE_FLAG_LINK; 1896 1897 /* Switch to the current media. */ 1898 mii = &sc->sc_miibus; 1899 mii_mediachg(mii); 1900 1901 callout_schedule(&sc->sc_tick_ch, hz); 1902 1903 ifp->if_flags |= IFF_RUNNING; 1904 ifp->if_flags &= ~IFF_OACTIVE; 1905 1906 return 0; 1907 } 1908 1909 static void 1910 age_stop(struct ifnet *ifp, int disable) 1911 { 1912 struct age_softc *sc = ifp->if_softc; 1913 struct age_txdesc *txd; 1914 struct age_rxdesc *rxd; 1915 uint32_t reg; 1916 int i; 1917 1918 callout_stop(&sc->sc_tick_ch); 1919 1920 /* 1921 * Mark the interface down and cancel the watchdog timer. 1922 */ 1923 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1924 ifp->if_timer = 0; 1925 1926 sc->age_flags &= ~AGE_FLAG_LINK; 1927 1928 mii_down(&sc->sc_miibus); 1929 1930 /* 1931 * Disable interrupts. 1932 */ 1933 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 1934 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 1935 1936 /* Stop CMB/SMB updates. */ 1937 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 1938 1939 /* Stop Rx/Tx MAC. */ 1940 age_stop_rxmac(sc); 1941 age_stop_txmac(sc); 1942 1943 /* Stop DMA. */ 1944 CSR_WRITE_4(sc, AGE_DMA_CFG, 1945 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 1946 1947 /* Stop TxQ/RxQ. */ 1948 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1949 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 1950 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1951 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 1952 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1953 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1954 break; 1955 DELAY(10); 1956 } 1957 if (i == 0) 1958 printf("%s: stopping Rx/Tx MACs timed out(0x%08x)!\n", 1959 device_xname(sc->sc_dev), reg); 1960 1961 /* Reclaim Rx buffers that have been processed. */ 1962 if (sc->age_cdata.age_rxhead != NULL) 1963 m_freem(sc->age_cdata.age_rxhead); 1964 AGE_RXCHAIN_RESET(sc); 1965 1966 /* 1967 * Free RX and TX mbufs still in the queues. 1968 */ 1969 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1970 rxd = &sc->age_cdata.age_rxdesc[i]; 1971 if (rxd->rx_m != NULL) { 1972 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1973 m_freem(rxd->rx_m); 1974 rxd->rx_m = NULL; 1975 } 1976 } 1977 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1978 txd = &sc->age_cdata.age_txdesc[i]; 1979 if (txd->tx_m != NULL) { 1980 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1981 m_freem(txd->tx_m); 1982 txd->tx_m = NULL; 1983 } 1984 } 1985 } 1986 1987 static void 1988 age_stats_update(struct age_softc *sc) 1989 { 1990 struct ifnet *ifp = &sc->sc_ec.ec_if; 1991 struct age_stats *stat; 1992 struct smb *smb; 1993 1994 stat = &sc->age_stat; 1995 1996 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 1997 sc->age_cdata.age_smb_block_map->dm_mapsize, 1998 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1999 2000 smb = sc->age_rdata.age_smb_block; 2001 if (smb->updated == 0) 2002 return; 2003 2004 /* Rx stats. */ 2005 stat->rx_frames += smb->rx_frames; 2006 stat->rx_bcast_frames += smb->rx_bcast_frames; 2007 stat->rx_mcast_frames += smb->rx_mcast_frames; 2008 stat->rx_pause_frames += smb->rx_pause_frames; 2009 stat->rx_control_frames += smb->rx_control_frames; 2010 stat->rx_crcerrs += smb->rx_crcerrs; 2011 stat->rx_lenerrs += smb->rx_lenerrs; 2012 stat->rx_bytes += smb->rx_bytes; 2013 stat->rx_runts += smb->rx_runts; 2014 stat->rx_fragments += smb->rx_fragments; 2015 stat->rx_pkts_64 += smb->rx_pkts_64; 2016 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2017 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2018 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2019 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2020 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2021 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2022 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2023 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2024 stat->rx_desc_oflows += smb->rx_desc_oflows; 2025 stat->rx_alignerrs += smb->rx_alignerrs; 2026 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2027 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2028 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2029 2030 /* Tx stats. */ 2031 stat->tx_frames += smb->tx_frames; 2032 stat->tx_bcast_frames += smb->tx_bcast_frames; 2033 stat->tx_mcast_frames += smb->tx_mcast_frames; 2034 stat->tx_pause_frames += smb->tx_pause_frames; 2035 stat->tx_excess_defer += smb->tx_excess_defer; 2036 stat->tx_control_frames += smb->tx_control_frames; 2037 stat->tx_deferred += smb->tx_deferred; 2038 stat->tx_bytes += smb->tx_bytes; 2039 stat->tx_pkts_64 += smb->tx_pkts_64; 2040 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2041 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2042 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2043 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2044 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2045 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2046 stat->tx_single_colls += smb->tx_single_colls; 2047 stat->tx_multi_colls += smb->tx_multi_colls; 2048 stat->tx_late_colls += smb->tx_late_colls; 2049 stat->tx_excess_colls += smb->tx_excess_colls; 2050 stat->tx_underrun += smb->tx_underrun; 2051 stat->tx_desc_underrun += smb->tx_desc_underrun; 2052 stat->tx_lenerrs += smb->tx_lenerrs; 2053 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2054 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2055 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2056 2057 /* Update counters in ifnet. */ 2058 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 2059 2060 if_statadd_ref(nsr, if_opackets, smb->tx_frames); 2061 2062 if_statadd_ref(nsr, if_collisions, 2063 smb->tx_single_colls + 2064 smb->tx_multi_colls + smb->tx_late_colls + 2065 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 2066 2067 if_statadd_ref(nsr, if_oerrors, 2068 smb->tx_excess_colls + 2069 smb->tx_late_colls + smb->tx_underrun + 2070 smb->tx_pkts_truncated); 2071 2072 if_statadd_ref(nsr, if_ierrors, 2073 smb->rx_crcerrs + smb->rx_lenerrs + 2074 smb->rx_runts + smb->rx_pkts_truncated + 2075 smb->rx_fifo_oflows + smb->rx_desc_oflows + 2076 smb->rx_alignerrs); 2077 2078 IF_STAT_PUTREF(ifp); 2079 2080 /* Update done, clear. */ 2081 smb->updated = 0; 2082 2083 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2084 sc->age_cdata.age_smb_block_map->dm_mapsize, 2085 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2086 } 2087 2088 static void 2089 age_stop_txmac(struct age_softc *sc) 2090 { 2091 uint32_t reg; 2092 int i; 2093 2094 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2095 if ((reg & MAC_CFG_TX_ENB) != 0) { 2096 reg &= ~MAC_CFG_TX_ENB; 2097 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2098 } 2099 /* Stop Tx DMA engine. */ 2100 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2101 if ((reg & DMA_CFG_RD_ENB) != 0) { 2102 reg &= ~DMA_CFG_RD_ENB; 2103 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2104 } 2105 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2106 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2107 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2108 break; 2109 DELAY(10); 2110 } 2111 if (i == 0) 2112 printf("%s: stopping TxMAC timeout!\n", device_xname(sc->sc_dev)); 2113 } 2114 2115 static void 2116 age_stop_rxmac(struct age_softc *sc) 2117 { 2118 uint32_t reg; 2119 int i; 2120 2121 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2122 if ((reg & MAC_CFG_RX_ENB) != 0) { 2123 reg &= ~MAC_CFG_RX_ENB; 2124 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2125 } 2126 /* Stop Rx DMA engine. */ 2127 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2128 if ((reg & DMA_CFG_WR_ENB) != 0) { 2129 reg &= ~DMA_CFG_WR_ENB; 2130 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2131 } 2132 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2133 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2134 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2135 break; 2136 DELAY(10); 2137 } 2138 if (i == 0) 2139 printf("%s: stopping RxMAC timeout!\n", device_xname(sc->sc_dev)); 2140 } 2141 2142 static void 2143 age_init_tx_ring(struct age_softc *sc) 2144 { 2145 struct age_ring_data *rd; 2146 struct age_txdesc *txd; 2147 int i; 2148 2149 sc->age_cdata.age_tx_prod = 0; 2150 sc->age_cdata.age_tx_cons = 0; 2151 sc->age_cdata.age_tx_cnt = 0; 2152 2153 rd = &sc->age_rdata; 2154 memset(rd->age_tx_ring, 0, AGE_TX_RING_SZ); 2155 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2156 txd = &sc->age_cdata.age_txdesc[i]; 2157 txd->tx_desc = &rd->age_tx_ring[i]; 2158 txd->tx_m = NULL; 2159 } 2160 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 2161 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2162 } 2163 2164 static int 2165 age_init_rx_ring(struct age_softc *sc) 2166 { 2167 struct age_ring_data *rd; 2168 struct age_rxdesc *rxd; 2169 int i; 2170 2171 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 2172 rd = &sc->age_rdata; 2173 memset(rd->age_rx_ring, 0, AGE_RX_RING_SZ); 2174 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2175 rxd = &sc->age_cdata.age_rxdesc[i]; 2176 rxd->rx_m = NULL; 2177 rxd->rx_desc = &rd->age_rx_ring[i]; 2178 if (age_newbuf(sc, rxd, 1) != 0) 2179 return ENOBUFS; 2180 } 2181 2182 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 0, 2183 sc->age_cdata.age_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2184 2185 return 0; 2186 } 2187 2188 static void 2189 age_init_rr_ring(struct age_softc *sc) 2190 { 2191 struct age_ring_data *rd; 2192 2193 sc->age_cdata.age_rr_cons = 0; 2194 AGE_RXCHAIN_RESET(sc); 2195 2196 rd = &sc->age_rdata; 2197 memset(rd->age_rr_ring, 0, AGE_RR_RING_SZ); 2198 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 2199 sc->age_cdata.age_rr_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2200 } 2201 2202 static void 2203 age_init_cmb_block(struct age_softc *sc) 2204 { 2205 struct age_ring_data *rd; 2206 2207 rd = &sc->age_rdata; 2208 memset(rd->age_cmb_block, 0, AGE_CMB_BLOCK_SZ); 2209 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 2210 sc->age_cdata.age_cmb_block_map->dm_mapsize, 2211 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2212 } 2213 2214 static void 2215 age_init_smb_block(struct age_softc *sc) 2216 { 2217 struct age_ring_data *rd; 2218 2219 rd = &sc->age_rdata; 2220 memset(rd->age_smb_block, 0, AGE_SMB_BLOCK_SZ); 2221 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2222 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2223 } 2224 2225 static int 2226 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd, int init) 2227 { 2228 struct rx_desc *desc; 2229 struct mbuf *m; 2230 bus_dmamap_t map; 2231 int error; 2232 2233 MGETHDR(m, M_DONTWAIT, MT_DATA); 2234 if (m == NULL) 2235 return ENOBUFS; 2236 MCLGET(m, M_DONTWAIT); 2237 if (!(m->m_flags & M_EXT)) { 2238 m_freem(m); 2239 return ENOBUFS; 2240 } 2241 2242 m->m_len = m->m_pkthdr.len = MCLBYTES; 2243 m_adj(m, ETHER_ALIGN); 2244 2245 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2246 sc->age_cdata.age_rx_sparemap, m, BUS_DMA_NOWAIT); 2247 2248 if (error != 0) { 2249 m_freem(m); 2250 2251 if (init) 2252 printf("%s: can't load RX mbuf\n", device_xname(sc->sc_dev)); 2253 return error; 2254 } 2255 2256 if (rxd->rx_m != NULL) { 2257 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2258 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2259 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2260 } 2261 map = rxd->rx_dmamap; 2262 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 2263 sc->age_cdata.age_rx_sparemap = map; 2264 rxd->rx_m = m; 2265 2266 desc = rxd->rx_desc; 2267 desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 2268 desc->len = 2269 htole32((rxd->rx_dmamap->dm_segs[0].ds_len & AGE_RD_LEN_MASK) << 2270 AGE_RD_LEN_SHIFT); 2271 2272 return 0; 2273 } 2274 2275 static void 2276 age_rxvlan(struct age_softc *sc) 2277 { 2278 uint32_t reg; 2279 2280 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2281 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2282 if (sc->sc_ec.ec_capenable & ETHERCAP_VLAN_HWTAGGING) 2283 reg |= MAC_CFG_VLAN_TAG_STRIP; 2284 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2285 } 2286 2287 static void 2288 age_rxfilter(struct age_softc *sc) 2289 { 2290 struct ethercom *ec = &sc->sc_ec; 2291 struct ifnet *ifp = &sc->sc_ec.ec_if; 2292 struct ether_multi *enm; 2293 struct ether_multistep step; 2294 uint32_t crc; 2295 uint32_t mchash[2]; 2296 uint32_t rxcfg; 2297 2298 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 2299 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2300 ifp->if_flags &= ~IFF_ALLMULTI; 2301 2302 /* 2303 * Always accept broadcast frames. 2304 */ 2305 rxcfg |= MAC_CFG_BCAST; 2306 2307 /* Program new filter. */ 2308 if ((ifp->if_flags & IFF_PROMISC) != 0) 2309 goto update; 2310 2311 memset(mchash, 0, sizeof(mchash)); 2312 2313 ETHER_LOCK(ec); 2314 ETHER_FIRST_MULTI(step, ec, enm); 2315 while (enm != NULL) { 2316 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2317 /* XXX Use ETHER_F_ALLMULTI in future. */ 2318 ifp->if_flags |= IFF_ALLMULTI; 2319 ETHER_UNLOCK(ec); 2320 goto update; 2321 } 2322 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2323 mchash[crc >> 31] |= 1U << ((crc >> 26) & 0x1f); 2324 ETHER_NEXT_MULTI(step, enm); 2325 } 2326 ETHER_UNLOCK(ec); 2327 2328 update: 2329 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2330 if (ifp->if_flags & IFF_PROMISC) { 2331 rxcfg |= MAC_CFG_PROMISC; 2332 /* XXX Use ETHER_F_ALLMULTI in future. */ 2333 ifp->if_flags |= IFF_ALLMULTI; 2334 } else 2335 rxcfg |= MAC_CFG_ALLMULTI; 2336 mchash[0] = mchash[1] = 0xFFFFFFFF; 2337 } 2338 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 2339 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 2340 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 2341 } 2342
Indexes created Mon Sep 29 21:09:56 GMT 2025