if_age.c revision 1.8.2.3
1 /* $NetBSD: if_age.c,v 1.8.2.3 2009/03/03 18:31:07 skrll Exp $ */ 2 /* $OpenBSD: if_age.c,v 1.1 2009/01/16 05:00:34 kevlo Exp $ */ 3 4 /*- 5 * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: if_age.c,v 1.8.2.3 2009/03/03 18:31:07 skrll Exp $"); 35 36 #include "bpfilter.h" 37 #include "vlan.h" 38 39 #include <sys/param.h> 40 #include <sys/proc.h> 41 #include <sys/endian.h> 42 #include <sys/systm.h> 43 #include <sys/types.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/queue.h> 47 #include <sys/kernel.h> 48 #include <sys/device.h> 49 #include <sys/callout.h> 50 #include <sys/socket.h> 51 52 #include <net/if.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #ifdef INET 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/in_var.h> 61 #include <netinet/ip.h> 62 #endif 63 64 #include <net/if_types.h> 65 #include <net/if_vlanvar.h> 66 67 #if NBPFILTER > 0 68 #include <net/bpf.h> 69 #endif 70 71 #include <sys/rnd.h> 72 73 #include <dev/mii/mii.h> 74 #include <dev/mii/miivar.h> 75 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/pcidevs.h> 79 80 #include <dev/pci/if_agereg.h> 81 82 static int age_match(device_t, cfdata_t, void *); 83 static void age_attach(device_t, device_t, void *); 84 static int age_detach(device_t, int); 85 86 static bool age_resume(device_t PMF_FN_PROTO); 87 88 static int age_miibus_readreg(device_t, int, int); 89 static void age_miibus_writereg(device_t, int, int, int); 90 static void age_miibus_statchg(device_t); 91 92 static int age_init(struct ifnet *); 93 static int age_ioctl(struct ifnet *, u_long, void *); 94 static void age_start(struct ifnet *); 95 static void age_watchdog(struct ifnet *); 96 static void age_mediastatus(struct ifnet *, struct ifmediareq *); 97 static int age_mediachange(struct ifnet *); 98 99 static int age_intr(void *); 100 static int age_read_vpd_word(struct age_softc *, uint32_t, uint32_t, uint32_t *); 101 static int age_dma_alloc(struct age_softc *); 102 static void age_dma_free(struct age_softc *); 103 static void age_get_macaddr(struct age_softc *, uint8_t[]); 104 static void age_phy_reset(struct age_softc *); 105 106 static int age_encap(struct age_softc *, struct mbuf **); 107 static void age_init_tx_ring(struct age_softc *); 108 static int age_init_rx_ring(struct age_softc *); 109 static void age_init_rr_ring(struct age_softc *); 110 static void age_init_cmb_block(struct age_softc *); 111 static void age_init_smb_block(struct age_softc *); 112 static int age_newbuf(struct age_softc *, struct age_rxdesc *, int); 113 static void age_mac_config(struct age_softc *); 114 static void age_txintr(struct age_softc *, int); 115 static void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 116 static void age_rxintr(struct age_softc *, int); 117 static void age_tick(void *); 118 static void age_reset(struct age_softc *); 119 static void age_stop(struct ifnet *, int); 120 static void age_stats_update(struct age_softc *); 121 static void age_stop_txmac(struct age_softc *); 122 static void age_stop_rxmac(struct age_softc *); 123 static void age_rxvlan(struct age_softc *sc); 124 static void age_rxfilter(struct age_softc *); 125 126 CFATTACH_DECL_NEW(age, sizeof(struct age_softc), 127 age_match, age_attach, age_detach, NULL); 128 129 int agedebug = 0; 130 #define DPRINTF(x) do { if (agedebug) printf x; } while (0) 131 132 #define ETHER_ALIGN 2 133 #define AGE_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 134 135 static int 136 age_match(device_t dev, cfdata_t match, void *aux) 137 { 138 struct pci_attach_args *pa = aux; 139 140 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && 141 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_GIGA); 142 } 143 144 static void 145 age_attach(device_t parent, device_t self, void *aux) 146 { 147 struct age_softc *sc = device_private(self); 148 struct pci_attach_args *pa = aux; 149 pci_intr_handle_t ih; 150 const char *intrstr; 151 struct ifnet *ifp = &sc->sc_ec.ec_if; 152 pcireg_t memtype; 153 int error = 0; 154 155 aprint_naive("\n"); 156 aprint_normal(": Attansic/Atheros L1 Gigabit Ethernet\n"); 157 158 sc->sc_dev = self; 159 sc->sc_dmat = pa->pa_dmat; 160 sc->sc_pct = pa->pa_pc; 161 sc->sc_pcitag = pa->pa_tag; 162 163 /* 164 * Allocate IO memory 165 */ 166 memtype = pci_mapreg_type(sc->sc_pct, sc->sc_pcitag, AGE_PCIR_BAR); 167 switch (memtype) { 168 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 169 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 170 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 171 break; 172 default: 173 aprint_error_dev(self, "invalid base address register\n"); 174 break; 175 } 176 177 if (pci_mapreg_map(pa, AGE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 178 &sc->sc_mem_bh, NULL, &sc->sc_mem_size) != 0) { 179 aprint_error_dev(self, "could not map mem space\n"); 180 return; 181 } 182 183 if (pci_intr_map(pa, &ih) != 0) { 184 aprint_error_dev(self, "could not map interrupt\n"); 185 goto fail; 186 } 187 188 /* 189 * Allocate IRQ 190 */ 191 intrstr = pci_intr_string(sc->sc_pct, ih); 192 sc->sc_irq_handle = pci_intr_establish(sc->sc_pct, ih, IPL_NET, 193 age_intr, sc); 194 if (sc->sc_irq_handle == NULL) { 195 aprint_error_dev(self, "could not establish interrupt"); 196 if (intrstr != NULL) 197 aprint_error(" at %s", intrstr); 198 aprint_error("\n"); 199 goto fail; 200 } 201 aprint_normal_dev(self, "%s\n", intrstr); 202 203 /* Set PHY address. */ 204 sc->age_phyaddr = AGE_PHY_ADDR; 205 206 /* Reset PHY. */ 207 age_phy_reset(sc); 208 209 /* Reset the ethernet controller. */ 210 age_reset(sc); 211 212 /* Get PCI and chip id/revision. */ 213 sc->age_rev = PCI_REVISION(pa->pa_class); 214 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 215 MASTER_CHIP_REV_SHIFT; 216 217 aprint_debug_dev(self, "PCI device revision : 0x%04x\n", sc->age_rev); 218 aprint_debug_dev(self, "Chip id/revision : 0x%04x\n", sc->age_chip_rev); 219 220 if (agedebug) { 221 aprint_debug_dev(self, "%d Tx FIFO, %d Rx FIFO\n", 222 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 223 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 224 } 225 226 /* Set max allowable DMA size. */ 227 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 228 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 229 230 /* Allocate DMA stuffs */ 231 error = age_dma_alloc(sc); 232 if (error) 233 goto fail; 234 235 callout_init(&sc->sc_tick_ch, 0); 236 callout_setfunc(&sc->sc_tick_ch, age_tick, sc); 237 238 /* Load station address. */ 239 age_get_macaddr(sc, sc->sc_enaddr); 240 241 aprint_normal_dev(self, "Ethernet address %s\n", 242 ether_sprintf(sc->sc_enaddr)); 243 244 ifp->if_softc = sc; 245 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 246 ifp->if_init = age_init; 247 ifp->if_ioctl = age_ioctl; 248 ifp->if_start = age_start; 249 ifp->if_stop = age_stop; 250 ifp->if_watchdog = age_watchdog; 251 ifp->if_baudrate = IF_Gbps(1); 252 IFQ_SET_MAXLEN(&ifp->if_snd, AGE_TX_RING_CNT - 1); 253 IFQ_SET_READY(&ifp->if_snd); 254 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 255 256 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 257 258 #ifdef AGE_CHECKSUM 259 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 260 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 261 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 262 #endif 263 264 #if NVLAN > 0 265 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 266 #endif 267 268 /* Set up MII bus. */ 269 sc->sc_miibus.mii_ifp = ifp; 270 sc->sc_miibus.mii_readreg = age_miibus_readreg; 271 sc->sc_miibus.mii_writereg = age_miibus_writereg; 272 sc->sc_miibus.mii_statchg = age_miibus_statchg; 273 274 sc->sc_ec.ec_mii = &sc->sc_miibus; 275 ifmedia_init(&sc->sc_miibus.mii_media, 0, age_mediachange, 276 age_mediastatus); 277 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 278 MII_OFFSET_ANY, 0); 279 280 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 281 aprint_error_dev(self, "no PHY found!\n"); 282 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 283 0, NULL); 284 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 285 } else 286 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 287 288 if_attach(ifp); 289 ether_ifattach(ifp, sc->sc_enaddr); 290 291 if (!pmf_device_register(self, NULL, age_resume)) 292 aprint_error_dev(self, "couldn't establish power handler\n"); 293 else 294 pmf_class_network_register(self, ifp); 295 296 return; 297 298 fail: 299 age_dma_free(sc); 300 if (sc->sc_irq_handle != NULL) { 301 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 302 sc->sc_irq_handle = NULL; 303 } 304 if (sc->sc_mem_size) { 305 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 306 sc->sc_mem_size = 0; 307 } 308 } 309 310 static int 311 age_detach(device_t self, int flags) 312 { 313 struct age_softc *sc = device_private(self); 314 struct ifnet *ifp = &sc->sc_ec.ec_if; 315 int s; 316 317 s = splnet(); 318 age_stop(ifp, 0); 319 splx(s); 320 321 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 322 323 /* Delete all remaining media. */ 324 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 325 326 ether_ifdetach(ifp); 327 if_detach(ifp); 328 age_dma_free(sc); 329 330 if (sc->sc_irq_handle != NULL) { 331 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 332 sc->sc_irq_handle = NULL; 333 } 334 335 return 0; 336 } 337 338 /* 339 * Read a PHY register on the MII of the L1. 340 */ 341 static int 342 age_miibus_readreg(device_t dev, int phy, int reg) 343 { 344 struct age_softc *sc = device_private(dev); 345 uint32_t v; 346 int i; 347 348 if (phy != sc->age_phyaddr) 349 return 0; 350 351 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 352 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 353 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 354 DELAY(1); 355 v = CSR_READ_4(sc, AGE_MDIO); 356 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 357 break; 358 } 359 360 if (i == 0) { 361 printf("%s: phy read timeout: phy %d, reg %d\n", 362 device_xname(sc->sc_dev), phy, reg); 363 return 0; 364 } 365 366 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 367 } 368 369 /* 370 * Write a PHY register on the MII of the L1. 371 */ 372 static void 373 age_miibus_writereg(device_t dev, int phy, int reg, int val) 374 { 375 struct age_softc *sc = device_private(dev); 376 uint32_t v; 377 int i; 378 379 if (phy != sc->age_phyaddr) 380 return; 381 382 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 383 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 384 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 385 386 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 387 DELAY(1); 388 v = CSR_READ_4(sc, AGE_MDIO); 389 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 390 break; 391 } 392 393 if (i == 0) { 394 printf("%s: phy write timeout: phy %d, reg %d\n", 395 device_xname(sc->sc_dev), phy, reg); 396 } 397 } 398 399 /* 400 * Callback from MII layer when media changes. 401 */ 402 static void 403 age_miibus_statchg(device_t dev) 404 { 405 struct age_softc *sc = device_private(dev); 406 struct ifnet *ifp = &sc->sc_ec.ec_if; 407 struct mii_data *mii; 408 409 if ((ifp->if_flags & IFF_RUNNING) == 0) 410 return; 411 412 mii = &sc->sc_miibus; 413 414 sc->age_flags &= ~AGE_FLAG_LINK; 415 if ((mii->mii_media_status & IFM_AVALID) != 0) { 416 switch (IFM_SUBTYPE(mii->mii_media_active)) { 417 case IFM_10_T: 418 case IFM_100_TX: 419 case IFM_1000_T: 420 sc->age_flags |= AGE_FLAG_LINK; 421 break; 422 default: 423 break; 424 } 425 } 426 427 /* Stop Rx/Tx MACs. */ 428 age_stop_rxmac(sc); 429 age_stop_txmac(sc); 430 431 /* Program MACs with resolved speed/duplex/flow-control. */ 432 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 433 uint32_t reg; 434 435 age_mac_config(sc); 436 reg = CSR_READ_4(sc, AGE_MAC_CFG); 437 /* Restart DMA engine and Tx/Rx MAC. */ 438 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 439 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 440 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 441 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 442 } 443 } 444 445 /* 446 * Get the current interface media status. 447 */ 448 static void 449 age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 450 { 451 struct age_softc *sc = ifp->if_softc; 452 struct mii_data *mii = &sc->sc_miibus; 453 454 mii_pollstat(mii); 455 ifmr->ifm_status = mii->mii_media_status; 456 ifmr->ifm_active = mii->mii_media_active; 457 } 458 459 /* 460 * Set hardware to newly-selected media. 461 */ 462 static int 463 age_mediachange(struct ifnet *ifp) 464 { 465 struct age_softc *sc = ifp->if_softc; 466 struct mii_data *mii = &sc->sc_miibus; 467 int error; 468 469 if (mii->mii_instance != 0) { 470 struct mii_softc *miisc; 471 472 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 473 mii_phy_reset(miisc); 474 } 475 error = mii_mediachg(mii); 476 477 return error; 478 } 479 480 static int 481 age_intr(void *arg) 482 { 483 struct age_softc *sc = arg; 484 struct ifnet *ifp = &sc->sc_ec.ec_if; 485 struct cmb *cmb; 486 uint32_t status; 487 488 status = CSR_READ_4(sc, AGE_INTR_STATUS); 489 if (status == 0 || (status & AGE_INTRS) == 0) 490 return 0; 491 492 cmb = sc->age_rdata.age_cmb_block; 493 if (cmb == NULL) 494 return 0; 495 496 /* Disable interrupts. */ 497 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 498 499 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 500 sc->age_cdata.age_cmb_block_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 501 status = le32toh(cmb->intr_status); 502 if ((status & AGE_INTRS) == 0) 503 goto back; 504 505 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 506 TPD_CONS_SHIFT; 507 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 508 RRD_PROD_SHIFT; 509 510 /* Let hardware know CMB was served. */ 511 cmb->intr_status = 0; 512 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 513 sc->age_cdata.age_cmb_block_map->dm_mapsize, 514 BUS_DMASYNC_PREWRITE); 515 516 if (ifp->if_flags & IFF_RUNNING) { 517 if (status & INTR_CMB_RX) 518 age_rxintr(sc, sc->age_rr_prod); 519 520 if (status & INTR_CMB_TX) 521 age_txintr(sc, sc->age_tpd_cons); 522 523 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 524 if (status & INTR_DMA_RD_TO_RST) 525 printf("%s: DMA read error! -- resetting\n", 526 device_xname(sc->sc_dev)); 527 if (status & INTR_DMA_WR_TO_RST) 528 printf("%s: DMA write error! -- resetting\n", 529 device_xname(sc->sc_dev)); 530 age_init(ifp); 531 } 532 533 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 534 age_start(ifp); 535 536 if (status & INTR_SMB) 537 age_stats_update(sc); 538 } 539 540 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 541 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 542 sc->age_cdata.age_cmb_block_map->dm_mapsize, 543 BUS_DMASYNC_POSTREAD); 544 545 back: 546 /* Re-enable interrupts. */ 547 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 548 549 return 1; 550 } 551 552 static int 553 age_read_vpd_word(struct age_softc *sc, uint32_t vpdc, uint32_t offset, 554 uint32_t *word) 555 { 556 int i; 557 pcireg_t rv; 558 559 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_VPD_ADDRESS(vpdc), 560 offset << PCI_VPD_ADDRESS_SHIFT); 561 for (i = AGE_TIMEOUT; i > 0; i--) { 562 DELAY(10); 563 rv = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 564 PCI_VPD_ADDRESS(vpdc)); 565 if ((rv & PCI_VPD_OPFLAG) == PCI_VPD_OPFLAG) 566 break; 567 } 568 if (i == 0) { 569 printf("%s: VPD read timeout!\n", device_xname(sc->sc_dev)); 570 *word = 0; 571 return ETIMEDOUT; 572 } 573 574 *word = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_VPD_DATAREG(vpdc)); 575 return 0; 576 } 577 578 static void 579 age_get_macaddr(struct age_softc *sc, uint8_t eaddr[]) 580 { 581 uint32_t ea[2], off, reg, word; 582 int vpd_error, match, vpdc; 583 584 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 585 if ((reg & SPI_VPD_ENB) != 0) { 586 /* Get VPD stored in TWSI EEPROM. */ 587 reg &= ~SPI_VPD_ENB; 588 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 589 } 590 591 vpd_error = 0; 592 ea[0] = ea[1] = 0; 593 if ((vpd_error = pci_get_capability(sc->sc_pct, sc->sc_pcitag, 594 PCI_CAP_VPD, &vpdc, NULL))) { 595 /* 596 * PCI VPD capability exists, but it seems that it's 597 * not in the standard form as stated in PCI VPD 598 * specification such that driver could not use 599 * pci_get_vpd_readonly(9) with keyword 'NA'. 600 * Search VPD data starting at address 0x0100. The data 601 * should be used as initializers to set AGE_PAR0, 602 * AGE_PAR1 register including other PCI configuration 603 * registers. 604 */ 605 word = 0; 606 match = 0; 607 reg = 0; 608 for (off = AGE_VPD_REG_CONF_START; off < AGE_VPD_REG_CONF_END; 609 off += sizeof(uint32_t)) { 610 vpd_error = age_read_vpd_word(sc, vpdc, off, &word); 611 if (vpd_error != 0) 612 break; 613 if (match != 0) { 614 switch (reg) { 615 case AGE_PAR0: 616 ea[0] = word; 617 break; 618 case AGE_PAR1: 619 ea[1] = word; 620 break; 621 default: 622 break; 623 } 624 match = 0; 625 } else if ((word & 0xFF) == AGE_VPD_REG_CONF_SIG) { 626 match = 1; 627 reg = word >> 16; 628 } else 629 break; 630 } 631 if (off >= AGE_VPD_REG_CONF_END) 632 vpd_error = ENOENT; 633 if (vpd_error == 0) { 634 /* 635 * Don't blindly trust ethernet address obtained 636 * from VPD. Check whether ethernet address is 637 * valid one. Otherwise fall-back to reading 638 * PAR register. 639 */ 640 ea[1] &= 0xFFFF; 641 if ((ea[0] == 0 && ea[1] == 0) || 642 (ea[0] == 0xFFFFFFFF && ea[1] == 0xFFFF)) { 643 if (agedebug) 644 printf("%s: invalid ethernet address " 645 "returned from VPD.\n", 646 device_xname(sc->sc_dev)); 647 vpd_error = EINVAL; 648 } 649 } 650 if (vpd_error != 0 && (agedebug)) 651 printf("%s: VPD access failure!\n", 652 device_xname(sc->sc_dev)); 653 } else { 654 if (agedebug) 655 printf("%s: PCI VPD capability not found!\n", 656 device_xname(sc->sc_dev)); 657 } 658 659 /* 660 * It seems that L1 also provides a way to extract ethernet 661 * address via SPI flash interface. Because SPI flash memory 662 * device of different vendors vary in their instruction 663 * codes for read ID instruction, it's very hard to get 664 * instructions codes without detailed information for the 665 * flash memory device used on ethernet controller. To simplify 666 * code, just read AGE_PAR0/AGE_PAR1 register to get ethernet 667 * address which is supposed to be set by hardware during 668 * power on reset. 669 */ 670 if (vpd_error != 0) { 671 /* 672 * VPD is mapped to SPI flash memory or BIOS set it. 673 */ 674 ea[0] = CSR_READ_4(sc, AGE_PAR0); 675 ea[1] = CSR_READ_4(sc, AGE_PAR1); 676 } 677 678 ea[1] &= 0xFFFF; 679 eaddr[0] = (ea[1] >> 8) & 0xFF; 680 eaddr[1] = (ea[1] >> 0) & 0xFF; 681 eaddr[2] = (ea[0] >> 24) & 0xFF; 682 eaddr[3] = (ea[0] >> 16) & 0xFF; 683 eaddr[4] = (ea[0] >> 8) & 0xFF; 684 eaddr[5] = (ea[0] >> 0) & 0xFF; 685 } 686 687 static void 688 age_phy_reset(struct age_softc *sc) 689 { 690 /* Reset PHY. */ 691 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 692 DELAY(1000); 693 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 694 DELAY(1000); 695 } 696 697 static int 698 age_dma_alloc(struct age_softc *sc) 699 { 700 struct age_txdesc *txd; 701 struct age_rxdesc *rxd; 702 int nsegs, error, i; 703 704 /* 705 * Create DMA stuffs for TX ring 706 */ 707 error = bus_dmamap_create(sc->sc_dmat, AGE_TX_RING_SZ, 1, 708 AGE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_tx_ring_map); 709 if (error) 710 return ENOBUFS; 711 712 /* Allocate DMA'able memory for TX ring */ 713 error = bus_dmamem_alloc(sc->sc_dmat, AGE_TX_RING_SZ, 714 ETHER_ALIGN, 0, &sc->age_rdata.age_tx_ring_seg, 1, 715 &nsegs, BUS_DMA_WAITOK); 716 if (error) { 717 printf("%s: could not allocate DMA'able memory for Tx ring, " 718 "error = %i\n", device_xname(sc->sc_dev), error); 719 return error; 720 } 721 722 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_tx_ring_seg, 723 nsegs, AGE_TX_RING_SZ, (void **)&sc->age_rdata.age_tx_ring, 724 BUS_DMA_NOWAIT); 725 if (error) 726 return ENOBUFS; 727 728 memset(sc->age_rdata.age_tx_ring, 0, AGE_TX_RING_SZ); 729 730 /* Load the DMA map for Tx ring. */ 731 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 732 sc->age_rdata.age_tx_ring, AGE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 733 if (error) { 734 printf("%s: could not load DMA'able memory for Tx ring, " 735 "error = %i\n", device_xname(sc->sc_dev), error); 736 bus_dmamem_free(sc->sc_dmat, 737 (bus_dma_segment_t *)&sc->age_rdata.age_tx_ring, 1); 738 return error; 739 } 740 741 sc->age_rdata.age_tx_ring_paddr = 742 sc->age_cdata.age_tx_ring_map->dm_segs[0].ds_addr; 743 744 /* 745 * Create DMA stuffs for RX ring 746 */ 747 error = bus_dmamap_create(sc->sc_dmat, AGE_RX_RING_SZ, 1, 748 AGE_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_ring_map); 749 if (error) 750 return ENOBUFS; 751 752 /* Allocate DMA'able memory for RX ring */ 753 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RX_RING_SZ, 754 ETHER_ALIGN, 0, &sc->age_rdata.age_rx_ring_seg, 1, 755 &nsegs, BUS_DMA_WAITOK); 756 if (error) { 757 printf("%s: could not allocate DMA'able memory for Rx ring, " 758 "error = %i.\n", device_xname(sc->sc_dev), error); 759 return error; 760 } 761 762 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rx_ring_seg, 763 nsegs, AGE_RX_RING_SZ, (void **)&sc->age_rdata.age_rx_ring, 764 BUS_DMA_NOWAIT); 765 if (error) 766 return ENOBUFS; 767 768 memset(sc->age_rdata.age_rx_ring, 0, AGE_RX_RING_SZ); 769 770 /* Load the DMA map for Rx ring. */ 771 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 772 sc->age_rdata.age_rx_ring, AGE_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 773 if (error) { 774 printf("%s: could not load DMA'able memory for Rx ring, " 775 "error = %i.\n", device_xname(sc->sc_dev), error); 776 bus_dmamem_free(sc->sc_dmat, 777 (bus_dma_segment_t *)sc->age_rdata.age_rx_ring, 1); 778 return error; 779 } 780 781 sc->age_rdata.age_rx_ring_paddr = 782 sc->age_cdata.age_rx_ring_map->dm_segs[0].ds_addr; 783 784 /* 785 * Create DMA stuffs for RX return ring 786 */ 787 error = bus_dmamap_create(sc->sc_dmat, AGE_RR_RING_SZ, 1, 788 AGE_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rr_ring_map); 789 if (error) 790 return ENOBUFS; 791 792 /* Allocate DMA'able memory for RX return ring */ 793 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RR_RING_SZ, 794 ETHER_ALIGN, 0, &sc->age_rdata.age_rr_ring_seg, 1, 795 &nsegs, BUS_DMA_WAITOK); 796 if (error) { 797 printf("%s: could not allocate DMA'able memory for Rx " 798 "return ring, error = %i.\n", 799 device_xname(sc->sc_dev), error); 800 return error; 801 } 802 803 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rr_ring_seg, 804 nsegs, AGE_RR_RING_SZ, (void **)&sc->age_rdata.age_rr_ring, 805 BUS_DMA_NOWAIT); 806 if (error) 807 return ENOBUFS; 808 809 memset(sc->age_rdata.age_rr_ring, 0, AGE_RR_RING_SZ); 810 811 /* Load the DMA map for Rx return ring. */ 812 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 813 sc->age_rdata.age_rr_ring, AGE_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 814 if (error) { 815 printf("%s: could not load DMA'able memory for Rx return ring, " 816 "error = %i\n", device_xname(sc->sc_dev), error); 817 bus_dmamem_free(sc->sc_dmat, 818 (bus_dma_segment_t *)&sc->age_rdata.age_rr_ring, 1); 819 return error; 820 } 821 822 sc->age_rdata.age_rr_ring_paddr = 823 sc->age_cdata.age_rr_ring_map->dm_segs[0].ds_addr; 824 825 /* 826 * Create DMA stuffs for CMB block 827 */ 828 error = bus_dmamap_create(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 1, 829 AGE_CMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 830 &sc->age_cdata.age_cmb_block_map); 831 if (error) 832 return ENOBUFS; 833 834 /* Allocate DMA'able memory for CMB block */ 835 error = bus_dmamem_alloc(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 836 ETHER_ALIGN, 0, &sc->age_rdata.age_cmb_block_seg, 1, 837 &nsegs, BUS_DMA_WAITOK); 838 if (error) { 839 printf("%s: could not allocate DMA'able memory for " 840 "CMB block, error = %i\n", device_xname(sc->sc_dev), error); 841 return error; 842 } 843 844 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_cmb_block_seg, 845 nsegs, AGE_CMB_BLOCK_SZ, (void **)&sc->age_rdata.age_cmb_block, 846 BUS_DMA_NOWAIT); 847 if (error) 848 return ENOBUFS; 849 850 memset(sc->age_rdata.age_cmb_block, 0, AGE_CMB_BLOCK_SZ); 851 852 /* Load the DMA map for CMB block. */ 853 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 854 sc->age_rdata.age_cmb_block, AGE_CMB_BLOCK_SZ, NULL, 855 BUS_DMA_WAITOK); 856 if (error) { 857 printf("%s: could not load DMA'able memory for CMB block, " 858 "error = %i\n", device_xname(sc->sc_dev), error); 859 bus_dmamem_free(sc->sc_dmat, 860 (bus_dma_segment_t *)&sc->age_rdata.age_cmb_block, 1); 861 return error; 862 } 863 864 sc->age_rdata.age_cmb_block_paddr = 865 sc->age_cdata.age_cmb_block_map->dm_segs[0].ds_addr; 866 867 /* 868 * Create DMA stuffs for SMB block 869 */ 870 error = bus_dmamap_create(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 1, 871 AGE_SMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 872 &sc->age_cdata.age_smb_block_map); 873 if (error) 874 return ENOBUFS; 875 876 /* Allocate DMA'able memory for SMB block */ 877 error = bus_dmamem_alloc(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 878 ETHER_ALIGN, 0, &sc->age_rdata.age_smb_block_seg, 1, 879 &nsegs, BUS_DMA_WAITOK); 880 if (error) { 881 printf("%s: could not allocate DMA'able memory for " 882 "SMB block, error = %i\n", device_xname(sc->sc_dev), error); 883 return error; 884 } 885 886 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_smb_block_seg, 887 nsegs, AGE_SMB_BLOCK_SZ, (void **)&sc->age_rdata.age_smb_block, 888 BUS_DMA_NOWAIT); 889 if (error) 890 return ENOBUFS; 891 892 memset(sc->age_rdata.age_smb_block, 0, AGE_SMB_BLOCK_SZ); 893 894 /* Load the DMA map for SMB block */ 895 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 896 sc->age_rdata.age_smb_block, AGE_SMB_BLOCK_SZ, NULL, 897 BUS_DMA_WAITOK); 898 if (error) { 899 printf("%s: could not load DMA'able memory for SMB block, " 900 "error = %i\n", device_xname(sc->sc_dev), error); 901 bus_dmamem_free(sc->sc_dmat, 902 (bus_dma_segment_t *)&sc->age_rdata.age_smb_block, 1); 903 return error; 904 } 905 906 sc->age_rdata.age_smb_block_paddr = 907 sc->age_cdata.age_smb_block_map->dm_segs[0].ds_addr; 908 909 /* Create DMA maps for Tx buffers. */ 910 for (i = 0; i < AGE_TX_RING_CNT; i++) { 911 txd = &sc->age_cdata.age_txdesc[i]; 912 txd->tx_m = NULL; 913 txd->tx_dmamap = NULL; 914 error = bus_dmamap_create(sc->sc_dmat, AGE_TSO_MAXSIZE, 915 AGE_MAXTXSEGS, AGE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 916 &txd->tx_dmamap); 917 if (error) { 918 printf("%s: could not create Tx dmamap, error = %i.\n", 919 device_xname(sc->sc_dev), error); 920 return error; 921 } 922 } 923 924 /* Create DMA maps for Rx buffers. */ 925 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 926 BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_sparemap); 927 if (error) { 928 printf("%s: could not create spare Rx dmamap, error = %i.\n", 929 device_xname(sc->sc_dev), error); 930 return error; 931 } 932 for (i = 0; i < AGE_RX_RING_CNT; i++) { 933 rxd = &sc->age_cdata.age_rxdesc[i]; 934 rxd->rx_m = NULL; 935 rxd->rx_dmamap = NULL; 936 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 937 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 938 if (error) { 939 printf("%s: could not create Rx dmamap, error = %i.\n", 940 device_xname(sc->sc_dev), error); 941 return error; 942 } 943 } 944 945 return 0; 946 } 947 948 static void 949 age_dma_free(struct age_softc *sc) 950 { 951 struct age_txdesc *txd; 952 struct age_rxdesc *rxd; 953 int i; 954 955 /* Tx buffers */ 956 for (i = 0; i < AGE_TX_RING_CNT; i++) { 957 txd = &sc->age_cdata.age_txdesc[i]; 958 if (txd->tx_dmamap != NULL) { 959 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 960 txd->tx_dmamap = NULL; 961 } 962 } 963 /* Rx buffers */ 964 for (i = 0; i < AGE_RX_RING_CNT; i++) { 965 rxd = &sc->age_cdata.age_rxdesc[i]; 966 if (rxd->rx_dmamap != NULL) { 967 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 968 rxd->rx_dmamap = NULL; 969 } 970 } 971 if (sc->age_cdata.age_rx_sparemap != NULL) { 972 bus_dmamap_destroy(sc->sc_dmat, sc->age_cdata.age_rx_sparemap); 973 sc->age_cdata.age_rx_sparemap = NULL; 974 } 975 976 /* Tx ring. */ 977 if (sc->age_cdata.age_tx_ring_map != NULL) 978 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_tx_ring_map); 979 if (sc->age_cdata.age_tx_ring_map != NULL && 980 sc->age_rdata.age_tx_ring != NULL) 981 bus_dmamem_free(sc->sc_dmat, 982 (bus_dma_segment_t *)sc->age_rdata.age_tx_ring, 1); 983 sc->age_rdata.age_tx_ring = NULL; 984 sc->age_cdata.age_tx_ring_map = NULL; 985 986 /* Rx ring. */ 987 if (sc->age_cdata.age_rx_ring_map != NULL) 988 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rx_ring_map); 989 if (sc->age_cdata.age_rx_ring_map != NULL && 990 sc->age_rdata.age_rx_ring != NULL) 991 bus_dmamem_free(sc->sc_dmat, 992 (bus_dma_segment_t *)sc->age_rdata.age_rx_ring, 1); 993 sc->age_rdata.age_rx_ring = NULL; 994 sc->age_cdata.age_rx_ring_map = NULL; 995 996 /* Rx return ring. */ 997 if (sc->age_cdata.age_rr_ring_map != NULL) 998 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rr_ring_map); 999 if (sc->age_cdata.age_rr_ring_map != NULL && 1000 sc->age_rdata.age_rr_ring != NULL) 1001 bus_dmamem_free(sc->sc_dmat, 1002 (bus_dma_segment_t *)sc->age_rdata.age_rr_ring, 1); 1003 sc->age_rdata.age_rr_ring = NULL; 1004 sc->age_cdata.age_rr_ring_map = NULL; 1005 1006 /* CMB block */ 1007 if (sc->age_cdata.age_cmb_block_map != NULL) 1008 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_cmb_block_map); 1009 if (sc->age_cdata.age_cmb_block_map != NULL && 1010 sc->age_rdata.age_cmb_block != NULL) 1011 bus_dmamem_free(sc->sc_dmat, 1012 (bus_dma_segment_t *)sc->age_rdata.age_cmb_block, 1); 1013 sc->age_rdata.age_cmb_block = NULL; 1014 sc->age_cdata.age_cmb_block_map = NULL; 1015 1016 /* SMB block */ 1017 if (sc->age_cdata.age_smb_block_map != NULL) 1018 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_smb_block_map); 1019 if (sc->age_cdata.age_smb_block_map != NULL && 1020 sc->age_rdata.age_smb_block != NULL) 1021 bus_dmamem_free(sc->sc_dmat, 1022 (bus_dma_segment_t *)sc->age_rdata.age_smb_block, 1); 1023 sc->age_rdata.age_smb_block = NULL; 1024 sc->age_cdata.age_smb_block_map = NULL; 1025 } 1026 1027 static void 1028 age_start(struct ifnet *ifp) 1029 { 1030 struct age_softc *sc = ifp->if_softc; 1031 struct mbuf *m_head; 1032 int enq; 1033 1034 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1035 return; 1036 1037 enq = 0; 1038 for (;;) { 1039 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1040 if (m_head == NULL) 1041 break; 1042 1043 /* 1044 * Pack the data into the transmit ring. If we 1045 * don't have room, set the OACTIVE flag and wait 1046 * for the NIC to drain the ring. 1047 */ 1048 if (age_encap(sc, &m_head)) { 1049 if (m_head == NULL) 1050 break; 1051 ifp->if_flags |= IFF_OACTIVE; 1052 break; 1053 } 1054 enq = 1; 1055 1056 #if NBPFILTER > 0 1057 /* 1058 * If there's a BPF listener, bounce a copy of this frame 1059 * to him. 1060 */ 1061 if (ifp->if_bpf != NULL) 1062 bpf_mtap(ifp->if_bpf, m_head); 1063 #endif 1064 } 1065 1066 if (enq) { 1067 /* Update mbox. */ 1068 AGE_COMMIT_MBOX(sc); 1069 /* Set a timeout in case the chip goes out to lunch. */ 1070 ifp->if_timer = AGE_TX_TIMEOUT; 1071 } 1072 } 1073 1074 static void 1075 age_watchdog(struct ifnet *ifp) 1076 { 1077 struct age_softc *sc = ifp->if_softc; 1078 1079 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1080 printf("%s: watchdog timeout (missed link)\n", 1081 device_xname(sc->sc_dev)); 1082 ifp->if_oerrors++; 1083 age_init(ifp); 1084 return; 1085 } 1086 1087 if (sc->age_cdata.age_tx_cnt == 0) { 1088 printf("%s: watchdog timeout (missed Tx interrupts) " 1089 "-- recovering\n", device_xname(sc->sc_dev)); 1090 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1091 age_start(ifp); 1092 return; 1093 } 1094 1095 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1096 ifp->if_oerrors++; 1097 age_init(ifp); 1098 1099 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1100 age_start(ifp); 1101 } 1102 1103 static int 1104 age_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1105 { 1106 struct age_softc *sc = ifp->if_softc; 1107 int s, error; 1108 1109 s = splnet(); 1110 1111 error = ether_ioctl(ifp, cmd, data); 1112 if (error == ENETRESET) { 1113 if (ifp->if_flags & IFF_RUNNING) 1114 age_rxfilter(sc); 1115 error = 0; 1116 } 1117 1118 splx(s); 1119 return error; 1120 } 1121 1122 static void 1123 age_mac_config(struct age_softc *sc) 1124 { 1125 struct mii_data *mii; 1126 uint32_t reg; 1127 1128 mii = &sc->sc_miibus; 1129 1130 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1131 reg &= ~MAC_CFG_FULL_DUPLEX; 1132 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1133 reg &= ~MAC_CFG_SPEED_MASK; 1134 1135 /* Reprogram MAC with resolved speed/duplex. */ 1136 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1137 case IFM_10_T: 1138 case IFM_100_TX: 1139 reg |= MAC_CFG_SPEED_10_100; 1140 break; 1141 case IFM_1000_T: 1142 reg |= MAC_CFG_SPEED_1000; 1143 break; 1144 } 1145 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1146 reg |= MAC_CFG_FULL_DUPLEX; 1147 #ifdef notyet 1148 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1149 reg |= MAC_CFG_TX_FC; 1150 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1151 reg |= MAC_CFG_RX_FC; 1152 #endif 1153 } 1154 1155 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1156 } 1157 1158 static bool 1159 age_resume(device_t dv PMF_FN_ARGS) 1160 { 1161 struct age_softc *sc = device_private(dv); 1162 uint16_t cmd; 1163 1164 /* 1165 * Clear INTx emulation disable for hardware that 1166 * is set in resume event. From Linux. 1167 */ 1168 cmd = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 1169 if ((cmd & PCI_COMMAND_INTERRUPT_DISABLE) != 0) { 1170 cmd &= ~PCI_COMMAND_INTERRUPT_DISABLE; 1171 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 1172 PCI_COMMAND_STATUS_REG, cmd); 1173 } 1174 1175 return true; 1176 } 1177 1178 static int 1179 age_encap(struct age_softc *sc, struct mbuf **m_head) 1180 { 1181 struct age_txdesc *txd, *txd_last; 1182 struct tx_desc *desc; 1183 struct mbuf *m; 1184 bus_dmamap_t map; 1185 uint32_t cflags, poff, vtag; 1186 int error, i, nsegs, prod; 1187 #if NVLAN > 0 1188 struct m_tag *mtag; 1189 #endif 1190 1191 m = *m_head; 1192 cflags = vtag = 0; 1193 poff = 0; 1194 1195 prod = sc->age_cdata.age_tx_prod; 1196 txd = &sc->age_cdata.age_txdesc[prod]; 1197 txd_last = txd; 1198 map = txd->tx_dmamap; 1199 1200 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1201 1202 if (error == EFBIG) { 1203 error = 0; 1204 1205 MGETHDR(m, M_DONTWAIT, MT_DATA); 1206 if (m == NULL) { 1207 printf("%s: can't defrag TX mbuf\n", 1208 device_xname(sc->sc_dev)); 1209 m_freem(*m_head); 1210 *m_head = NULL; 1211 return ENOBUFS; 1212 } 1213 1214 M_COPY_PKTHDR(m, *m_head); 1215 if ((*m_head)->m_pkthdr.len > MHLEN) { 1216 MCLGET(m, M_DONTWAIT); 1217 if (!(m->m_flags & M_EXT)) { 1218 m_freem(*m_head); 1219 m_freem(m); 1220 *m_head = NULL; 1221 return ENOBUFS; 1222 } 1223 } 1224 m_copydata(*m_head, 0, (*m_head)->m_pkthdr.len, 1225 mtod(m, void *)); 1226 m_freem(*m_head); 1227 m->m_len = m->m_pkthdr.len; 1228 *m_head = m; 1229 1230 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1231 BUS_DMA_NOWAIT); 1232 1233 if (error != 0) { 1234 printf("%s: could not load defragged TX mbuf\n", 1235 device_xname(sc->sc_dev)); 1236 if (!error) { 1237 bus_dmamap_unload(sc->sc_dmat, map); 1238 error = EFBIG; 1239 } 1240 m_freem(*m_head); 1241 *m_head = NULL; 1242 return error; 1243 } 1244 } else if (error) { 1245 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 1246 return error; 1247 } 1248 1249 nsegs = map->dm_nsegs; 1250 1251 if (nsegs == 0) { 1252 m_freem(*m_head); 1253 *m_head = NULL; 1254 return EIO; 1255 } 1256 1257 /* Check descriptor overrun. */ 1258 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1259 bus_dmamap_unload(sc->sc_dmat, map); 1260 return ENOBUFS; 1261 } 1262 1263 m = *m_head; 1264 /* Configure Tx IP/TCP/UDP checksum offload. */ 1265 if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1266 cflags |= AGE_TD_CSUM; 1267 if ((m->m_pkthdr.csum_flags & M_CSUM_TCPv4) != 0) 1268 cflags |= AGE_TD_TCPCSUM; 1269 if ((m->m_pkthdr.csum_flags & M_CSUM_UDPv4) != 0) 1270 cflags |= AGE_TD_UDPCSUM; 1271 /* Set checksum start offset. */ 1272 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1273 } 1274 1275 #if NVLAN > 0 1276 /* Configure VLAN hardware tag insertion. */ 1277 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m))) { 1278 vtag = AGE_TX_VLAN_TAG(htons(VLAN_TAG_VALUE(mtag))); 1279 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1280 cflags |= AGE_TD_INSERT_VLAN_TAG; 1281 } 1282 #endif 1283 1284 desc = NULL; 1285 for (i = 0; i < nsegs; i++) { 1286 desc = &sc->age_rdata.age_tx_ring[prod]; 1287 desc->addr = htole64(map->dm_segs[i].ds_addr); 1288 desc->len = 1289 htole32(AGE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 1290 desc->flags = htole32(cflags); 1291 sc->age_cdata.age_tx_cnt++; 1292 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1293 } 1294 1295 /* Update producer index. */ 1296 sc->age_cdata.age_tx_prod = prod; 1297 1298 /* Set EOP on the last descriptor. */ 1299 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1300 desc = &sc->age_rdata.age_tx_ring[prod]; 1301 desc->flags |= htole32(AGE_TD_EOP); 1302 1303 /* Swap dmamap of the first and the last. */ 1304 txd = &sc->age_cdata.age_txdesc[prod]; 1305 map = txd_last->tx_dmamap; 1306 txd_last->tx_dmamap = txd->tx_dmamap; 1307 txd->tx_dmamap = map; 1308 txd->tx_m = m; 1309 1310 /* Sync descriptors. */ 1311 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1312 BUS_DMASYNC_PREWRITE); 1313 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1314 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1315 1316 return 0; 1317 } 1318 1319 static void 1320 age_txintr(struct age_softc *sc, int tpd_cons) 1321 { 1322 struct ifnet *ifp = &sc->sc_ec.ec_if; 1323 struct age_txdesc *txd; 1324 int cons, prog; 1325 1326 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1327 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1328 1329 /* 1330 * Go through our Tx list and free mbufs for those 1331 * frames which have been transmitted. 1332 */ 1333 cons = sc->age_cdata.age_tx_cons; 1334 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 1335 if (sc->age_cdata.age_tx_cnt <= 0) 1336 break; 1337 prog++; 1338 ifp->if_flags &= ~IFF_OACTIVE; 1339 sc->age_cdata.age_tx_cnt--; 1340 txd = &sc->age_cdata.age_txdesc[cons]; 1341 /* 1342 * Clear Tx descriptors, it's not required but would 1343 * help debugging in case of Tx issues. 1344 */ 1345 txd->tx_desc->addr = 0; 1346 txd->tx_desc->len = 0; 1347 txd->tx_desc->flags = 0; 1348 1349 if (txd->tx_m == NULL) 1350 continue; 1351 /* Reclaim transmitted mbufs. */ 1352 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1353 m_freem(txd->tx_m); 1354 txd->tx_m = NULL; 1355 } 1356 1357 if (prog > 0) { 1358 sc->age_cdata.age_tx_cons = cons; 1359 1360 /* 1361 * Unarm watchdog timer only when there are no pending 1362 * Tx descriptors in queue. 1363 */ 1364 if (sc->age_cdata.age_tx_cnt == 0) 1365 ifp->if_timer = 0; 1366 1367 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1368 sc->age_cdata.age_tx_ring_map->dm_mapsize, 1369 BUS_DMASYNC_PREWRITE); 1370 } 1371 } 1372 1373 /* Receive a frame. */ 1374 static void 1375 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 1376 { 1377 struct ifnet *ifp = &sc->sc_ec.ec_if; 1378 struct age_rxdesc *rxd; 1379 struct rx_desc *desc; 1380 struct mbuf *mp, *m; 1381 uint32_t status, index; 1382 int count, nsegs, pktlen; 1383 int rx_cons; 1384 1385 status = le32toh(rxrd->flags); 1386 index = le32toh(rxrd->index); 1387 rx_cons = AGE_RX_CONS(index); 1388 nsegs = AGE_RX_NSEGS(index); 1389 1390 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 1391 if ((status & AGE_RRD_ERROR) != 0 && 1392 (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 1393 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) { 1394 /* 1395 * We want to pass the following frames to upper 1396 * layer regardless of error status of Rx return 1397 * ring. 1398 * 1399 * o IP/TCP/UDP checksum is bad. 1400 * o frame length and protocol specific length 1401 * does not match. 1402 */ 1403 sc->age_cdata.age_rx_cons += nsegs; 1404 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1405 return; 1406 } 1407 1408 pktlen = 0; 1409 for (count = 0; count < nsegs; count++, 1410 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 1411 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 1412 mp = rxd->rx_m; 1413 desc = rxd->rx_desc; 1414 /* Add a new receive buffer to the ring. */ 1415 if (age_newbuf(sc, rxd, 0) != 0) { 1416 ifp->if_iqdrops++; 1417 /* Reuse Rx buffers. */ 1418 if (sc->age_cdata.age_rxhead != NULL) { 1419 m_freem(sc->age_cdata.age_rxhead); 1420 AGE_RXCHAIN_RESET(sc); 1421 } 1422 break; 1423 } 1424 1425 /* The length of the first mbuf is computed last. */ 1426 if (count != 0) { 1427 mp->m_len = AGE_RX_BYTES(le32toh(desc->len)); 1428 pktlen += mp->m_len; 1429 } 1430 1431 /* Chain received mbufs. */ 1432 if (sc->age_cdata.age_rxhead == NULL) { 1433 sc->age_cdata.age_rxhead = mp; 1434 sc->age_cdata.age_rxtail = mp; 1435 } else { 1436 mp->m_flags &= ~M_PKTHDR; 1437 sc->age_cdata.age_rxprev_tail = 1438 sc->age_cdata.age_rxtail; 1439 sc->age_cdata.age_rxtail->m_next = mp; 1440 sc->age_cdata.age_rxtail = mp; 1441 } 1442 1443 if (count == nsegs - 1) { 1444 /* 1445 * It seems that L1 controller has no way 1446 * to tell hardware to strip CRC bytes. 1447 */ 1448 sc->age_cdata.age_rxlen -= ETHER_CRC_LEN; 1449 if (nsegs > 1) { 1450 /* Remove the CRC bytes in chained mbufs. */ 1451 pktlen -= ETHER_CRC_LEN; 1452 if (mp->m_len <= ETHER_CRC_LEN) { 1453 sc->age_cdata.age_rxtail = 1454 sc->age_cdata.age_rxprev_tail; 1455 sc->age_cdata.age_rxtail->m_len -= 1456 (ETHER_CRC_LEN - mp->m_len); 1457 sc->age_cdata.age_rxtail->m_next = NULL; 1458 m_freem(mp); 1459 } else { 1460 mp->m_len -= ETHER_CRC_LEN; 1461 } 1462 } 1463 1464 m = sc->age_cdata.age_rxhead; 1465 m->m_flags |= M_PKTHDR; 1466 m->m_pkthdr.rcvif = ifp; 1467 m->m_pkthdr.len = sc->age_cdata.age_rxlen; 1468 /* Set the first mbuf length. */ 1469 m->m_len = sc->age_cdata.age_rxlen - pktlen; 1470 1471 /* 1472 * Set checksum information. 1473 * It seems that L1 controller can compute partial 1474 * checksum. The partial checksum value can be used 1475 * to accelerate checksum computation for fragmented 1476 * TCP/UDP packets. Upper network stack already 1477 * takes advantage of the partial checksum value in 1478 * IP reassembly stage. But I'm not sure the 1479 * correctness of the partial hardware checksum 1480 * assistance due to lack of data sheet. If it is 1481 * proven to work on L1 I'll enable it. 1482 */ 1483 if (status & AGE_RRD_IPV4) { 1484 if (status & AGE_RRD_IPCSUM_NOK) 1485 m->m_pkthdr.csum_flags |= 1486 M_CSUM_IPv4_BAD; 1487 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 1488 (status & AGE_RRD_TCP_UDPCSUM_NOK)) { 1489 m->m_pkthdr.csum_flags |= 1490 M_CSUM_TCP_UDP_BAD; 1491 } 1492 /* 1493 * Don't mark bad checksum for TCP/UDP frames 1494 * as fragmented frames may always have set 1495 * bad checksummed bit of descriptor status. 1496 */ 1497 } 1498 #if NVLAN > 0 1499 /* Check for VLAN tagged frames. */ 1500 if (status & AGE_RRD_VLAN) { 1501 uint32_t vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 1502 VLAN_INPUT_TAG(ifp, m, AGE_RX_VLAN_TAG(vtag), 1503 continue); 1504 } 1505 #endif 1506 1507 #if NBPFILTER > 0 1508 if (ifp->if_bpf) 1509 bpf_mtap(ifp->if_bpf, m); 1510 #endif 1511 /* Pass it on. */ 1512 ether_input(ifp, m); 1513 1514 /* Reset mbuf chains. */ 1515 AGE_RXCHAIN_RESET(sc); 1516 } 1517 } 1518 1519 if (count != nsegs) { 1520 sc->age_cdata.age_rx_cons += nsegs; 1521 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1522 } else 1523 sc->age_cdata.age_rx_cons = rx_cons; 1524 } 1525 1526 static void 1527 age_rxintr(struct age_softc *sc, int rr_prod) 1528 { 1529 struct rx_rdesc *rxrd; 1530 int rr_cons, nsegs, pktlen, prog; 1531 1532 rr_cons = sc->age_cdata.age_rr_cons; 1533 if (rr_cons == rr_prod) 1534 return; 1535 1536 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1537 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1538 BUS_DMASYNC_POSTREAD); 1539 1540 for (prog = 0; rr_cons != rr_prod; prog++) { 1541 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 1542 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 1543 if (nsegs == 0) 1544 break; 1545 /* 1546 * Check number of segments against received bytes 1547 * Non-matching value would indicate that hardware 1548 * is still trying to update Rx return descriptors. 1549 * I'm not sure whether this check is really needed. 1550 */ 1551 pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 1552 if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) / 1553 (MCLBYTES - ETHER_ALIGN))) 1554 break; 1555 1556 /* Received a frame. */ 1557 age_rxeof(sc, rxrd); 1558 1559 /* Clear return ring. */ 1560 rxrd->index = 0; 1561 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 1562 } 1563 1564 if (prog > 0) { 1565 /* Update the consumer index. */ 1566 sc->age_cdata.age_rr_cons = rr_cons; 1567 1568 /* Sync descriptors. */ 1569 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1570 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1571 BUS_DMASYNC_PREWRITE); 1572 1573 /* Notify hardware availability of new Rx buffers. */ 1574 AGE_COMMIT_MBOX(sc); 1575 } 1576 } 1577 1578 static void 1579 age_tick(void *xsc) 1580 { 1581 struct age_softc *sc = xsc; 1582 struct mii_data *mii = &sc->sc_miibus; 1583 int s; 1584 1585 s = splnet(); 1586 mii_tick(mii); 1587 splx(s); 1588 1589 callout_schedule(&sc->sc_tick_ch, hz); 1590 } 1591 1592 static void 1593 age_reset(struct age_softc *sc) 1594 { 1595 uint32_t reg; 1596 int i; 1597 1598 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 1599 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1600 DELAY(1); 1601 if ((CSR_READ_4(sc, AGE_MASTER_CFG) & MASTER_RESET) == 0) 1602 break; 1603 } 1604 if (i == 0) 1605 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 1606 1607 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1608 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1609 break; 1610 DELAY(10); 1611 } 1612 1613 if (i == 0) 1614 printf("%s: reset timeout(0x%08x)!\n", device_xname(sc->sc_dev), 1615 reg); 1616 1617 /* Initialize PCIe module. From Linux. */ 1618 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1619 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1620 } 1621 1622 static int 1623 age_init(struct ifnet *ifp) 1624 { 1625 struct age_softc *sc = ifp->if_softc; 1626 struct mii_data *mii; 1627 uint8_t eaddr[ETHER_ADDR_LEN]; 1628 bus_addr_t paddr; 1629 uint32_t reg, fsize; 1630 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 1631 int error; 1632 1633 /* 1634 * Cancel any pending I/O. 1635 */ 1636 age_stop(ifp, 0); 1637 1638 /* 1639 * Reset the chip to a known state. 1640 */ 1641 age_reset(sc); 1642 1643 /* Initialize descriptors. */ 1644 error = age_init_rx_ring(sc); 1645 if (error != 0) { 1646 printf("%s: no memory for Rx buffers.\n", device_xname(sc->sc_dev)); 1647 age_stop(ifp, 0); 1648 return error; 1649 } 1650 age_init_rr_ring(sc); 1651 age_init_tx_ring(sc); 1652 age_init_cmb_block(sc); 1653 age_init_smb_block(sc); 1654 1655 /* Reprogram the station address. */ 1656 memcpy(eaddr, CLLADDR(ifp->if_sadl), sizeof(eaddr)); 1657 CSR_WRITE_4(sc, AGE_PAR0, 1658 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1659 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 1660 1661 /* Set descriptor base addresses. */ 1662 paddr = sc->age_rdata.age_tx_ring_paddr; 1663 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 1664 paddr = sc->age_rdata.age_rx_ring_paddr; 1665 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 1666 paddr = sc->age_rdata.age_rr_ring_paddr; 1667 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 1668 paddr = sc->age_rdata.age_tx_ring_paddr; 1669 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 1670 paddr = sc->age_rdata.age_cmb_block_paddr; 1671 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1672 paddr = sc->age_rdata.age_smb_block_paddr; 1673 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1674 1675 /* Set Rx/Rx return descriptor counter. */ 1676 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 1677 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 1678 DESC_RRD_CNT_MASK) | 1679 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 1680 1681 /* Set Tx descriptor counter. */ 1682 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 1683 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 1684 1685 /* Tell hardware that we're ready to load descriptors. */ 1686 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 1687 1688 /* 1689 * Initialize mailbox register. 1690 * Updated producer/consumer index information is exchanged 1691 * through this mailbox register. However Tx producer and 1692 * Rx return consumer/Rx producer are all shared such that 1693 * it's hard to separate code path between Tx and Rx without 1694 * locking. If L1 hardware have a separate mail box register 1695 * for Tx and Rx consumer/producer management we could have 1696 * indepent Tx/Rx handler which in turn Rx handler could have 1697 * been run without any locking. 1698 */ 1699 AGE_COMMIT_MBOX(sc); 1700 1701 /* Configure IPG/IFG parameters. */ 1702 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 1703 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 1704 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1705 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1706 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 1707 1708 /* Set parameters for half-duplex media. */ 1709 CSR_WRITE_4(sc, AGE_HDPX_CFG, 1710 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1711 HDPX_CFG_LCOL_MASK) | 1712 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1713 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1714 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1715 HDPX_CFG_ABEBT_MASK) | 1716 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1717 HDPX_CFG_JAMIPG_MASK)); 1718 1719 /* Configure interrupt moderation timer. */ 1720 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 1721 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 1722 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 1723 reg &= ~MASTER_MTIMER_ENB; 1724 if (AGE_USECS(sc->age_int_mod) == 0) 1725 reg &= ~MASTER_ITIMER_ENB; 1726 else 1727 reg |= MASTER_ITIMER_ENB; 1728 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 1729 if (agedebug) 1730 printf("%s: interrupt moderation is %d us.\n", 1731 device_xname(sc->sc_dev), sc->age_int_mod); 1732 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 1733 1734 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 1735 if (ifp->if_mtu < ETHERMTU) 1736 sc->age_max_frame_size = ETHERMTU; 1737 else 1738 sc->age_max_frame_size = ifp->if_mtu; 1739 sc->age_max_frame_size += ETHER_HDR_LEN + 1740 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 1741 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 1742 1743 /* Configure jumbo frame. */ 1744 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 1745 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 1746 (((fsize / sizeof(uint64_t)) << 1747 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 1748 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 1749 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 1750 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 1751 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 1752 1753 /* Configure flow-control parameters. From Linux. */ 1754 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 1755 /* 1756 * Magic workaround for old-L1. 1757 * Don't know which hw revision requires this magic. 1758 */ 1759 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1760 /* 1761 * Another magic workaround for flow-control mode 1762 * change. From Linux. 1763 */ 1764 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1765 } 1766 /* 1767 * TODO 1768 * Should understand pause parameter relationships between FIFO 1769 * size and number of Rx descriptors and Rx return descriptors. 1770 * 1771 * Magic parameters came from Linux. 1772 */ 1773 switch (sc->age_chip_rev) { 1774 case 0x8001: 1775 case 0x9001: 1776 case 0x9002: 1777 case 0x9003: 1778 rxf_hi = AGE_RX_RING_CNT / 16; 1779 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 1780 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 1781 rrd_lo = AGE_RR_RING_CNT / 16; 1782 break; 1783 default: 1784 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 1785 rxf_lo = reg / 16; 1786 if (rxf_lo < 192) 1787 rxf_lo = 192; 1788 rxf_hi = (reg * 7) / 8; 1789 if (rxf_hi < rxf_lo) 1790 rxf_hi = rxf_lo + 16; 1791 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 1792 rrd_lo = reg / 8; 1793 rrd_hi = (reg * 7) / 8; 1794 if (rrd_lo < 2) 1795 rrd_lo = 2; 1796 if (rrd_hi < rrd_lo) 1797 rrd_hi = rrd_lo + 3; 1798 break; 1799 } 1800 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 1801 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 1802 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 1803 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 1804 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 1805 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 1806 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 1807 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 1808 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 1809 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 1810 1811 /* Configure RxQ. */ 1812 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1813 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 1814 RXQ_CFG_RD_BURST_MASK) | 1815 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 1816 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 1817 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 1818 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 1819 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1820 1821 /* Configure TxQ. */ 1822 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1823 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1824 TXQ_CFG_TPD_BURST_MASK) | 1825 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 1826 TXQ_CFG_TX_FIFO_BURST_MASK) | 1827 ((TXQ_CFG_TPD_FETCH_DEFAULT << 1828 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 1829 TXQ_CFG_ENB); 1830 1831 /* Configure DMA parameters. */ 1832 CSR_WRITE_4(sc, AGE_DMA_CFG, 1833 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 1834 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 1835 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 1836 1837 /* Configure CMB DMA write threshold. */ 1838 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 1839 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 1840 CMB_WR_THRESH_RRD_MASK) | 1841 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 1842 CMB_WR_THRESH_TPD_MASK)); 1843 1844 /* Set CMB/SMB timer and enable them. */ 1845 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 1846 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 1847 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 1848 1849 /* Request SMB updates for every seconds. */ 1850 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 1851 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 1852 1853 /* 1854 * Disable all WOL bits as WOL can interfere normal Rx 1855 * operation. 1856 */ 1857 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1858 1859 /* 1860 * Configure Tx/Rx MACs. 1861 * - Auto-padding for short frames. 1862 * - Enable CRC generation. 1863 * Start with full-duplex/1000Mbps media. Actual reconfiguration 1864 * of MAC is followed after link establishment. 1865 */ 1866 CSR_WRITE_4(sc, AGE_MAC_CFG, 1867 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 1868 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 1869 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1870 MAC_CFG_PREAMBLE_MASK)); 1871 1872 /* Set up the receive filter. */ 1873 age_rxfilter(sc); 1874 age_rxvlan(sc); 1875 1876 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1877 reg |= MAC_CFG_RXCSUM_ENB; 1878 1879 /* Ack all pending interrupts and clear it. */ 1880 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 1881 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 1882 1883 /* Finally enable Tx/Rx MAC. */ 1884 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 1885 1886 sc->age_flags &= ~AGE_FLAG_LINK; 1887 1888 /* Switch to the current media. */ 1889 mii = &sc->sc_miibus; 1890 mii_mediachg(mii); 1891 1892 callout_schedule(&sc->sc_tick_ch, hz); 1893 1894 ifp->if_flags |= IFF_RUNNING; 1895 ifp->if_flags &= ~IFF_OACTIVE; 1896 1897 return 0; 1898 } 1899 1900 static void 1901 age_stop(struct ifnet *ifp, int disable) 1902 { 1903 struct age_softc *sc = ifp->if_softc; 1904 struct age_txdesc *txd; 1905 struct age_rxdesc *rxd; 1906 uint32_t reg; 1907 int i; 1908 1909 callout_stop(&sc->sc_tick_ch); 1910 1911 /* 1912 * Mark the interface down and cancel the watchdog timer. 1913 */ 1914 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1915 ifp->if_timer = 0; 1916 1917 sc->age_flags &= ~AGE_FLAG_LINK; 1918 1919 mii_down(&sc->sc_miibus); 1920 1921 /* 1922 * Disable interrupts. 1923 */ 1924 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 1925 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 1926 1927 /* Stop CMB/SMB updates. */ 1928 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 1929 1930 /* Stop Rx/Tx MAC. */ 1931 age_stop_rxmac(sc); 1932 age_stop_txmac(sc); 1933 1934 /* Stop DMA. */ 1935 CSR_WRITE_4(sc, AGE_DMA_CFG, 1936 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 1937 1938 /* Stop TxQ/RxQ. */ 1939 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1940 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 1941 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1942 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 1943 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1944 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1945 break; 1946 DELAY(10); 1947 } 1948 if (i == 0) 1949 printf("%s: stopping Rx/Tx MACs timed out(0x%08x)!\n", 1950 device_xname(sc->sc_dev), reg); 1951 1952 /* Reclaim Rx buffers that have been processed. */ 1953 if (sc->age_cdata.age_rxhead != NULL) 1954 m_freem(sc->age_cdata.age_rxhead); 1955 AGE_RXCHAIN_RESET(sc); 1956 1957 /* 1958 * Free RX and TX mbufs still in the queues. 1959 */ 1960 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1961 rxd = &sc->age_cdata.age_rxdesc[i]; 1962 if (rxd->rx_m != NULL) { 1963 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1964 m_freem(rxd->rx_m); 1965 rxd->rx_m = NULL; 1966 } 1967 } 1968 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1969 txd = &sc->age_cdata.age_txdesc[i]; 1970 if (txd->tx_m != NULL) { 1971 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1972 m_freem(txd->tx_m); 1973 txd->tx_m = NULL; 1974 } 1975 } 1976 } 1977 1978 static void 1979 age_stats_update(struct age_softc *sc) 1980 { 1981 struct ifnet *ifp = &sc->sc_ec.ec_if; 1982 struct age_stats *stat; 1983 struct smb *smb; 1984 1985 stat = &sc->age_stat; 1986 1987 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 1988 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1989 1990 smb = sc->age_rdata.age_smb_block; 1991 if (smb->updated == 0) 1992 return; 1993 1994 /* Rx stats. */ 1995 stat->rx_frames += smb->rx_frames; 1996 stat->rx_bcast_frames += smb->rx_bcast_frames; 1997 stat->rx_mcast_frames += smb->rx_mcast_frames; 1998 stat->rx_pause_frames += smb->rx_pause_frames; 1999 stat->rx_control_frames += smb->rx_control_frames; 2000 stat->rx_crcerrs += smb->rx_crcerrs; 2001 stat->rx_lenerrs += smb->rx_lenerrs; 2002 stat->rx_bytes += smb->rx_bytes; 2003 stat->rx_runts += smb->rx_runts; 2004 stat->rx_fragments += smb->rx_fragments; 2005 stat->rx_pkts_64 += smb->rx_pkts_64; 2006 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2007 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2008 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2009 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2010 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2011 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2012 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2013 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2014 stat->rx_desc_oflows += smb->rx_desc_oflows; 2015 stat->rx_alignerrs += smb->rx_alignerrs; 2016 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2017 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2018 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2019 2020 /* Tx stats. */ 2021 stat->tx_frames += smb->tx_frames; 2022 stat->tx_bcast_frames += smb->tx_bcast_frames; 2023 stat->tx_mcast_frames += smb->tx_mcast_frames; 2024 stat->tx_pause_frames += smb->tx_pause_frames; 2025 stat->tx_excess_defer += smb->tx_excess_defer; 2026 stat->tx_control_frames += smb->tx_control_frames; 2027 stat->tx_deferred += smb->tx_deferred; 2028 stat->tx_bytes += smb->tx_bytes; 2029 stat->tx_pkts_64 += smb->tx_pkts_64; 2030 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2031 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2032 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2033 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2034 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2035 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2036 stat->tx_single_colls += smb->tx_single_colls; 2037 stat->tx_multi_colls += smb->tx_multi_colls; 2038 stat->tx_late_colls += smb->tx_late_colls; 2039 stat->tx_excess_colls += smb->tx_excess_colls; 2040 stat->tx_underrun += smb->tx_underrun; 2041 stat->tx_desc_underrun += smb->tx_desc_underrun; 2042 stat->tx_lenerrs += smb->tx_lenerrs; 2043 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2044 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2045 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2046 2047 /* Update counters in ifnet. */ 2048 ifp->if_opackets += smb->tx_frames; 2049 2050 ifp->if_collisions += smb->tx_single_colls + 2051 smb->tx_multi_colls + smb->tx_late_colls + 2052 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 2053 2054 ifp->if_oerrors += smb->tx_excess_colls + 2055 smb->tx_late_colls + smb->tx_underrun + 2056 smb->tx_pkts_truncated; 2057 2058 ifp->if_ipackets += smb->rx_frames; 2059 2060 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2061 smb->rx_runts + smb->rx_pkts_truncated + 2062 smb->rx_fifo_oflows + smb->rx_desc_oflows + 2063 smb->rx_alignerrs; 2064 2065 /* Update done, clear. */ 2066 smb->updated = 0; 2067 2068 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2069 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2070 } 2071 2072 static void 2073 age_stop_txmac(struct age_softc *sc) 2074 { 2075 uint32_t reg; 2076 int i; 2077 2078 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2079 if ((reg & MAC_CFG_TX_ENB) != 0) { 2080 reg &= ~MAC_CFG_TX_ENB; 2081 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2082 } 2083 /* Stop Tx DMA engine. */ 2084 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2085 if ((reg & DMA_CFG_RD_ENB) != 0) { 2086 reg &= ~DMA_CFG_RD_ENB; 2087 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2088 } 2089 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2090 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2091 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2092 break; 2093 DELAY(10); 2094 } 2095 if (i == 0) 2096 printf("%s: stopping TxMAC timeout!\n", device_xname(sc->sc_dev)); 2097 } 2098 2099 static void 2100 age_stop_rxmac(struct age_softc *sc) 2101 { 2102 uint32_t reg; 2103 int i; 2104 2105 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2106 if ((reg & MAC_CFG_RX_ENB) != 0) { 2107 reg &= ~MAC_CFG_RX_ENB; 2108 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2109 } 2110 /* Stop Rx DMA engine. */ 2111 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2112 if ((reg & DMA_CFG_WR_ENB) != 0) { 2113 reg &= ~DMA_CFG_WR_ENB; 2114 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2115 } 2116 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2117 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2118 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2119 break; 2120 DELAY(10); 2121 } 2122 if (i == 0) 2123 printf("%s: stopping RxMAC timeout!\n", device_xname(sc->sc_dev)); 2124 } 2125 2126 static void 2127 age_init_tx_ring(struct age_softc *sc) 2128 { 2129 struct age_ring_data *rd; 2130 struct age_txdesc *txd; 2131 int i; 2132 2133 sc->age_cdata.age_tx_prod = 0; 2134 sc->age_cdata.age_tx_cons = 0; 2135 sc->age_cdata.age_tx_cnt = 0; 2136 2137 rd = &sc->age_rdata; 2138 memset(rd->age_tx_ring, 0, AGE_TX_RING_SZ); 2139 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2140 txd = &sc->age_cdata.age_txdesc[i]; 2141 txd->tx_desc = &rd->age_tx_ring[i]; 2142 txd->tx_m = NULL; 2143 } 2144 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 2145 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2146 } 2147 2148 static int 2149 age_init_rx_ring(struct age_softc *sc) 2150 { 2151 struct age_ring_data *rd; 2152 struct age_rxdesc *rxd; 2153 int i; 2154 2155 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 2156 rd = &sc->age_rdata; 2157 memset(rd->age_rx_ring, 0, AGE_RX_RING_SZ); 2158 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2159 rxd = &sc->age_cdata.age_rxdesc[i]; 2160 rxd->rx_m = NULL; 2161 rxd->rx_desc = &rd->age_rx_ring[i]; 2162 if (age_newbuf(sc, rxd, 1) != 0) 2163 return ENOBUFS; 2164 } 2165 2166 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 0, 2167 sc->age_cdata.age_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2168 2169 return 0; 2170 } 2171 2172 static void 2173 age_init_rr_ring(struct age_softc *sc) 2174 { 2175 struct age_ring_data *rd; 2176 2177 sc->age_cdata.age_rr_cons = 0; 2178 AGE_RXCHAIN_RESET(sc); 2179 2180 rd = &sc->age_rdata; 2181 memset(rd->age_rr_ring, 0, AGE_RR_RING_SZ); 2182 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 2183 sc->age_cdata.age_rr_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2184 } 2185 2186 static void 2187 age_init_cmb_block(struct age_softc *sc) 2188 { 2189 struct age_ring_data *rd; 2190 2191 rd = &sc->age_rdata; 2192 memset(rd->age_cmb_block, 0, AGE_CMB_BLOCK_SZ); 2193 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 2194 sc->age_cdata.age_cmb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2195 } 2196 2197 static void 2198 age_init_smb_block(struct age_softc *sc) 2199 { 2200 struct age_ring_data *rd; 2201 2202 rd = &sc->age_rdata; 2203 memset(rd->age_smb_block, 0, AGE_SMB_BLOCK_SZ); 2204 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2205 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2206 } 2207 2208 static int 2209 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd, int init) 2210 { 2211 struct rx_desc *desc; 2212 struct mbuf *m; 2213 bus_dmamap_t map; 2214 int error; 2215 2216 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 2217 if (m == NULL) 2218 return ENOBUFS; 2219 MCLGET(m, init ? M_WAITOK : M_DONTWAIT); 2220 if (!(m->m_flags & M_EXT)) { 2221 m_freem(m); 2222 return ENOBUFS; 2223 } 2224 2225 m->m_len = m->m_pkthdr.len = MCLBYTES; 2226 m_adj(m, ETHER_ALIGN); 2227 2228 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2229 sc->age_cdata.age_rx_sparemap, m, BUS_DMA_NOWAIT); 2230 2231 if (error != 0) { 2232 if (!error) { 2233 bus_dmamap_unload(sc->sc_dmat, 2234 sc->age_cdata.age_rx_sparemap); 2235 error = EFBIG; 2236 printf("%s: too many segments?!\n", 2237 device_xname(sc->sc_dev)); 2238 } 2239 m_freem(m); 2240 2241 if (init) 2242 printf("%s: can't load RX mbuf\n", device_xname(sc->sc_dev)); 2243 return error; 2244 } 2245 2246 if (rxd->rx_m != NULL) { 2247 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2248 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2249 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2250 } 2251 map = rxd->rx_dmamap; 2252 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 2253 sc->age_cdata.age_rx_sparemap = map; 2254 rxd->rx_m = m; 2255 2256 desc = rxd->rx_desc; 2257 desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 2258 desc->len = 2259 htole32((rxd->rx_dmamap->dm_segs[0].ds_len & AGE_RD_LEN_MASK) << 2260 AGE_RD_LEN_SHIFT); 2261 2262 return 0; 2263 } 2264 2265 static void 2266 age_rxvlan(struct age_softc *sc) 2267 { 2268 uint32_t reg; 2269 2270 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2271 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2272 if (sc->sc_ec.ec_capabilities & ETHERCAP_VLAN_HWTAGGING) 2273 reg |= MAC_CFG_VLAN_TAG_STRIP; 2274 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2275 } 2276 2277 static void 2278 age_rxfilter(struct age_softc *sc) 2279 { 2280 struct ethercom *ec = &sc->sc_ec; 2281 struct ifnet *ifp = &sc->sc_ec.ec_if; 2282 struct ether_multi *enm; 2283 struct ether_multistep step; 2284 uint32_t crc; 2285 uint32_t mchash[2]; 2286 uint32_t rxcfg; 2287 2288 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 2289 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2290 2291 if (ifp->if_flags & IFF_BROADCAST) 2292 rxcfg |= MAC_CFG_BCAST; 2293 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 2294 if (ifp->if_flags & IFF_PROMISC) 2295 rxcfg |= MAC_CFG_PROMISC; 2296 if (ifp->if_flags & IFF_ALLMULTI) 2297 rxcfg |= MAC_CFG_ALLMULTI; 2298 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF); 2299 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF); 2300 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 2301 return; 2302 } 2303 2304 /* Program new filter. */ 2305 memset(mchash, 0, sizeof(mchash)); 2306 2307 ETHER_FIRST_MULTI(step, ec, enm); 2308 while (enm != NULL) { 2309 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 2310 enm->enm_addrlo), ETHER_ADDR_LEN); 2311 2312 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2313 ETHER_NEXT_MULTI(step, enm); 2314 } 2315 2316 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 2317 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 2318 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 2319 } 2320
Indexes created Fri Oct 03 02:09:57 GMT 2025