if_age.c revision 1.8.2.4
1 /* $NetBSD: if_age.c,v 1.8.2.4 2009/04/28 07:35:56 skrll Exp $ */ 2 /* $OpenBSD: if_age.c,v 1.1 2009/01/16 05:00:34 kevlo Exp $ */ 3 4 /*- 5 * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: if_age.c,v 1.8.2.4 2009/04/28 07:35:56 skrll Exp $"); 35 36 #include "bpfilter.h" 37 #include "vlan.h" 38 39 #include <sys/param.h> 40 #include <sys/proc.h> 41 #include <sys/endian.h> 42 #include <sys/systm.h> 43 #include <sys/types.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/queue.h> 47 #include <sys/kernel.h> 48 #include <sys/device.h> 49 #include <sys/callout.h> 50 #include <sys/socket.h> 51 52 #include <net/if.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #ifdef INET 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/in_var.h> 61 #include <netinet/ip.h> 62 #endif 63 64 #include <net/if_types.h> 65 #include <net/if_vlanvar.h> 66 67 #if NBPFILTER > 0 68 #include <net/bpf.h> 69 #endif 70 71 #include <sys/rnd.h> 72 73 #include <dev/mii/mii.h> 74 #include <dev/mii/miivar.h> 75 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/pcidevs.h> 79 80 #include <dev/pci/if_agereg.h> 81 82 static int age_match(device_t, cfdata_t, void *); 83 static void age_attach(device_t, device_t, void *); 84 static int age_detach(device_t, int); 85 86 static bool age_resume(device_t PMF_FN_PROTO); 87 88 static int age_miibus_readreg(device_t, int, int); 89 static void age_miibus_writereg(device_t, int, int, int); 90 static void age_miibus_statchg(device_t); 91 92 static int age_init(struct ifnet *); 93 static int age_ioctl(struct ifnet *, u_long, void *); 94 static void age_start(struct ifnet *); 95 static void age_watchdog(struct ifnet *); 96 static void age_mediastatus(struct ifnet *, struct ifmediareq *); 97 static int age_mediachange(struct ifnet *); 98 99 static int age_intr(void *); 100 static int age_read_vpd_word(struct age_softc *, uint32_t, uint32_t, uint32_t *); 101 static int age_dma_alloc(struct age_softc *); 102 static void age_dma_free(struct age_softc *); 103 static void age_get_macaddr(struct age_softc *, uint8_t[]); 104 static void age_phy_reset(struct age_softc *); 105 106 static int age_encap(struct age_softc *, struct mbuf **); 107 static void age_init_tx_ring(struct age_softc *); 108 static int age_init_rx_ring(struct age_softc *); 109 static void age_init_rr_ring(struct age_softc *); 110 static void age_init_cmb_block(struct age_softc *); 111 static void age_init_smb_block(struct age_softc *); 112 static int age_newbuf(struct age_softc *, struct age_rxdesc *, int); 113 static void age_mac_config(struct age_softc *); 114 static void age_txintr(struct age_softc *, int); 115 static void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 116 static void age_rxintr(struct age_softc *, int); 117 static void age_tick(void *); 118 static void age_reset(struct age_softc *); 119 static void age_stop(struct ifnet *, int); 120 static void age_stats_update(struct age_softc *); 121 static void age_stop_txmac(struct age_softc *); 122 static void age_stop_rxmac(struct age_softc *); 123 static void age_rxvlan(struct age_softc *sc); 124 static void age_rxfilter(struct age_softc *); 125 126 CFATTACH_DECL_NEW(age, sizeof(struct age_softc), 127 age_match, age_attach, age_detach, NULL); 128 129 int agedebug = 0; 130 #define DPRINTF(x) do { if (agedebug) printf x; } while (0) 131 132 #define ETHER_ALIGN 2 133 #define AGE_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 134 135 static int 136 age_match(device_t dev, cfdata_t match, void *aux) 137 { 138 struct pci_attach_args *pa = aux; 139 140 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && 141 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_GIGA); 142 } 143 144 static void 145 age_attach(device_t parent, device_t self, void *aux) 146 { 147 struct age_softc *sc = device_private(self); 148 struct pci_attach_args *pa = aux; 149 pci_intr_handle_t ih; 150 const char *intrstr; 151 struct ifnet *ifp = &sc->sc_ec.ec_if; 152 pcireg_t memtype; 153 int error = 0; 154 155 aprint_naive("\n"); 156 aprint_normal(": Attansic/Atheros L1 Gigabit Ethernet\n"); 157 158 sc->sc_dev = self; 159 sc->sc_dmat = pa->pa_dmat; 160 sc->sc_pct = pa->pa_pc; 161 sc->sc_pcitag = pa->pa_tag; 162 163 /* 164 * Allocate IO memory 165 */ 166 memtype = pci_mapreg_type(sc->sc_pct, sc->sc_pcitag, AGE_PCIR_BAR); 167 switch (memtype) { 168 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 169 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 170 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 171 break; 172 default: 173 aprint_error_dev(self, "invalid base address register\n"); 174 break; 175 } 176 177 if (pci_mapreg_map(pa, AGE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 178 &sc->sc_mem_bh, NULL, &sc->sc_mem_size) != 0) { 179 aprint_error_dev(self, "could not map mem space\n"); 180 return; 181 } 182 183 if (pci_intr_map(pa, &ih) != 0) { 184 aprint_error_dev(self, "could not map interrupt\n"); 185 goto fail; 186 } 187 188 /* 189 * Allocate IRQ 190 */ 191 intrstr = pci_intr_string(sc->sc_pct, ih); 192 sc->sc_irq_handle = pci_intr_establish(sc->sc_pct, ih, IPL_NET, 193 age_intr, sc); 194 if (sc->sc_irq_handle == NULL) { 195 aprint_error_dev(self, "could not establish interrupt"); 196 if (intrstr != NULL) 197 aprint_error(" at %s", intrstr); 198 aprint_error("\n"); 199 goto fail; 200 } 201 aprint_normal_dev(self, "%s\n", intrstr); 202 203 /* Set PHY address. */ 204 sc->age_phyaddr = AGE_PHY_ADDR; 205 206 /* Reset PHY. */ 207 age_phy_reset(sc); 208 209 /* Reset the ethernet controller. */ 210 age_reset(sc); 211 212 /* Get PCI and chip id/revision. */ 213 sc->age_rev = PCI_REVISION(pa->pa_class); 214 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 215 MASTER_CHIP_REV_SHIFT; 216 217 aprint_debug_dev(self, "PCI device revision : 0x%04x\n", sc->age_rev); 218 aprint_debug_dev(self, "Chip id/revision : 0x%04x\n", sc->age_chip_rev); 219 220 if (agedebug) { 221 aprint_debug_dev(self, "%d Tx FIFO, %d Rx FIFO\n", 222 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 223 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 224 } 225 226 /* Set max allowable DMA size. */ 227 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 228 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 229 230 /* Allocate DMA stuffs */ 231 error = age_dma_alloc(sc); 232 if (error) 233 goto fail; 234 235 callout_init(&sc->sc_tick_ch, 0); 236 callout_setfunc(&sc->sc_tick_ch, age_tick, sc); 237 238 /* Load station address. */ 239 age_get_macaddr(sc, sc->sc_enaddr); 240 241 aprint_normal_dev(self, "Ethernet address %s\n", 242 ether_sprintf(sc->sc_enaddr)); 243 244 ifp->if_softc = sc; 245 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 246 ifp->if_init = age_init; 247 ifp->if_ioctl = age_ioctl; 248 ifp->if_start = age_start; 249 ifp->if_stop = age_stop; 250 ifp->if_watchdog = age_watchdog; 251 ifp->if_baudrate = IF_Gbps(1); 252 IFQ_SET_MAXLEN(&ifp->if_snd, AGE_TX_RING_CNT - 1); 253 IFQ_SET_READY(&ifp->if_snd); 254 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 255 256 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 257 258 #ifdef AGE_CHECKSUM 259 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 260 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 261 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 262 #endif 263 264 #if NVLAN > 0 265 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 266 #endif 267 268 /* Set up MII bus. */ 269 sc->sc_miibus.mii_ifp = ifp; 270 sc->sc_miibus.mii_readreg = age_miibus_readreg; 271 sc->sc_miibus.mii_writereg = age_miibus_writereg; 272 sc->sc_miibus.mii_statchg = age_miibus_statchg; 273 274 sc->sc_ec.ec_mii = &sc->sc_miibus; 275 ifmedia_init(&sc->sc_miibus.mii_media, 0, age_mediachange, 276 age_mediastatus); 277 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 278 MII_OFFSET_ANY, 0); 279 280 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 281 aprint_error_dev(self, "no PHY found!\n"); 282 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 283 0, NULL); 284 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 285 } else 286 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 287 288 if_attach(ifp); 289 ether_ifattach(ifp, sc->sc_enaddr); 290 291 if (!pmf_device_register(self, NULL, age_resume)) 292 aprint_error_dev(self, "couldn't establish power handler\n"); 293 else 294 pmf_class_network_register(self, ifp); 295 296 return; 297 298 fail: 299 age_dma_free(sc); 300 if (sc->sc_irq_handle != NULL) { 301 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 302 sc->sc_irq_handle = NULL; 303 } 304 if (sc->sc_mem_size) { 305 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 306 sc->sc_mem_size = 0; 307 } 308 } 309 310 static int 311 age_detach(device_t self, int flags) 312 { 313 struct age_softc *sc = device_private(self); 314 struct ifnet *ifp = &sc->sc_ec.ec_if; 315 int s; 316 317 s = splnet(); 318 age_stop(ifp, 0); 319 splx(s); 320 321 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 322 323 /* Delete all remaining media. */ 324 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 325 326 ether_ifdetach(ifp); 327 if_detach(ifp); 328 age_dma_free(sc); 329 330 if (sc->sc_irq_handle != NULL) { 331 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 332 sc->sc_irq_handle = NULL; 333 } 334 335 return 0; 336 } 337 338 /* 339 * Read a PHY register on the MII of the L1. 340 */ 341 static int 342 age_miibus_readreg(device_t dev, int phy, int reg) 343 { 344 struct age_softc *sc = device_private(dev); 345 uint32_t v; 346 int i; 347 348 if (phy != sc->age_phyaddr) 349 return 0; 350 351 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 352 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 353 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 354 DELAY(1); 355 v = CSR_READ_4(sc, AGE_MDIO); 356 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 357 break; 358 } 359 360 if (i == 0) { 361 printf("%s: phy read timeout: phy %d, reg %d\n", 362 device_xname(sc->sc_dev), phy, reg); 363 return 0; 364 } 365 366 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 367 } 368 369 /* 370 * Write a PHY register on the MII of the L1. 371 */ 372 static void 373 age_miibus_writereg(device_t dev, int phy, int reg, int val) 374 { 375 struct age_softc *sc = device_private(dev); 376 uint32_t v; 377 int i; 378 379 if (phy != sc->age_phyaddr) 380 return; 381 382 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 383 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 384 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 385 386 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 387 DELAY(1); 388 v = CSR_READ_4(sc, AGE_MDIO); 389 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 390 break; 391 } 392 393 if (i == 0) { 394 printf("%s: phy write timeout: phy %d, reg %d\n", 395 device_xname(sc->sc_dev), phy, reg); 396 } 397 } 398 399 /* 400 * Callback from MII layer when media changes. 401 */ 402 static void 403 age_miibus_statchg(device_t dev) 404 { 405 struct age_softc *sc = device_private(dev); 406 struct ifnet *ifp = &sc->sc_ec.ec_if; 407 struct mii_data *mii; 408 409 if ((ifp->if_flags & IFF_RUNNING) == 0) 410 return; 411 412 mii = &sc->sc_miibus; 413 414 sc->age_flags &= ~AGE_FLAG_LINK; 415 if ((mii->mii_media_status & IFM_AVALID) != 0) { 416 switch (IFM_SUBTYPE(mii->mii_media_active)) { 417 case IFM_10_T: 418 case IFM_100_TX: 419 case IFM_1000_T: 420 sc->age_flags |= AGE_FLAG_LINK; 421 break; 422 default: 423 break; 424 } 425 } 426 427 /* Stop Rx/Tx MACs. */ 428 age_stop_rxmac(sc); 429 age_stop_txmac(sc); 430 431 /* Program MACs with resolved speed/duplex/flow-control. */ 432 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 433 uint32_t reg; 434 435 age_mac_config(sc); 436 reg = CSR_READ_4(sc, AGE_MAC_CFG); 437 /* Restart DMA engine and Tx/Rx MAC. */ 438 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 439 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 440 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 441 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 442 } 443 } 444 445 /* 446 * Get the current interface media status. 447 */ 448 static void 449 age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 450 { 451 struct age_softc *sc = ifp->if_softc; 452 struct mii_data *mii = &sc->sc_miibus; 453 454 mii_pollstat(mii); 455 ifmr->ifm_status = mii->mii_media_status; 456 ifmr->ifm_active = mii->mii_media_active; 457 } 458 459 /* 460 * Set hardware to newly-selected media. 461 */ 462 static int 463 age_mediachange(struct ifnet *ifp) 464 { 465 struct age_softc *sc = ifp->if_softc; 466 struct mii_data *mii = &sc->sc_miibus; 467 int error; 468 469 if (mii->mii_instance != 0) { 470 struct mii_softc *miisc; 471 472 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 473 mii_phy_reset(miisc); 474 } 475 error = mii_mediachg(mii); 476 477 return error; 478 } 479 480 static int 481 age_intr(void *arg) 482 { 483 struct age_softc *sc = arg; 484 struct ifnet *ifp = &sc->sc_ec.ec_if; 485 struct cmb *cmb; 486 uint32_t status; 487 488 status = CSR_READ_4(sc, AGE_INTR_STATUS); 489 if (status == 0 || (status & AGE_INTRS) == 0) 490 return 0; 491 492 cmb = sc->age_rdata.age_cmb_block; 493 if (cmb == NULL) { 494 /* Happens when bringing up the interface 495 * w/o having a carrier. Ack. the interrupt. 496 */ 497 CSR_WRITE_4(sc, AGE_INTR_STATUS, status); 498 return 0; 499 } 500 501 /* Disable interrupts. */ 502 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 503 504 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 505 sc->age_cdata.age_cmb_block_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 506 status = le32toh(cmb->intr_status); 507 if ((status & AGE_INTRS) == 0) 508 goto back; 509 510 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 511 TPD_CONS_SHIFT; 512 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 513 RRD_PROD_SHIFT; 514 515 /* Let hardware know CMB was served. */ 516 cmb->intr_status = 0; 517 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 518 sc->age_cdata.age_cmb_block_map->dm_mapsize, 519 BUS_DMASYNC_PREWRITE); 520 521 if (ifp->if_flags & IFF_RUNNING) { 522 if (status & INTR_CMB_RX) 523 age_rxintr(sc, sc->age_rr_prod); 524 525 if (status & INTR_CMB_TX) 526 age_txintr(sc, sc->age_tpd_cons); 527 528 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 529 if (status & INTR_DMA_RD_TO_RST) 530 printf("%s: DMA read error! -- resetting\n", 531 device_xname(sc->sc_dev)); 532 if (status & INTR_DMA_WR_TO_RST) 533 printf("%s: DMA write error! -- resetting\n", 534 device_xname(sc->sc_dev)); 535 age_init(ifp); 536 } 537 538 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 539 age_start(ifp); 540 541 if (status & INTR_SMB) 542 age_stats_update(sc); 543 } 544 545 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 546 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 547 sc->age_cdata.age_cmb_block_map->dm_mapsize, 548 BUS_DMASYNC_POSTREAD); 549 550 back: 551 /* Re-enable interrupts. */ 552 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 553 554 return 1; 555 } 556 557 static int 558 age_read_vpd_word(struct age_softc *sc, uint32_t vpdc, uint32_t offset, 559 uint32_t *word) 560 { 561 int i; 562 pcireg_t rv; 563 564 pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_VPD_ADDRESS(vpdc), 565 offset << PCI_VPD_ADDRESS_SHIFT); 566 for (i = AGE_TIMEOUT; i > 0; i--) { 567 DELAY(10); 568 rv = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 569 PCI_VPD_ADDRESS(vpdc)); 570 if ((rv & PCI_VPD_OPFLAG) == PCI_VPD_OPFLAG) 571 break; 572 } 573 if (i == 0) { 574 printf("%s: VPD read timeout!\n", device_xname(sc->sc_dev)); 575 *word = 0; 576 return ETIMEDOUT; 577 } 578 579 *word = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_VPD_DATAREG(vpdc)); 580 return 0; 581 } 582 583 static void 584 age_get_macaddr(struct age_softc *sc, uint8_t eaddr[]) 585 { 586 uint32_t ea[2], off, reg, word; 587 int vpd_error, match, vpdc; 588 589 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 590 if ((reg & SPI_VPD_ENB) != 0) { 591 /* Get VPD stored in TWSI EEPROM. */ 592 reg &= ~SPI_VPD_ENB; 593 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 594 } 595 596 vpd_error = 0; 597 ea[0] = ea[1] = 0; 598 if ((vpd_error = pci_get_capability(sc->sc_pct, sc->sc_pcitag, 599 PCI_CAP_VPD, &vpdc, NULL))) { 600 /* 601 * PCI VPD capability exists, but it seems that it's 602 * not in the standard form as stated in PCI VPD 603 * specification such that driver could not use 604 * pci_get_vpd_readonly(9) with keyword 'NA'. 605 * Search VPD data starting at address 0x0100. The data 606 * should be used as initializers to set AGE_PAR0, 607 * AGE_PAR1 register including other PCI configuration 608 * registers. 609 */ 610 word = 0; 611 match = 0; 612 reg = 0; 613 for (off = AGE_VPD_REG_CONF_START; off < AGE_VPD_REG_CONF_END; 614 off += sizeof(uint32_t)) { 615 vpd_error = age_read_vpd_word(sc, vpdc, off, &word); 616 if (vpd_error != 0) 617 break; 618 if (match != 0) { 619 switch (reg) { 620 case AGE_PAR0: 621 ea[0] = word; 622 break; 623 case AGE_PAR1: 624 ea[1] = word; 625 break; 626 default: 627 break; 628 } 629 match = 0; 630 } else if ((word & 0xFF) == AGE_VPD_REG_CONF_SIG) { 631 match = 1; 632 reg = word >> 16; 633 } else 634 break; 635 } 636 if (off >= AGE_VPD_REG_CONF_END) 637 vpd_error = ENOENT; 638 if (vpd_error == 0) { 639 /* 640 * Don't blindly trust ethernet address obtained 641 * from VPD. Check whether ethernet address is 642 * valid one. Otherwise fall-back to reading 643 * PAR register. 644 */ 645 ea[1] &= 0xFFFF; 646 if ((ea[0] == 0 && ea[1] == 0) || 647 (ea[0] == 0xFFFFFFFF && ea[1] == 0xFFFF)) { 648 if (agedebug) 649 printf("%s: invalid ethernet address " 650 "returned from VPD.\n", 651 device_xname(sc->sc_dev)); 652 vpd_error = EINVAL; 653 } 654 } 655 if (vpd_error != 0 && (agedebug)) 656 printf("%s: VPD access failure!\n", 657 device_xname(sc->sc_dev)); 658 } else { 659 if (agedebug) 660 printf("%s: PCI VPD capability not found!\n", 661 device_xname(sc->sc_dev)); 662 } 663 664 /* 665 * It seems that L1 also provides a way to extract ethernet 666 * address via SPI flash interface. Because SPI flash memory 667 * device of different vendors vary in their instruction 668 * codes for read ID instruction, it's very hard to get 669 * instructions codes without detailed information for the 670 * flash memory device used on ethernet controller. To simplify 671 * code, just read AGE_PAR0/AGE_PAR1 register to get ethernet 672 * address which is supposed to be set by hardware during 673 * power on reset. 674 */ 675 if (vpd_error != 0) { 676 /* 677 * VPD is mapped to SPI flash memory or BIOS set it. 678 */ 679 ea[0] = CSR_READ_4(sc, AGE_PAR0); 680 ea[1] = CSR_READ_4(sc, AGE_PAR1); 681 } 682 683 ea[1] &= 0xFFFF; 684 eaddr[0] = (ea[1] >> 8) & 0xFF; 685 eaddr[1] = (ea[1] >> 0) & 0xFF; 686 eaddr[2] = (ea[0] >> 24) & 0xFF; 687 eaddr[3] = (ea[0] >> 16) & 0xFF; 688 eaddr[4] = (ea[0] >> 8) & 0xFF; 689 eaddr[5] = (ea[0] >> 0) & 0xFF; 690 } 691 692 static void 693 age_phy_reset(struct age_softc *sc) 694 { 695 /* Reset PHY. */ 696 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 697 DELAY(1000); 698 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 699 DELAY(1000); 700 } 701 702 static int 703 age_dma_alloc(struct age_softc *sc) 704 { 705 struct age_txdesc *txd; 706 struct age_rxdesc *rxd; 707 int nsegs, error, i; 708 709 /* 710 * Create DMA stuffs for TX ring 711 */ 712 error = bus_dmamap_create(sc->sc_dmat, AGE_TX_RING_SZ, 1, 713 AGE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_tx_ring_map); 714 if (error) { 715 sc->age_cdata.age_tx_ring_map = NULL; 716 return ENOBUFS; 717 } 718 719 /* Allocate DMA'able memory for TX ring */ 720 error = bus_dmamem_alloc(sc->sc_dmat, AGE_TX_RING_SZ, 721 ETHER_ALIGN, 0, &sc->age_rdata.age_tx_ring_seg, 1, 722 &nsegs, BUS_DMA_WAITOK); 723 if (error) { 724 printf("%s: could not allocate DMA'able memory for Tx ring, " 725 "error = %i\n", device_xname(sc->sc_dev), error); 726 return error; 727 } 728 729 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_tx_ring_seg, 730 nsegs, AGE_TX_RING_SZ, (void **)&sc->age_rdata.age_tx_ring, 731 BUS_DMA_NOWAIT); 732 if (error) 733 return ENOBUFS; 734 735 memset(sc->age_rdata.age_tx_ring, 0, AGE_TX_RING_SZ); 736 737 /* Load the DMA map for Tx ring. */ 738 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 739 sc->age_rdata.age_tx_ring, AGE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 740 if (error) { 741 printf("%s: could not load DMA'able memory for Tx ring, " 742 "error = %i\n", device_xname(sc->sc_dev), error); 743 bus_dmamem_free(sc->sc_dmat, 744 &sc->age_rdata.age_tx_ring_seg, 1); 745 return error; 746 } 747 748 sc->age_rdata.age_tx_ring_paddr = 749 sc->age_cdata.age_tx_ring_map->dm_segs[0].ds_addr; 750 751 /* 752 * Create DMA stuffs for RX ring 753 */ 754 error = bus_dmamap_create(sc->sc_dmat, AGE_RX_RING_SZ, 1, 755 AGE_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_ring_map); 756 if (error) { 757 sc->age_cdata.age_rx_ring_map = NULL; 758 return ENOBUFS; 759 } 760 761 /* Allocate DMA'able memory for RX ring */ 762 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RX_RING_SZ, 763 ETHER_ALIGN, 0, &sc->age_rdata.age_rx_ring_seg, 1, 764 &nsegs, BUS_DMA_WAITOK); 765 if (error) { 766 printf("%s: could not allocate DMA'able memory for Rx ring, " 767 "error = %i.\n", device_xname(sc->sc_dev), error); 768 return error; 769 } 770 771 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rx_ring_seg, 772 nsegs, AGE_RX_RING_SZ, (void **)&sc->age_rdata.age_rx_ring, 773 BUS_DMA_NOWAIT); 774 if (error) 775 return ENOBUFS; 776 777 memset(sc->age_rdata.age_rx_ring, 0, AGE_RX_RING_SZ); 778 779 /* Load the DMA map for Rx ring. */ 780 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 781 sc->age_rdata.age_rx_ring, AGE_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 782 if (error) { 783 printf("%s: could not load DMA'able memory for Rx ring, " 784 "error = %i.\n", device_xname(sc->sc_dev), error); 785 bus_dmamem_free(sc->sc_dmat, 786 &sc->age_rdata.age_rx_ring_seg, 1); 787 return error; 788 } 789 790 sc->age_rdata.age_rx_ring_paddr = 791 sc->age_cdata.age_rx_ring_map->dm_segs[0].ds_addr; 792 793 /* 794 * Create DMA stuffs for RX return ring 795 */ 796 error = bus_dmamap_create(sc->sc_dmat, AGE_RR_RING_SZ, 1, 797 AGE_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rr_ring_map); 798 if (error) { 799 sc->age_cdata.age_rr_ring_map = NULL; 800 return ENOBUFS; 801 } 802 803 /* Allocate DMA'able memory for RX return ring */ 804 error = bus_dmamem_alloc(sc->sc_dmat, AGE_RR_RING_SZ, 805 ETHER_ALIGN, 0, &sc->age_rdata.age_rr_ring_seg, 1, 806 &nsegs, BUS_DMA_WAITOK); 807 if (error) { 808 printf("%s: could not allocate DMA'able memory for Rx " 809 "return ring, error = %i.\n", 810 device_xname(sc->sc_dev), error); 811 return error; 812 } 813 814 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_rr_ring_seg, 815 nsegs, AGE_RR_RING_SZ, (void **)&sc->age_rdata.age_rr_ring, 816 BUS_DMA_NOWAIT); 817 if (error) 818 return ENOBUFS; 819 820 memset(sc->age_rdata.age_rr_ring, 0, AGE_RR_RING_SZ); 821 822 /* Load the DMA map for Rx return ring. */ 823 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 824 sc->age_rdata.age_rr_ring, AGE_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 825 if (error) { 826 printf("%s: could not load DMA'able memory for Rx return ring, " 827 "error = %i\n", device_xname(sc->sc_dev), error); 828 bus_dmamem_free(sc->sc_dmat, 829 &sc->age_rdata.age_rr_ring_seg, 1); 830 return error; 831 } 832 833 sc->age_rdata.age_rr_ring_paddr = 834 sc->age_cdata.age_rr_ring_map->dm_segs[0].ds_addr; 835 836 /* 837 * Create DMA stuffs for CMB block 838 */ 839 error = bus_dmamap_create(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 1, 840 AGE_CMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 841 &sc->age_cdata.age_cmb_block_map); 842 if (error) { 843 sc->age_cdata.age_cmb_block_map = NULL; 844 return ENOBUFS; 845 } 846 847 /* Allocate DMA'able memory for CMB block */ 848 error = bus_dmamem_alloc(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 849 ETHER_ALIGN, 0, &sc->age_rdata.age_cmb_block_seg, 1, 850 &nsegs, BUS_DMA_WAITOK); 851 if (error) { 852 printf("%s: could not allocate DMA'able memory for " 853 "CMB block, error = %i\n", device_xname(sc->sc_dev), error); 854 return error; 855 } 856 857 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_cmb_block_seg, 858 nsegs, AGE_CMB_BLOCK_SZ, (void **)&sc->age_rdata.age_cmb_block, 859 BUS_DMA_NOWAIT); 860 if (error) 861 return ENOBUFS; 862 863 memset(sc->age_rdata.age_cmb_block, 0, AGE_CMB_BLOCK_SZ); 864 865 /* Load the DMA map for CMB block. */ 866 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 867 sc->age_rdata.age_cmb_block, AGE_CMB_BLOCK_SZ, NULL, 868 BUS_DMA_WAITOK); 869 if (error) { 870 printf("%s: could not load DMA'able memory for CMB block, " 871 "error = %i\n", device_xname(sc->sc_dev), error); 872 bus_dmamem_free(sc->sc_dmat, 873 &sc->age_rdata.age_cmb_block_seg, 1); 874 return error; 875 } 876 877 sc->age_rdata.age_cmb_block_paddr = 878 sc->age_cdata.age_cmb_block_map->dm_segs[0].ds_addr; 879 880 /* 881 * Create DMA stuffs for SMB block 882 */ 883 error = bus_dmamap_create(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 1, 884 AGE_SMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, 885 &sc->age_cdata.age_smb_block_map); 886 if (error) { 887 sc->age_cdata.age_smb_block_map = NULL; 888 return ENOBUFS; 889 } 890 891 /* Allocate DMA'able memory for SMB block */ 892 error = bus_dmamem_alloc(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 893 ETHER_ALIGN, 0, &sc->age_rdata.age_smb_block_seg, 1, 894 &nsegs, BUS_DMA_WAITOK); 895 if (error) { 896 printf("%s: could not allocate DMA'able memory for " 897 "SMB block, error = %i\n", device_xname(sc->sc_dev), error); 898 return error; 899 } 900 901 error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_smb_block_seg, 902 nsegs, AGE_SMB_BLOCK_SZ, (void **)&sc->age_rdata.age_smb_block, 903 BUS_DMA_NOWAIT); 904 if (error) 905 return ENOBUFS; 906 907 memset(sc->age_rdata.age_smb_block, 0, AGE_SMB_BLOCK_SZ); 908 909 /* Load the DMA map for SMB block */ 910 error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 911 sc->age_rdata.age_smb_block, AGE_SMB_BLOCK_SZ, NULL, 912 BUS_DMA_WAITOK); 913 if (error) { 914 printf("%s: could not load DMA'able memory for SMB block, " 915 "error = %i\n", device_xname(sc->sc_dev), error); 916 bus_dmamem_free(sc->sc_dmat, 917 &sc->age_rdata.age_smb_block_seg, 1); 918 return error; 919 } 920 921 sc->age_rdata.age_smb_block_paddr = 922 sc->age_cdata.age_smb_block_map->dm_segs[0].ds_addr; 923 924 /* Create DMA maps for Tx buffers. */ 925 for (i = 0; i < AGE_TX_RING_CNT; i++) { 926 txd = &sc->age_cdata.age_txdesc[i]; 927 txd->tx_m = NULL; 928 txd->tx_dmamap = NULL; 929 error = bus_dmamap_create(sc->sc_dmat, AGE_TSO_MAXSIZE, 930 AGE_MAXTXSEGS, AGE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 931 &txd->tx_dmamap); 932 if (error) { 933 txd->tx_dmamap = NULL; 934 printf("%s: could not create Tx dmamap, error = %i.\n", 935 device_xname(sc->sc_dev), error); 936 return error; 937 } 938 } 939 940 /* Create DMA maps for Rx buffers. */ 941 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 942 BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_sparemap); 943 if (error) { 944 sc->age_cdata.age_rx_sparemap = NULL; 945 printf("%s: could not create spare Rx dmamap, error = %i.\n", 946 device_xname(sc->sc_dev), error); 947 return error; 948 } 949 for (i = 0; i < AGE_RX_RING_CNT; i++) { 950 rxd = &sc->age_cdata.age_rxdesc[i]; 951 rxd->rx_m = NULL; 952 rxd->rx_dmamap = NULL; 953 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 954 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 955 if (error) { 956 rxd->rx_dmamap = NULL; 957 printf("%s: could not create Rx dmamap, error = %i.\n", 958 device_xname(sc->sc_dev), error); 959 return error; 960 } 961 } 962 963 return 0; 964 } 965 966 static void 967 age_dma_free(struct age_softc *sc) 968 { 969 struct age_txdesc *txd; 970 struct age_rxdesc *rxd; 971 int i; 972 973 /* Tx buffers */ 974 for (i = 0; i < AGE_TX_RING_CNT; i++) { 975 txd = &sc->age_cdata.age_txdesc[i]; 976 if (txd->tx_dmamap != NULL) { 977 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 978 txd->tx_dmamap = NULL; 979 } 980 } 981 /* Rx buffers */ 982 for (i = 0; i < AGE_RX_RING_CNT; i++) { 983 rxd = &sc->age_cdata.age_rxdesc[i]; 984 if (rxd->rx_dmamap != NULL) { 985 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 986 rxd->rx_dmamap = NULL; 987 } 988 } 989 if (sc->age_cdata.age_rx_sparemap != NULL) { 990 bus_dmamap_destroy(sc->sc_dmat, sc->age_cdata.age_rx_sparemap); 991 sc->age_cdata.age_rx_sparemap = NULL; 992 } 993 994 /* Tx ring. */ 995 if (sc->age_cdata.age_tx_ring_map != NULL) 996 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_tx_ring_map); 997 if (sc->age_cdata.age_tx_ring_map != NULL && 998 sc->age_rdata.age_tx_ring != NULL) 999 bus_dmamem_free(sc->sc_dmat, 1000 &sc->age_rdata.age_tx_ring_seg, 1); 1001 sc->age_rdata.age_tx_ring = NULL; 1002 sc->age_cdata.age_tx_ring_map = NULL; 1003 1004 /* Rx ring. */ 1005 if (sc->age_cdata.age_rx_ring_map != NULL) 1006 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rx_ring_map); 1007 if (sc->age_cdata.age_rx_ring_map != NULL && 1008 sc->age_rdata.age_rx_ring != NULL) 1009 bus_dmamem_free(sc->sc_dmat, 1010 &sc->age_rdata.age_rx_ring_seg, 1); 1011 sc->age_rdata.age_rx_ring = NULL; 1012 sc->age_cdata.age_rx_ring_map = NULL; 1013 1014 /* Rx return ring. */ 1015 if (sc->age_cdata.age_rr_ring_map != NULL) 1016 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rr_ring_map); 1017 if (sc->age_cdata.age_rr_ring_map != NULL && 1018 sc->age_rdata.age_rr_ring != NULL) 1019 bus_dmamem_free(sc->sc_dmat, 1020 &sc->age_rdata.age_rr_ring_seg, 1); 1021 sc->age_rdata.age_rr_ring = NULL; 1022 sc->age_cdata.age_rr_ring_map = NULL; 1023 1024 /* CMB block */ 1025 if (sc->age_cdata.age_cmb_block_map != NULL) 1026 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_cmb_block_map); 1027 if (sc->age_cdata.age_cmb_block_map != NULL && 1028 sc->age_rdata.age_cmb_block != NULL) 1029 bus_dmamem_free(sc->sc_dmat, 1030 &sc->age_rdata.age_cmb_block_seg, 1); 1031 sc->age_rdata.age_cmb_block = NULL; 1032 sc->age_cdata.age_cmb_block_map = NULL; 1033 1034 /* SMB block */ 1035 if (sc->age_cdata.age_smb_block_map != NULL) 1036 bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_smb_block_map); 1037 if (sc->age_cdata.age_smb_block_map != NULL && 1038 sc->age_rdata.age_smb_block != NULL) 1039 bus_dmamem_free(sc->sc_dmat, 1040 &sc->age_rdata.age_smb_block_seg, 1); 1041 sc->age_rdata.age_smb_block = NULL; 1042 sc->age_cdata.age_smb_block_map = NULL; 1043 } 1044 1045 static void 1046 age_start(struct ifnet *ifp) 1047 { 1048 struct age_softc *sc = ifp->if_softc; 1049 struct mbuf *m_head; 1050 int enq; 1051 1052 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1053 return; 1054 1055 enq = 0; 1056 for (;;) { 1057 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1058 if (m_head == NULL) 1059 break; 1060 1061 /* 1062 * Pack the data into the transmit ring. If we 1063 * don't have room, set the OACTIVE flag and wait 1064 * for the NIC to drain the ring. 1065 */ 1066 if (age_encap(sc, &m_head)) { 1067 if (m_head == NULL) 1068 break; 1069 ifp->if_flags |= IFF_OACTIVE; 1070 break; 1071 } 1072 enq = 1; 1073 1074 #if NBPFILTER > 0 1075 /* 1076 * If there's a BPF listener, bounce a copy of this frame 1077 * to him. 1078 */ 1079 if (ifp->if_bpf != NULL) 1080 bpf_mtap(ifp->if_bpf, m_head); 1081 #endif 1082 } 1083 1084 if (enq) { 1085 /* Update mbox. */ 1086 AGE_COMMIT_MBOX(sc); 1087 /* Set a timeout in case the chip goes out to lunch. */ 1088 ifp->if_timer = AGE_TX_TIMEOUT; 1089 } 1090 } 1091 1092 static void 1093 age_watchdog(struct ifnet *ifp) 1094 { 1095 struct age_softc *sc = ifp->if_softc; 1096 1097 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1098 printf("%s: watchdog timeout (missed link)\n", 1099 device_xname(sc->sc_dev)); 1100 ifp->if_oerrors++; 1101 age_init(ifp); 1102 return; 1103 } 1104 1105 if (sc->age_cdata.age_tx_cnt == 0) { 1106 printf("%s: watchdog timeout (missed Tx interrupts) " 1107 "-- recovering\n", device_xname(sc->sc_dev)); 1108 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1109 age_start(ifp); 1110 return; 1111 } 1112 1113 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1114 ifp->if_oerrors++; 1115 age_init(ifp); 1116 1117 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1118 age_start(ifp); 1119 } 1120 1121 static int 1122 age_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1123 { 1124 struct age_softc *sc = ifp->if_softc; 1125 int s, error; 1126 1127 s = splnet(); 1128 1129 error = ether_ioctl(ifp, cmd, data); 1130 if (error == ENETRESET) { 1131 if (ifp->if_flags & IFF_RUNNING) 1132 age_rxfilter(sc); 1133 error = 0; 1134 } 1135 1136 splx(s); 1137 return error; 1138 } 1139 1140 static void 1141 age_mac_config(struct age_softc *sc) 1142 { 1143 struct mii_data *mii; 1144 uint32_t reg; 1145 1146 mii = &sc->sc_miibus; 1147 1148 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1149 reg &= ~MAC_CFG_FULL_DUPLEX; 1150 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1151 reg &= ~MAC_CFG_SPEED_MASK; 1152 1153 /* Reprogram MAC with resolved speed/duplex. */ 1154 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1155 case IFM_10_T: 1156 case IFM_100_TX: 1157 reg |= MAC_CFG_SPEED_10_100; 1158 break; 1159 case IFM_1000_T: 1160 reg |= MAC_CFG_SPEED_1000; 1161 break; 1162 } 1163 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1164 reg |= MAC_CFG_FULL_DUPLEX; 1165 #ifdef notyet 1166 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1167 reg |= MAC_CFG_TX_FC; 1168 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1169 reg |= MAC_CFG_RX_FC; 1170 #endif 1171 } 1172 1173 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1174 } 1175 1176 static bool 1177 age_resume(device_t dv PMF_FN_ARGS) 1178 { 1179 struct age_softc *sc = device_private(dv); 1180 uint16_t cmd; 1181 1182 /* 1183 * Clear INTx emulation disable for hardware that 1184 * is set in resume event. From Linux. 1185 */ 1186 cmd = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 1187 if ((cmd & PCI_COMMAND_INTERRUPT_DISABLE) != 0) { 1188 cmd &= ~PCI_COMMAND_INTERRUPT_DISABLE; 1189 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 1190 PCI_COMMAND_STATUS_REG, cmd); 1191 } 1192 1193 return true; 1194 } 1195 1196 static int 1197 age_encap(struct age_softc *sc, struct mbuf **m_head) 1198 { 1199 struct age_txdesc *txd, *txd_last; 1200 struct tx_desc *desc; 1201 struct mbuf *m; 1202 bus_dmamap_t map; 1203 uint32_t cflags, poff, vtag; 1204 int error, i, nsegs, prod; 1205 #if NVLAN > 0 1206 struct m_tag *mtag; 1207 #endif 1208 1209 m = *m_head; 1210 cflags = vtag = 0; 1211 poff = 0; 1212 1213 prod = sc->age_cdata.age_tx_prod; 1214 txd = &sc->age_cdata.age_txdesc[prod]; 1215 txd_last = txd; 1216 map = txd->tx_dmamap; 1217 1218 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1219 1220 if (error == EFBIG) { 1221 error = 0; 1222 1223 MGETHDR(m, M_DONTWAIT, MT_DATA); 1224 if (m == NULL) { 1225 printf("%s: can't defrag TX mbuf\n", 1226 device_xname(sc->sc_dev)); 1227 m_freem(*m_head); 1228 *m_head = NULL; 1229 return ENOBUFS; 1230 } 1231 1232 M_COPY_PKTHDR(m, *m_head); 1233 if ((*m_head)->m_pkthdr.len > MHLEN) { 1234 MCLGET(m, M_DONTWAIT); 1235 if (!(m->m_flags & M_EXT)) { 1236 m_freem(*m_head); 1237 m_freem(m); 1238 *m_head = NULL; 1239 return ENOBUFS; 1240 } 1241 } 1242 m_copydata(*m_head, 0, (*m_head)->m_pkthdr.len, 1243 mtod(m, void *)); 1244 m_freem(*m_head); 1245 m->m_len = m->m_pkthdr.len; 1246 *m_head = m; 1247 1248 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1249 BUS_DMA_NOWAIT); 1250 1251 if (error != 0) { 1252 printf("%s: could not load defragged TX mbuf\n", 1253 device_xname(sc->sc_dev)); 1254 if (!error) { 1255 bus_dmamap_unload(sc->sc_dmat, map); 1256 error = EFBIG; 1257 } 1258 m_freem(*m_head); 1259 *m_head = NULL; 1260 return error; 1261 } 1262 } else if (error) { 1263 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 1264 return error; 1265 } 1266 1267 nsegs = map->dm_nsegs; 1268 1269 if (nsegs == 0) { 1270 m_freem(*m_head); 1271 *m_head = NULL; 1272 return EIO; 1273 } 1274 1275 /* Check descriptor overrun. */ 1276 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1277 bus_dmamap_unload(sc->sc_dmat, map); 1278 return ENOBUFS; 1279 } 1280 1281 m = *m_head; 1282 /* Configure Tx IP/TCP/UDP checksum offload. */ 1283 if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1284 cflags |= AGE_TD_CSUM; 1285 if ((m->m_pkthdr.csum_flags & M_CSUM_TCPv4) != 0) 1286 cflags |= AGE_TD_TCPCSUM; 1287 if ((m->m_pkthdr.csum_flags & M_CSUM_UDPv4) != 0) 1288 cflags |= AGE_TD_UDPCSUM; 1289 /* Set checksum start offset. */ 1290 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1291 } 1292 1293 #if NVLAN > 0 1294 /* Configure VLAN hardware tag insertion. */ 1295 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m))) { 1296 vtag = AGE_TX_VLAN_TAG(htons(VLAN_TAG_VALUE(mtag))); 1297 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1298 cflags |= AGE_TD_INSERT_VLAN_TAG; 1299 } 1300 #endif 1301 1302 desc = NULL; 1303 for (i = 0; i < nsegs; i++) { 1304 desc = &sc->age_rdata.age_tx_ring[prod]; 1305 desc->addr = htole64(map->dm_segs[i].ds_addr); 1306 desc->len = 1307 htole32(AGE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 1308 desc->flags = htole32(cflags); 1309 sc->age_cdata.age_tx_cnt++; 1310 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1311 } 1312 1313 /* Update producer index. */ 1314 sc->age_cdata.age_tx_prod = prod; 1315 1316 /* Set EOP on the last descriptor. */ 1317 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1318 desc = &sc->age_rdata.age_tx_ring[prod]; 1319 desc->flags |= htole32(AGE_TD_EOP); 1320 1321 /* Swap dmamap of the first and the last. */ 1322 txd = &sc->age_cdata.age_txdesc[prod]; 1323 map = txd_last->tx_dmamap; 1324 txd_last->tx_dmamap = txd->tx_dmamap; 1325 txd->tx_dmamap = map; 1326 txd->tx_m = m; 1327 1328 /* Sync descriptors. */ 1329 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1330 BUS_DMASYNC_PREWRITE); 1331 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1332 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1333 1334 return 0; 1335 } 1336 1337 static void 1338 age_txintr(struct age_softc *sc, int tpd_cons) 1339 { 1340 struct ifnet *ifp = &sc->sc_ec.ec_if; 1341 struct age_txdesc *txd; 1342 int cons, prog; 1343 1344 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1345 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1346 1347 /* 1348 * Go through our Tx list and free mbufs for those 1349 * frames which have been transmitted. 1350 */ 1351 cons = sc->age_cdata.age_tx_cons; 1352 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 1353 if (sc->age_cdata.age_tx_cnt <= 0) 1354 break; 1355 prog++; 1356 ifp->if_flags &= ~IFF_OACTIVE; 1357 sc->age_cdata.age_tx_cnt--; 1358 txd = &sc->age_cdata.age_txdesc[cons]; 1359 /* 1360 * Clear Tx descriptors, it's not required but would 1361 * help debugging in case of Tx issues. 1362 */ 1363 txd->tx_desc->addr = 0; 1364 txd->tx_desc->len = 0; 1365 txd->tx_desc->flags = 0; 1366 1367 if (txd->tx_m == NULL) 1368 continue; 1369 /* Reclaim transmitted mbufs. */ 1370 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1371 m_freem(txd->tx_m); 1372 txd->tx_m = NULL; 1373 } 1374 1375 if (prog > 0) { 1376 sc->age_cdata.age_tx_cons = cons; 1377 1378 /* 1379 * Unarm watchdog timer only when there are no pending 1380 * Tx descriptors in queue. 1381 */ 1382 if (sc->age_cdata.age_tx_cnt == 0) 1383 ifp->if_timer = 0; 1384 1385 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 1386 sc->age_cdata.age_tx_ring_map->dm_mapsize, 1387 BUS_DMASYNC_PREWRITE); 1388 } 1389 } 1390 1391 /* Receive a frame. */ 1392 static void 1393 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 1394 { 1395 struct ifnet *ifp = &sc->sc_ec.ec_if; 1396 struct age_rxdesc *rxd; 1397 struct rx_desc *desc; 1398 struct mbuf *mp, *m; 1399 uint32_t status, index; 1400 int count, nsegs, pktlen; 1401 int rx_cons; 1402 1403 status = le32toh(rxrd->flags); 1404 index = le32toh(rxrd->index); 1405 rx_cons = AGE_RX_CONS(index); 1406 nsegs = AGE_RX_NSEGS(index); 1407 1408 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 1409 if ((status & AGE_RRD_ERROR) != 0 && 1410 (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 1411 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) { 1412 /* 1413 * We want to pass the following frames to upper 1414 * layer regardless of error status of Rx return 1415 * ring. 1416 * 1417 * o IP/TCP/UDP checksum is bad. 1418 * o frame length and protocol specific length 1419 * does not match. 1420 */ 1421 sc->age_cdata.age_rx_cons += nsegs; 1422 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1423 return; 1424 } 1425 1426 pktlen = 0; 1427 for (count = 0; count < nsegs; count++, 1428 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 1429 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 1430 mp = rxd->rx_m; 1431 desc = rxd->rx_desc; 1432 /* Add a new receive buffer to the ring. */ 1433 if (age_newbuf(sc, rxd, 0) != 0) { 1434 ifp->if_iqdrops++; 1435 /* Reuse Rx buffers. */ 1436 if (sc->age_cdata.age_rxhead != NULL) { 1437 m_freem(sc->age_cdata.age_rxhead); 1438 AGE_RXCHAIN_RESET(sc); 1439 } 1440 break; 1441 } 1442 1443 /* The length of the first mbuf is computed last. */ 1444 if (count != 0) { 1445 mp->m_len = AGE_RX_BYTES(le32toh(desc->len)); 1446 pktlen += mp->m_len; 1447 } 1448 1449 /* Chain received mbufs. */ 1450 if (sc->age_cdata.age_rxhead == NULL) { 1451 sc->age_cdata.age_rxhead = mp; 1452 sc->age_cdata.age_rxtail = mp; 1453 } else { 1454 mp->m_flags &= ~M_PKTHDR; 1455 sc->age_cdata.age_rxprev_tail = 1456 sc->age_cdata.age_rxtail; 1457 sc->age_cdata.age_rxtail->m_next = mp; 1458 sc->age_cdata.age_rxtail = mp; 1459 } 1460 1461 if (count == nsegs - 1) { 1462 /* 1463 * It seems that L1 controller has no way 1464 * to tell hardware to strip CRC bytes. 1465 */ 1466 sc->age_cdata.age_rxlen -= ETHER_CRC_LEN; 1467 if (nsegs > 1) { 1468 /* Remove the CRC bytes in chained mbufs. */ 1469 pktlen -= ETHER_CRC_LEN; 1470 if (mp->m_len <= ETHER_CRC_LEN) { 1471 sc->age_cdata.age_rxtail = 1472 sc->age_cdata.age_rxprev_tail; 1473 sc->age_cdata.age_rxtail->m_len -= 1474 (ETHER_CRC_LEN - mp->m_len); 1475 sc->age_cdata.age_rxtail->m_next = NULL; 1476 m_freem(mp); 1477 } else { 1478 mp->m_len -= ETHER_CRC_LEN; 1479 } 1480 } 1481 1482 m = sc->age_cdata.age_rxhead; 1483 m->m_flags |= M_PKTHDR; 1484 m->m_pkthdr.rcvif = ifp; 1485 m->m_pkthdr.len = sc->age_cdata.age_rxlen; 1486 /* Set the first mbuf length. */ 1487 m->m_len = sc->age_cdata.age_rxlen - pktlen; 1488 1489 /* 1490 * Set checksum information. 1491 * It seems that L1 controller can compute partial 1492 * checksum. The partial checksum value can be used 1493 * to accelerate checksum computation for fragmented 1494 * TCP/UDP packets. Upper network stack already 1495 * takes advantage of the partial checksum value in 1496 * IP reassembly stage. But I'm not sure the 1497 * correctness of the partial hardware checksum 1498 * assistance due to lack of data sheet. If it is 1499 * proven to work on L1 I'll enable it. 1500 */ 1501 if (status & AGE_RRD_IPV4) { 1502 if (status & AGE_RRD_IPCSUM_NOK) 1503 m->m_pkthdr.csum_flags |= 1504 M_CSUM_IPv4_BAD; 1505 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 1506 (status & AGE_RRD_TCP_UDPCSUM_NOK)) { 1507 m->m_pkthdr.csum_flags |= 1508 M_CSUM_TCP_UDP_BAD; 1509 } 1510 /* 1511 * Don't mark bad checksum for TCP/UDP frames 1512 * as fragmented frames may always have set 1513 * bad checksummed bit of descriptor status. 1514 */ 1515 } 1516 #if NVLAN > 0 1517 /* Check for VLAN tagged frames. */ 1518 if (status & AGE_RRD_VLAN) { 1519 uint32_t vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 1520 VLAN_INPUT_TAG(ifp, m, AGE_RX_VLAN_TAG(vtag), 1521 continue); 1522 } 1523 #endif 1524 1525 #if NBPFILTER > 0 1526 if (ifp->if_bpf) 1527 bpf_mtap(ifp->if_bpf, m); 1528 #endif 1529 /* Pass it on. */ 1530 ether_input(ifp, m); 1531 1532 /* Reset mbuf chains. */ 1533 AGE_RXCHAIN_RESET(sc); 1534 } 1535 } 1536 1537 if (count != nsegs) { 1538 sc->age_cdata.age_rx_cons += nsegs; 1539 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 1540 } else 1541 sc->age_cdata.age_rx_cons = rx_cons; 1542 } 1543 1544 static void 1545 age_rxintr(struct age_softc *sc, int rr_prod) 1546 { 1547 struct rx_rdesc *rxrd; 1548 int rr_cons, nsegs, pktlen, prog; 1549 1550 rr_cons = sc->age_cdata.age_rr_cons; 1551 if (rr_cons == rr_prod) 1552 return; 1553 1554 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1555 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1556 BUS_DMASYNC_POSTREAD); 1557 1558 for (prog = 0; rr_cons != rr_prod; prog++) { 1559 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 1560 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 1561 if (nsegs == 0) 1562 break; 1563 /* 1564 * Check number of segments against received bytes 1565 * Non-matching value would indicate that hardware 1566 * is still trying to update Rx return descriptors. 1567 * I'm not sure whether this check is really needed. 1568 */ 1569 pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 1570 if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) / 1571 (MCLBYTES - ETHER_ALIGN))) 1572 break; 1573 1574 /* Received a frame. */ 1575 age_rxeof(sc, rxrd); 1576 1577 /* Clear return ring. */ 1578 rxrd->index = 0; 1579 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 1580 } 1581 1582 if (prog > 0) { 1583 /* Update the consumer index. */ 1584 sc->age_cdata.age_rr_cons = rr_cons; 1585 1586 /* Sync descriptors. */ 1587 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 1588 sc->age_cdata.age_rr_ring_map->dm_mapsize, 1589 BUS_DMASYNC_PREWRITE); 1590 1591 /* Notify hardware availability of new Rx buffers. */ 1592 AGE_COMMIT_MBOX(sc); 1593 } 1594 } 1595 1596 static void 1597 age_tick(void *xsc) 1598 { 1599 struct age_softc *sc = xsc; 1600 struct mii_data *mii = &sc->sc_miibus; 1601 int s; 1602 1603 s = splnet(); 1604 mii_tick(mii); 1605 splx(s); 1606 1607 callout_schedule(&sc->sc_tick_ch, hz); 1608 } 1609 1610 static void 1611 age_reset(struct age_softc *sc) 1612 { 1613 uint32_t reg; 1614 int i; 1615 1616 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 1617 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1618 DELAY(1); 1619 if ((CSR_READ_4(sc, AGE_MASTER_CFG) & MASTER_RESET) == 0) 1620 break; 1621 } 1622 if (i == 0) 1623 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 1624 1625 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1626 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1627 break; 1628 DELAY(10); 1629 } 1630 1631 if (i == 0) 1632 printf("%s: reset timeout(0x%08x)!\n", device_xname(sc->sc_dev), 1633 reg); 1634 1635 /* Initialize PCIe module. From Linux. */ 1636 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1637 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1638 } 1639 1640 static int 1641 age_init(struct ifnet *ifp) 1642 { 1643 struct age_softc *sc = ifp->if_softc; 1644 struct mii_data *mii; 1645 uint8_t eaddr[ETHER_ADDR_LEN]; 1646 bus_addr_t paddr; 1647 uint32_t reg, fsize; 1648 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 1649 int error; 1650 1651 /* 1652 * Cancel any pending I/O. 1653 */ 1654 age_stop(ifp, 0); 1655 1656 /* 1657 * Reset the chip to a known state. 1658 */ 1659 age_reset(sc); 1660 1661 /* Initialize descriptors. */ 1662 error = age_init_rx_ring(sc); 1663 if (error != 0) { 1664 printf("%s: no memory for Rx buffers.\n", device_xname(sc->sc_dev)); 1665 age_stop(ifp, 0); 1666 return error; 1667 } 1668 age_init_rr_ring(sc); 1669 age_init_tx_ring(sc); 1670 age_init_cmb_block(sc); 1671 age_init_smb_block(sc); 1672 1673 /* Reprogram the station address. */ 1674 memcpy(eaddr, CLLADDR(ifp->if_sadl), sizeof(eaddr)); 1675 CSR_WRITE_4(sc, AGE_PAR0, 1676 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1677 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 1678 1679 /* Set descriptor base addresses. */ 1680 paddr = sc->age_rdata.age_tx_ring_paddr; 1681 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 1682 paddr = sc->age_rdata.age_rx_ring_paddr; 1683 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 1684 paddr = sc->age_rdata.age_rr_ring_paddr; 1685 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 1686 paddr = sc->age_rdata.age_tx_ring_paddr; 1687 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 1688 paddr = sc->age_rdata.age_cmb_block_paddr; 1689 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1690 paddr = sc->age_rdata.age_smb_block_paddr; 1691 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 1692 1693 /* Set Rx/Rx return descriptor counter. */ 1694 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 1695 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 1696 DESC_RRD_CNT_MASK) | 1697 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 1698 1699 /* Set Tx descriptor counter. */ 1700 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 1701 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 1702 1703 /* Tell hardware that we're ready to load descriptors. */ 1704 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 1705 1706 /* 1707 * Initialize mailbox register. 1708 * Updated producer/consumer index information is exchanged 1709 * through this mailbox register. However Tx producer and 1710 * Rx return consumer/Rx producer are all shared such that 1711 * it's hard to separate code path between Tx and Rx without 1712 * locking. If L1 hardware have a separate mail box register 1713 * for Tx and Rx consumer/producer management we could have 1714 * indepent Tx/Rx handler which in turn Rx handler could have 1715 * been run without any locking. 1716 */ 1717 AGE_COMMIT_MBOX(sc); 1718 1719 /* Configure IPG/IFG parameters. */ 1720 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 1721 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 1722 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1723 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1724 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 1725 1726 /* Set parameters for half-duplex media. */ 1727 CSR_WRITE_4(sc, AGE_HDPX_CFG, 1728 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1729 HDPX_CFG_LCOL_MASK) | 1730 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1731 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1732 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1733 HDPX_CFG_ABEBT_MASK) | 1734 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1735 HDPX_CFG_JAMIPG_MASK)); 1736 1737 /* Configure interrupt moderation timer. */ 1738 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 1739 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 1740 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 1741 reg &= ~MASTER_MTIMER_ENB; 1742 if (AGE_USECS(sc->age_int_mod) == 0) 1743 reg &= ~MASTER_ITIMER_ENB; 1744 else 1745 reg |= MASTER_ITIMER_ENB; 1746 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 1747 if (agedebug) 1748 printf("%s: interrupt moderation is %d us.\n", 1749 device_xname(sc->sc_dev), sc->age_int_mod); 1750 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 1751 1752 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 1753 if (ifp->if_mtu < ETHERMTU) 1754 sc->age_max_frame_size = ETHERMTU; 1755 else 1756 sc->age_max_frame_size = ifp->if_mtu; 1757 sc->age_max_frame_size += ETHER_HDR_LEN + 1758 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 1759 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 1760 1761 /* Configure jumbo frame. */ 1762 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 1763 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 1764 (((fsize / sizeof(uint64_t)) << 1765 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 1766 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 1767 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 1768 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 1769 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 1770 1771 /* Configure flow-control parameters. From Linux. */ 1772 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 1773 /* 1774 * Magic workaround for old-L1. 1775 * Don't know which hw revision requires this magic. 1776 */ 1777 CSR_WRITE_4(sc, 0x12FC, 0x6500); 1778 /* 1779 * Another magic workaround for flow-control mode 1780 * change. From Linux. 1781 */ 1782 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1783 } 1784 /* 1785 * TODO 1786 * Should understand pause parameter relationships between FIFO 1787 * size and number of Rx descriptors and Rx return descriptors. 1788 * 1789 * Magic parameters came from Linux. 1790 */ 1791 switch (sc->age_chip_rev) { 1792 case 0x8001: 1793 case 0x9001: 1794 case 0x9002: 1795 case 0x9003: 1796 rxf_hi = AGE_RX_RING_CNT / 16; 1797 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 1798 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 1799 rrd_lo = AGE_RR_RING_CNT / 16; 1800 break; 1801 default: 1802 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 1803 rxf_lo = reg / 16; 1804 if (rxf_lo < 192) 1805 rxf_lo = 192; 1806 rxf_hi = (reg * 7) / 8; 1807 if (rxf_hi < rxf_lo) 1808 rxf_hi = rxf_lo + 16; 1809 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 1810 rrd_lo = reg / 8; 1811 rrd_hi = (reg * 7) / 8; 1812 if (rrd_lo < 2) 1813 rrd_lo = 2; 1814 if (rrd_hi < rrd_lo) 1815 rrd_hi = rrd_lo + 3; 1816 break; 1817 } 1818 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 1819 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 1820 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 1821 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 1822 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 1823 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 1824 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 1825 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 1826 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 1827 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 1828 1829 /* Configure RxQ. */ 1830 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1831 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 1832 RXQ_CFG_RD_BURST_MASK) | 1833 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 1834 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 1835 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 1836 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 1837 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1838 1839 /* Configure TxQ. */ 1840 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1841 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1842 TXQ_CFG_TPD_BURST_MASK) | 1843 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 1844 TXQ_CFG_TX_FIFO_BURST_MASK) | 1845 ((TXQ_CFG_TPD_FETCH_DEFAULT << 1846 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 1847 TXQ_CFG_ENB); 1848 1849 /* Configure DMA parameters. */ 1850 CSR_WRITE_4(sc, AGE_DMA_CFG, 1851 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 1852 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 1853 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 1854 1855 /* Configure CMB DMA write threshold. */ 1856 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 1857 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 1858 CMB_WR_THRESH_RRD_MASK) | 1859 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 1860 CMB_WR_THRESH_TPD_MASK)); 1861 1862 /* Set CMB/SMB timer and enable them. */ 1863 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 1864 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 1865 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 1866 1867 /* Request SMB updates for every seconds. */ 1868 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 1869 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 1870 1871 /* 1872 * Disable all WOL bits as WOL can interfere normal Rx 1873 * operation. 1874 */ 1875 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1876 1877 /* 1878 * Configure Tx/Rx MACs. 1879 * - Auto-padding for short frames. 1880 * - Enable CRC generation. 1881 * Start with full-duplex/1000Mbps media. Actual reconfiguration 1882 * of MAC is followed after link establishment. 1883 */ 1884 CSR_WRITE_4(sc, AGE_MAC_CFG, 1885 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 1886 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 1887 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1888 MAC_CFG_PREAMBLE_MASK)); 1889 1890 /* Set up the receive filter. */ 1891 age_rxfilter(sc); 1892 age_rxvlan(sc); 1893 1894 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1895 reg |= MAC_CFG_RXCSUM_ENB; 1896 1897 /* Ack all pending interrupts and clear it. */ 1898 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 1899 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 1900 1901 /* Finally enable Tx/Rx MAC. */ 1902 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 1903 1904 sc->age_flags &= ~AGE_FLAG_LINK; 1905 1906 /* Switch to the current media. */ 1907 mii = &sc->sc_miibus; 1908 mii_mediachg(mii); 1909 1910 callout_schedule(&sc->sc_tick_ch, hz); 1911 1912 ifp->if_flags |= IFF_RUNNING; 1913 ifp->if_flags &= ~IFF_OACTIVE; 1914 1915 return 0; 1916 } 1917 1918 static void 1919 age_stop(struct ifnet *ifp, int disable) 1920 { 1921 struct age_softc *sc = ifp->if_softc; 1922 struct age_txdesc *txd; 1923 struct age_rxdesc *rxd; 1924 uint32_t reg; 1925 int i; 1926 1927 callout_stop(&sc->sc_tick_ch); 1928 1929 /* 1930 * Mark the interface down and cancel the watchdog timer. 1931 */ 1932 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1933 ifp->if_timer = 0; 1934 1935 sc->age_flags &= ~AGE_FLAG_LINK; 1936 1937 mii_down(&sc->sc_miibus); 1938 1939 /* 1940 * Disable interrupts. 1941 */ 1942 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 1943 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 1944 1945 /* Stop CMB/SMB updates. */ 1946 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 1947 1948 /* Stop Rx/Tx MAC. */ 1949 age_stop_rxmac(sc); 1950 age_stop_txmac(sc); 1951 1952 /* Stop DMA. */ 1953 CSR_WRITE_4(sc, AGE_DMA_CFG, 1954 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 1955 1956 /* Stop TxQ/RxQ. */ 1957 CSR_WRITE_4(sc, AGE_TXQ_CFG, 1958 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 1959 CSR_WRITE_4(sc, AGE_RXQ_CFG, 1960 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 1961 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 1962 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 1963 break; 1964 DELAY(10); 1965 } 1966 if (i == 0) 1967 printf("%s: stopping Rx/Tx MACs timed out(0x%08x)!\n", 1968 device_xname(sc->sc_dev), reg); 1969 1970 /* Reclaim Rx buffers that have been processed. */ 1971 if (sc->age_cdata.age_rxhead != NULL) 1972 m_freem(sc->age_cdata.age_rxhead); 1973 AGE_RXCHAIN_RESET(sc); 1974 1975 /* 1976 * Free RX and TX mbufs still in the queues. 1977 */ 1978 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1979 rxd = &sc->age_cdata.age_rxdesc[i]; 1980 if (rxd->rx_m != NULL) { 1981 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1982 m_freem(rxd->rx_m); 1983 rxd->rx_m = NULL; 1984 } 1985 } 1986 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1987 txd = &sc->age_cdata.age_txdesc[i]; 1988 if (txd->tx_m != NULL) { 1989 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1990 m_freem(txd->tx_m); 1991 txd->tx_m = NULL; 1992 } 1993 } 1994 } 1995 1996 static void 1997 age_stats_update(struct age_softc *sc) 1998 { 1999 struct ifnet *ifp = &sc->sc_ec.ec_if; 2000 struct age_stats *stat; 2001 struct smb *smb; 2002 2003 stat = &sc->age_stat; 2004 2005 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2006 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2007 2008 smb = sc->age_rdata.age_smb_block; 2009 if (smb->updated == 0) 2010 return; 2011 2012 /* Rx stats. */ 2013 stat->rx_frames += smb->rx_frames; 2014 stat->rx_bcast_frames += smb->rx_bcast_frames; 2015 stat->rx_mcast_frames += smb->rx_mcast_frames; 2016 stat->rx_pause_frames += smb->rx_pause_frames; 2017 stat->rx_control_frames += smb->rx_control_frames; 2018 stat->rx_crcerrs += smb->rx_crcerrs; 2019 stat->rx_lenerrs += smb->rx_lenerrs; 2020 stat->rx_bytes += smb->rx_bytes; 2021 stat->rx_runts += smb->rx_runts; 2022 stat->rx_fragments += smb->rx_fragments; 2023 stat->rx_pkts_64 += smb->rx_pkts_64; 2024 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2025 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2026 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2027 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2028 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2029 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2030 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2031 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2032 stat->rx_desc_oflows += smb->rx_desc_oflows; 2033 stat->rx_alignerrs += smb->rx_alignerrs; 2034 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2035 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2036 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2037 2038 /* Tx stats. */ 2039 stat->tx_frames += smb->tx_frames; 2040 stat->tx_bcast_frames += smb->tx_bcast_frames; 2041 stat->tx_mcast_frames += smb->tx_mcast_frames; 2042 stat->tx_pause_frames += smb->tx_pause_frames; 2043 stat->tx_excess_defer += smb->tx_excess_defer; 2044 stat->tx_control_frames += smb->tx_control_frames; 2045 stat->tx_deferred += smb->tx_deferred; 2046 stat->tx_bytes += smb->tx_bytes; 2047 stat->tx_pkts_64 += smb->tx_pkts_64; 2048 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2049 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2050 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2051 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2052 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2053 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2054 stat->tx_single_colls += smb->tx_single_colls; 2055 stat->tx_multi_colls += smb->tx_multi_colls; 2056 stat->tx_late_colls += smb->tx_late_colls; 2057 stat->tx_excess_colls += smb->tx_excess_colls; 2058 stat->tx_underrun += smb->tx_underrun; 2059 stat->tx_desc_underrun += smb->tx_desc_underrun; 2060 stat->tx_lenerrs += smb->tx_lenerrs; 2061 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2062 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2063 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2064 2065 /* Update counters in ifnet. */ 2066 ifp->if_opackets += smb->tx_frames; 2067 2068 ifp->if_collisions += smb->tx_single_colls + 2069 smb->tx_multi_colls + smb->tx_late_colls + 2070 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 2071 2072 ifp->if_oerrors += smb->tx_excess_colls + 2073 smb->tx_late_colls + smb->tx_underrun + 2074 smb->tx_pkts_truncated; 2075 2076 ifp->if_ipackets += smb->rx_frames; 2077 2078 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2079 smb->rx_runts + smb->rx_pkts_truncated + 2080 smb->rx_fifo_oflows + smb->rx_desc_oflows + 2081 smb->rx_alignerrs; 2082 2083 /* Update done, clear. */ 2084 smb->updated = 0; 2085 2086 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2087 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2088 } 2089 2090 static void 2091 age_stop_txmac(struct age_softc *sc) 2092 { 2093 uint32_t reg; 2094 int i; 2095 2096 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2097 if ((reg & MAC_CFG_TX_ENB) != 0) { 2098 reg &= ~MAC_CFG_TX_ENB; 2099 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2100 } 2101 /* Stop Tx DMA engine. */ 2102 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2103 if ((reg & DMA_CFG_RD_ENB) != 0) { 2104 reg &= ~DMA_CFG_RD_ENB; 2105 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2106 } 2107 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2108 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2109 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2110 break; 2111 DELAY(10); 2112 } 2113 if (i == 0) 2114 printf("%s: stopping TxMAC timeout!\n", device_xname(sc->sc_dev)); 2115 } 2116 2117 static void 2118 age_stop_rxmac(struct age_softc *sc) 2119 { 2120 uint32_t reg; 2121 int i; 2122 2123 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2124 if ((reg & MAC_CFG_RX_ENB) != 0) { 2125 reg &= ~MAC_CFG_RX_ENB; 2126 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2127 } 2128 /* Stop Rx DMA engine. */ 2129 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2130 if ((reg & DMA_CFG_WR_ENB) != 0) { 2131 reg &= ~DMA_CFG_WR_ENB; 2132 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2133 } 2134 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2135 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2136 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2137 break; 2138 DELAY(10); 2139 } 2140 if (i == 0) 2141 printf("%s: stopping RxMAC timeout!\n", device_xname(sc->sc_dev)); 2142 } 2143 2144 static void 2145 age_init_tx_ring(struct age_softc *sc) 2146 { 2147 struct age_ring_data *rd; 2148 struct age_txdesc *txd; 2149 int i; 2150 2151 sc->age_cdata.age_tx_prod = 0; 2152 sc->age_cdata.age_tx_cons = 0; 2153 sc->age_cdata.age_tx_cnt = 0; 2154 2155 rd = &sc->age_rdata; 2156 memset(rd->age_tx_ring, 0, AGE_TX_RING_SZ); 2157 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2158 txd = &sc->age_cdata.age_txdesc[i]; 2159 txd->tx_desc = &rd->age_tx_ring[i]; 2160 txd->tx_m = NULL; 2161 } 2162 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_tx_ring_map, 0, 2163 sc->age_cdata.age_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2164 } 2165 2166 static int 2167 age_init_rx_ring(struct age_softc *sc) 2168 { 2169 struct age_ring_data *rd; 2170 struct age_rxdesc *rxd; 2171 int i; 2172 2173 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 2174 rd = &sc->age_rdata; 2175 memset(rd->age_rx_ring, 0, AGE_RX_RING_SZ); 2176 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2177 rxd = &sc->age_cdata.age_rxdesc[i]; 2178 rxd->rx_m = NULL; 2179 rxd->rx_desc = &rd->age_rx_ring[i]; 2180 if (age_newbuf(sc, rxd, 1) != 0) 2181 return ENOBUFS; 2182 } 2183 2184 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 0, 2185 sc->age_cdata.age_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2186 2187 return 0; 2188 } 2189 2190 static void 2191 age_init_rr_ring(struct age_softc *sc) 2192 { 2193 struct age_ring_data *rd; 2194 2195 sc->age_cdata.age_rr_cons = 0; 2196 AGE_RXCHAIN_RESET(sc); 2197 2198 rd = &sc->age_rdata; 2199 memset(rd->age_rr_ring, 0, AGE_RR_RING_SZ); 2200 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, 2201 sc->age_cdata.age_rr_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2202 } 2203 2204 static void 2205 age_init_cmb_block(struct age_softc *sc) 2206 { 2207 struct age_ring_data *rd; 2208 2209 rd = &sc->age_rdata; 2210 memset(rd->age_cmb_block, 0, AGE_CMB_BLOCK_SZ); 2211 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, 0, 2212 sc->age_cdata.age_cmb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2213 } 2214 2215 static void 2216 age_init_smb_block(struct age_softc *sc) 2217 { 2218 struct age_ring_data *rd; 2219 2220 rd = &sc->age_rdata; 2221 memset(rd->age_smb_block, 0, AGE_SMB_BLOCK_SZ); 2222 bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_smb_block_map, 0, 2223 sc->age_cdata.age_smb_block_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2224 } 2225 2226 static int 2227 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd, int init) 2228 { 2229 struct rx_desc *desc; 2230 struct mbuf *m; 2231 bus_dmamap_t map; 2232 int error; 2233 2234 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 2235 if (m == NULL) 2236 return ENOBUFS; 2237 MCLGET(m, init ? M_WAITOK : M_DONTWAIT); 2238 if (!(m->m_flags & M_EXT)) { 2239 m_freem(m); 2240 return ENOBUFS; 2241 } 2242 2243 m->m_len = m->m_pkthdr.len = MCLBYTES; 2244 m_adj(m, ETHER_ALIGN); 2245 2246 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2247 sc->age_cdata.age_rx_sparemap, m, BUS_DMA_NOWAIT); 2248 2249 if (error != 0) { 2250 if (!error) { 2251 bus_dmamap_unload(sc->sc_dmat, 2252 sc->age_cdata.age_rx_sparemap); 2253 error = EFBIG; 2254 printf("%s: too many segments?!\n", 2255 device_xname(sc->sc_dev)); 2256 } 2257 m_freem(m); 2258 2259 if (init) 2260 printf("%s: can't load RX mbuf\n", device_xname(sc->sc_dev)); 2261 return error; 2262 } 2263 2264 if (rxd->rx_m != NULL) { 2265 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2266 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2267 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2268 } 2269 map = rxd->rx_dmamap; 2270 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 2271 sc->age_cdata.age_rx_sparemap = map; 2272 rxd->rx_m = m; 2273 2274 desc = rxd->rx_desc; 2275 desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 2276 desc->len = 2277 htole32((rxd->rx_dmamap->dm_segs[0].ds_len & AGE_RD_LEN_MASK) << 2278 AGE_RD_LEN_SHIFT); 2279 2280 return 0; 2281 } 2282 2283 static void 2284 age_rxvlan(struct age_softc *sc) 2285 { 2286 uint32_t reg; 2287 2288 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2289 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2290 if (sc->sc_ec.ec_capabilities & ETHERCAP_VLAN_HWTAGGING) 2291 reg |= MAC_CFG_VLAN_TAG_STRIP; 2292 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2293 } 2294 2295 static void 2296 age_rxfilter(struct age_softc *sc) 2297 { 2298 struct ethercom *ec = &sc->sc_ec; 2299 struct ifnet *ifp = &sc->sc_ec.ec_if; 2300 struct ether_multi *enm; 2301 struct ether_multistep step; 2302 uint32_t crc; 2303 uint32_t mchash[2]; 2304 uint32_t rxcfg; 2305 2306 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 2307 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2308 ifp->if_flags &= ~IFF_ALLMULTI; 2309 2310 /* 2311 * Always accept broadcast frames. 2312 */ 2313 rxcfg |= MAC_CFG_BCAST; 2314 2315 if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 2316 ifp->if_flags |= IFF_ALLMULTI; 2317 if (ifp->if_flags & IFF_PROMISC) 2318 rxcfg |= MAC_CFG_PROMISC; 2319 else 2320 rxcfg |= MAC_CFG_ALLMULTI; 2321 mchash[0] = mchash[1] = 0xFFFFFFFF; 2322 } else { 2323 /* Program new filter. */ 2324 memset(mchash, 0, sizeof(mchash)); 2325 2326 ETHER_FIRST_MULTI(step, ec, enm); 2327 while (enm != NULL) { 2328 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2329 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2330 ETHER_NEXT_MULTI(step, enm); 2331 } 2332 } 2333 2334 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 2335 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 2336 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 2337 } 2338
Indexes created Fri Oct 03 02:09:57 GMT 2025