if_alc.c revision 1.12
1 /* $OpenBSD: if_alc.c,v 1.1 2009/08/08 09:31:13 kevlo Exp $ */ 2 /*- 3 * Copyright (c) 2009, Pyun YongHyeon <yongari (at) FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 30 31 #ifdef _KERNEL_OPT 32 #include "vlan.h" 33 #endif 34 35 #include <sys/param.h> 36 #include <sys/proc.h> 37 #include <sys/endian.h> 38 #include <sys/systm.h> 39 #include <sys/types.h> 40 #include <sys/sockio.h> 41 #include <sys/mbuf.h> 42 #include <sys/queue.h> 43 #include <sys/kernel.h> 44 #include <sys/device.h> 45 #include <sys/callout.h> 46 #include <sys/socket.h> 47 #include <sys/module.h> 48 49 #include <sys/bus.h> 50 51 #include <net/if.h> 52 #include <net/if_dl.h> 53 #include <net/if_llc.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #include <net/bpf.h> 58 59 #ifdef INET 60 #include <netinet/in.h> 61 #include <netinet/in_systm.h> 62 #include <netinet/in_var.h> 63 #include <netinet/ip.h> 64 #endif 65 66 #include <net/if_types.h> 67 #include <net/if_vlanvar.h> 68 69 #include <net/bpf.h> 70 71 #include <sys/rnd.h> 72 73 #include <dev/mii/mii.h> 74 #include <dev/mii/miivar.h> 75 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/pcidevs.h> 79 80 #include <dev/pci/if_alcreg.h> 81 82 /* 83 * Devices supported by this driver. 84 */ 85 static struct alc_ident alc_ident_table[] = { 86 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8131, 9 * 1024, 87 "Atheros AR8131 PCIe Gigabit Ethernet" }, 88 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8132, 9 * 1024, 89 "Atheros AR8132 PCIe Fast Ethernet" }, 90 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8151, 6 * 1024, 91 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 92 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8151_V2, 6 * 1024, 93 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 94 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8152_B, 6 * 1024, 95 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 96 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8152_B2, 6 * 1024, 97 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 98 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8161, 9 * 1024, 99 "Atheros AR8161 PCIe Gigabit Ethernet" }, 100 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8162, 9 * 1024, 101 "Atheros AR8162 PCIe Fast Ethernet" }, 102 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8171, 9 * 1024, 103 "Atheros AR8171 PCIe Gigabit Ethernet" }, 104 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8172, 9 * 1024, 105 "Atheros AR8172 PCIe Fast Ethernet" }, 106 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_E2200, 9 * 1024, 107 "Killer E2200 Gigabit Ethernet" }, 108 { 0, 0, 0, NULL }, 109 }; 110 111 static int alc_match(device_t, cfdata_t, void *); 112 static void alc_attach(device_t, device_t, void *); 113 static int alc_detach(device_t, int); 114 115 static int alc_init(struct ifnet *); 116 static int alc_init_backend(struct ifnet *, bool); 117 static void alc_start(struct ifnet *); 118 static int alc_ioctl(struct ifnet *, u_long, void *); 119 static void alc_watchdog(struct ifnet *); 120 static int alc_mediachange(struct ifnet *); 121 static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 122 123 static void alc_aspm(struct alc_softc *, int, int); 124 static void alc_aspm_813x(struct alc_softc *, int); 125 static void alc_aspm_816x(struct alc_softc *, int); 126 static void alc_disable_l0s_l1(struct alc_softc *); 127 static int alc_dma_alloc(struct alc_softc *); 128 static void alc_dma_free(struct alc_softc *); 129 static void alc_dsp_fixup(struct alc_softc *, int); 130 static int alc_encap(struct alc_softc *, struct mbuf **); 131 static struct alc_ident * 132 alc_find_ident(struct pci_attach_args *); 133 static void alc_get_macaddr(struct alc_softc *); 134 static void alc_get_macaddr_813x(struct alc_softc *); 135 static void alc_get_macaddr_816x(struct alc_softc *); 136 static void alc_get_macaddr_par(struct alc_softc *); 137 static void alc_init_cmb(struct alc_softc *); 138 static void alc_init_rr_ring(struct alc_softc *); 139 static int alc_init_rx_ring(struct alc_softc *, bool); 140 static void alc_init_smb(struct alc_softc *); 141 static void alc_init_tx_ring(struct alc_softc *); 142 static int alc_intr(void *); 143 static void alc_mac_config(struct alc_softc *); 144 static uint32_t alc_mii_readreg_813x(struct alc_softc *, int, int); 145 static uint32_t alc_mii_readreg_816x(struct alc_softc *, int, int); 146 static void alc_mii_writereg_813x(struct alc_softc *, int, int, int); 147 static void alc_mii_writereg_816x(struct alc_softc *, int, int, int); 148 static int alc_miibus_readreg(device_t, int, int); 149 static void alc_miibus_statchg(struct ifnet *); 150 static void alc_miibus_writereg(device_t, int, int, int); 151 static uint32_t alc_miidbg_readreg(struct alc_softc *, int); 152 static void alc_miidbg_writereg(struct alc_softc *, int, int); 153 static uint32_t alc_miiext_readreg(struct alc_softc *, int, int); 154 static uint32_t alc_miiext_writereg(struct alc_softc *, int, int, int); 155 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *, bool); 156 static void alc_phy_down(struct alc_softc *); 157 static void alc_phy_reset(struct alc_softc *); 158 static void alc_phy_reset_813x(struct alc_softc *); 159 static void alc_phy_reset_816x(struct alc_softc *); 160 static void alc_reset(struct alc_softc *); 161 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 162 static int alc_rxintr(struct alc_softc *); 163 static void alc_iff(struct alc_softc *); 164 static void alc_rxvlan(struct alc_softc *); 165 static void alc_start_queue(struct alc_softc *); 166 static void alc_stats_clear(struct alc_softc *); 167 static void alc_stats_update(struct alc_softc *); 168 static void alc_stop(struct ifnet *, int); 169 static void alc_stop_mac(struct alc_softc *); 170 static void alc_stop_queue(struct alc_softc *); 171 static void alc_tick(void *); 172 static void alc_txeof(struct alc_softc *); 173 174 uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 175 176 CFATTACH_DECL_NEW(alc, sizeof(struct alc_softc), 177 alc_match, alc_attach, alc_detach, NULL); 178 179 int alcdebug = 0; 180 #define DPRINTF(x) do { if (alcdebug) printf x; } while (0) 181 182 #define ETHER_ALIGN 2 183 #define ALC_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 184 185 static int 186 alc_miibus_readreg(device_t dev, int phy, int reg) 187 { 188 struct alc_softc *sc = device_private(dev); 189 int v; 190 191 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 192 v = alc_mii_readreg_816x(sc, phy, reg); 193 else 194 v = alc_mii_readreg_813x(sc, phy, reg); 195 return (v); 196 } 197 198 static uint32_t 199 alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg) 200 { 201 uint32_t v; 202 int i; 203 204 if (phy != sc->alc_phyaddr) 205 return (0); 206 207 /* 208 * For AR8132 fast ethernet controller, do not report 1000baseT 209 * capability to mii(4). Even though AR8132 uses the same 210 * model/revision number of F1 gigabit PHY, the PHY has no 211 * ability to establish 1000baseT link. 212 */ 213 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 214 reg == MII_EXTSR) 215 return 0; 216 217 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 218 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 219 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 220 DELAY(5); 221 v = CSR_READ_4(sc, ALC_MDIO); 222 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 223 break; 224 } 225 226 if (i == 0) { 227 printf("%s: phy read timeout: phy %d, reg %d\n", 228 device_xname(sc->sc_dev), phy, reg); 229 return (0); 230 } 231 232 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 233 } 234 235 static uint32_t 236 alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg) 237 { 238 uint32_t clk, v; 239 int i; 240 241 if (phy != sc->alc_phyaddr) 242 return (0); 243 244 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 245 clk = MDIO_CLK_25_128; 246 else 247 clk = MDIO_CLK_25_4; 248 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 249 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg)); 250 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 251 DELAY(5); 252 v = CSR_READ_4(sc, ALC_MDIO); 253 if ((v & MDIO_OP_BUSY) == 0) 254 break; 255 } 256 257 if (i == 0) { 258 printf("%s: phy read timeout: phy %d, reg %d\n", 259 device_xname(sc->sc_dev), phy, reg); 260 return (0); 261 } 262 263 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 264 } 265 266 static void 267 alc_miibus_writereg(device_t dev, int phy, int reg, int val) 268 { 269 struct alc_softc *sc = device_private(dev); 270 271 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 272 alc_mii_writereg_816x(sc, phy, reg, val); 273 else 274 alc_mii_writereg_813x(sc, phy, reg, val); 275 276 return; 277 } 278 279 static void 280 alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val) 281 { 282 uint32_t v; 283 int i; 284 285 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 286 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 287 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 288 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 289 DELAY(5); 290 v = CSR_READ_4(sc, ALC_MDIO); 291 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 292 break; 293 } 294 295 if (i == 0) 296 printf("%s: phy write timeout: phy %d, reg %d\n", 297 device_xname(sc->sc_dev), phy, reg); 298 299 return; 300 } 301 302 static void 303 alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val) 304 { 305 uint32_t clk, v; 306 int i; 307 308 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 309 clk = MDIO_CLK_25_128; 310 else 311 clk = MDIO_CLK_25_4; 312 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 313 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) | 314 MDIO_SUP_PREAMBLE | clk); 315 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 316 DELAY(5); 317 v = CSR_READ_4(sc, ALC_MDIO); 318 if ((v & MDIO_OP_BUSY) == 0) 319 break; 320 } 321 322 if (i == 0) 323 printf("%s: phy write timeout: phy %d, reg %d\n", 324 device_xname(sc->sc_dev), phy, reg); 325 326 return; 327 } 328 329 static void 330 alc_miibus_statchg(struct ifnet *ifp) 331 { 332 struct alc_softc *sc = ifp->if_softc; 333 struct mii_data *mii = &sc->sc_miibus; 334 uint32_t reg; 335 336 if ((ifp->if_flags & IFF_RUNNING) == 0) 337 return; 338 339 sc->alc_flags &= ~ALC_FLAG_LINK; 340 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 341 (IFM_ACTIVE | IFM_AVALID)) { 342 switch (IFM_SUBTYPE(mii->mii_media_active)) { 343 case IFM_10_T: 344 case IFM_100_TX: 345 sc->alc_flags |= ALC_FLAG_LINK; 346 break; 347 case IFM_1000_T: 348 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 349 sc->alc_flags |= ALC_FLAG_LINK; 350 break; 351 default: 352 break; 353 } 354 } 355 /* Stop Rx/Tx MACs. */ 356 alc_stop_mac(sc); 357 358 /* Program MACs with resolved speed/duplex/flow-control. */ 359 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 360 alc_start_queue(sc); 361 alc_mac_config(sc); 362 /* Re-enable Tx/Rx MACs. */ 363 reg = CSR_READ_4(sc, ALC_MAC_CFG); 364 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 365 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 366 } 367 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active)); 368 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active)); 369 } 370 371 static uint32_t 372 alc_miidbg_readreg(struct alc_softc *sc, int reg) 373 { 374 375 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 376 reg); 377 return (alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 378 ALC_MII_DBG_DATA)); 379 } 380 381 static void 382 alc_miidbg_writereg(struct alc_softc *sc, int reg, int val) 383 { 384 385 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 386 reg); 387 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, val); 388 389 return; 390 } 391 392 static uint32_t 393 alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg) 394 { 395 uint32_t clk, v; 396 int i; 397 398 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 399 EXT_MDIO_DEVADDR(devaddr)); 400 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 401 clk = MDIO_CLK_25_128; 402 else 403 clk = MDIO_CLK_25_4; 404 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 405 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 406 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 407 DELAY(5); 408 v = CSR_READ_4(sc, ALC_MDIO); 409 if ((v & MDIO_OP_BUSY) == 0) 410 break; 411 } 412 413 if (i == 0) { 414 printf("%s: phy ext read timeout: %d\n", 415 device_xname(sc->sc_dev), reg); 416 return (0); 417 } 418 419 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 420 } 421 422 static uint32_t 423 alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val) 424 { 425 uint32_t clk, v; 426 int i; 427 428 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 429 EXT_MDIO_DEVADDR(devaddr)); 430 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 431 clk = MDIO_CLK_25_128; 432 else 433 clk = MDIO_CLK_25_4; 434 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 435 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | 436 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 437 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 438 DELAY(5); 439 v = CSR_READ_4(sc, ALC_MDIO); 440 if ((v & MDIO_OP_BUSY) == 0) 441 break; 442 } 443 444 if (i == 0) { 445 printf("%s: phy ext write timeout: reg %d\n", 446 device_xname(sc->sc_dev), reg); 447 return (0); 448 } 449 450 return (0); 451 } 452 453 static void 454 alc_dsp_fixup(struct alc_softc *sc, int media) 455 { 456 uint16_t agc, len, val; 457 458 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 459 return; 460 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0) 461 return; 462 463 /* 464 * Vendor PHY magic. 465 * 1000BT/AZ, wrong cable length 466 */ 467 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 468 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6); 469 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) & 470 EXT_CLDCTL6_CAB_LEN_MASK; 471 agc = alc_miidbg_readreg(sc, MII_DBG_AGC); 472 agc = (agc >> DBG_AGC_2_VGA_SHIFT) & DBG_AGC_2_VGA_MASK; 473 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G && 474 agc > DBG_AGC_LONG1G_LIMT) || 475 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT && 476 agc > DBG_AGC_LONG1G_LIMT)) { 477 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 478 DBG_AZ_ANADECT_LONG); 479 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 480 MII_EXT_ANEG_AFE); 481 val |= ANEG_AFEE_10BT_100M_TH; 482 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 483 val); 484 } else { 485 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 486 DBG_AZ_ANADECT_DEFAULT); 487 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 488 MII_EXT_ANEG_AFE); 489 val &= ~ANEG_AFEE_10BT_100M_TH; 490 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 491 val); 492 } 493 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 494 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 495 if (media == IFM_1000_T) { 496 /* 497 * Giga link threshold, raise the tolerance of 498 * noise 50%. 499 */ 500 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 501 val &= ~DBG_MSE20DB_TH_MASK; 502 val |= (DBG_MSE20DB_TH_HI << 503 DBG_MSE20DB_TH_SHIFT); 504 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 505 } else if (media == IFM_100_TX) 506 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 507 DBG_MSE16DB_UP); 508 } 509 } else { 510 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE); 511 val &= ~ANEG_AFEE_10BT_100M_TH; 512 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); 513 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 514 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 515 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 516 DBG_MSE16DB_DOWN); 517 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 518 val &= ~DBG_MSE20DB_TH_MASK; 519 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT); 520 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 521 } 522 } 523 } 524 525 static void 526 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 527 { 528 struct alc_softc *sc = ifp->if_softc; 529 struct mii_data *mii = &sc->sc_miibus; 530 531 mii_pollstat(mii); 532 ifmr->ifm_status = mii->mii_media_status; 533 ifmr->ifm_active = mii->mii_media_active; 534 } 535 536 static int 537 alc_mediachange(struct ifnet *ifp) 538 { 539 struct alc_softc *sc = ifp->if_softc; 540 struct mii_data *mii = &sc->sc_miibus; 541 int error; 542 543 if (mii->mii_instance != 0) { 544 struct mii_softc *miisc; 545 546 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 547 mii_phy_reset(miisc); 548 } 549 error = mii_mediachg(mii); 550 551 return (error); 552 } 553 554 static struct alc_ident * 555 alc_find_ident(struct pci_attach_args *pa) 556 { 557 struct alc_ident *ident; 558 uint16_t vendor, devid; 559 560 vendor = PCI_VENDOR(pa->pa_id); 561 devid = PCI_PRODUCT(pa->pa_id); 562 for (ident = alc_ident_table; ident->name != NULL; ident++) { 563 if (vendor == ident->vendorid && devid == ident->deviceid) 564 return (ident); 565 } 566 567 return (NULL); 568 } 569 570 static int 571 alc_match(device_t dev, cfdata_t match, void *aux) 572 { 573 struct pci_attach_args *pa = aux; 574 575 return alc_find_ident(pa) != NULL; 576 } 577 578 static void 579 alc_get_macaddr(struct alc_softc *sc) 580 { 581 582 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 583 alc_get_macaddr_816x(sc); 584 else 585 alc_get_macaddr_813x(sc); 586 } 587 588 static void 589 alc_get_macaddr_813x(struct alc_softc *sc) 590 { 591 uint32_t opt; 592 uint16_t val; 593 int eeprom, i; 594 595 eeprom = 0; 596 opt = CSR_READ_4(sc, ALC_OPT_CFG); 597 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 598 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 599 /* 600 * EEPROM found, let TWSI reload EEPROM configuration. 601 * This will set ethernet address of controller. 602 */ 603 eeprom++; 604 switch (sc->alc_ident->deviceid) { 605 case PCI_PRODUCT_ATTANSIC_AR8131: 606 case PCI_PRODUCT_ATTANSIC_AR8132: 607 if ((opt & OPT_CFG_CLK_ENB) == 0) { 608 opt |= OPT_CFG_CLK_ENB; 609 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 610 CSR_READ_4(sc, ALC_OPT_CFG); 611 DELAY(1000); 612 } 613 break; 614 case PCI_PRODUCT_ATTANSIC_AR8151: 615 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 616 case PCI_PRODUCT_ATTANSIC_AR8152_B: 617 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 618 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 619 ALC_MII_DBG_ADDR, 0x00); 620 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 621 ALC_MII_DBG_DATA); 622 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 623 ALC_MII_DBG_DATA, val & 0xFF7F); 624 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 625 ALC_MII_DBG_ADDR, 0x3B); 626 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 627 ALC_MII_DBG_DATA); 628 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 629 ALC_MII_DBG_DATA, val | 0x0008); 630 DELAY(20); 631 break; 632 } 633 634 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 635 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 636 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 637 CSR_READ_4(sc, ALC_WOL_CFG); 638 639 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 640 TWSI_CFG_SW_LD_START); 641 for (i = 100; i > 0; i--) { 642 DELAY(1000); 643 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 644 TWSI_CFG_SW_LD_START) == 0) 645 break; 646 } 647 if (i == 0) 648 printf("%s: reloading EEPROM timeout!\n", 649 device_xname(sc->sc_dev)); 650 } else { 651 if (alcdebug) 652 printf("%s: EEPROM not found!\n", device_xname(sc->sc_dev)); 653 } 654 if (eeprom != 0) { 655 switch (sc->alc_ident->deviceid) { 656 case PCI_PRODUCT_ATTANSIC_AR8131: 657 case PCI_PRODUCT_ATTANSIC_AR8132: 658 if ((opt & OPT_CFG_CLK_ENB) != 0) { 659 opt &= ~OPT_CFG_CLK_ENB; 660 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 661 CSR_READ_4(sc, ALC_OPT_CFG); 662 DELAY(1000); 663 } 664 break; 665 case PCI_PRODUCT_ATTANSIC_AR8151: 666 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 667 case PCI_PRODUCT_ATTANSIC_AR8152_B: 668 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 669 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 670 ALC_MII_DBG_ADDR, 0x00); 671 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 672 ALC_MII_DBG_DATA); 673 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 674 ALC_MII_DBG_DATA, val | 0x0080); 675 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 676 ALC_MII_DBG_ADDR, 0x3B); 677 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 678 ALC_MII_DBG_DATA); 679 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 680 ALC_MII_DBG_DATA, val & 0xFFF7); 681 DELAY(20); 682 break; 683 } 684 } 685 686 alc_get_macaddr_par(sc); 687 } 688 689 static void 690 alc_get_macaddr_816x(struct alc_softc *sc) 691 { 692 uint32_t reg; 693 int i, reloaded; 694 695 reloaded = 0; 696 /* Try to reload station address via TWSI. */ 697 for (i = 100; i > 0; i--) { 698 reg = CSR_READ_4(sc, ALC_SLD); 699 if ((reg & (SLD_PROGRESS | SLD_START)) == 0) 700 break; 701 DELAY(1000); 702 } 703 if (i != 0) { 704 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); 705 for (i = 100; i > 0; i--) { 706 DELAY(1000); 707 reg = CSR_READ_4(sc, ALC_SLD); 708 if ((reg & SLD_START) == 0) 709 break; 710 } 711 if (i != 0) 712 reloaded++; 713 else if (alcdebug) 714 printf("%s: reloading station address via TWSI timed out!\n", 715 device_xname(sc->sc_dev)); 716 } 717 718 /* Try to reload station address from EEPROM or FLASH. */ 719 if (reloaded == 0) { 720 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 721 if ((reg & (EEPROM_LD_EEPROM_EXIST | 722 EEPROM_LD_FLASH_EXIST)) != 0) { 723 for (i = 100; i > 0; i--) { 724 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 725 if ((reg & (EEPROM_LD_PROGRESS | 726 EEPROM_LD_START)) == 0) 727 break; 728 DELAY(1000); 729 } 730 if (i != 0) { 731 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | 732 EEPROM_LD_START); 733 for (i = 100; i > 0; i--) { 734 DELAY(1000); 735 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 736 if ((reg & EEPROM_LD_START) == 0) 737 break; 738 } 739 } else if (alcdebug) 740 printf("%s: reloading EEPROM/FLASH timed out!\n", 741 device_xname(sc->sc_dev)); 742 } 743 } 744 745 alc_get_macaddr_par(sc); 746 } 747 748 749 static void 750 alc_get_macaddr_par(struct alc_softc *sc) 751 { 752 uint32_t ea[2]; 753 754 ea[0] = CSR_READ_4(sc, ALC_PAR0); 755 ea[1] = CSR_READ_4(sc, ALC_PAR1); 756 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 757 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 758 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 759 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 760 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 761 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 762 } 763 764 static void 765 alc_disable_l0s_l1(struct alc_softc *sc) 766 { 767 uint32_t pmcfg; 768 769 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 770 /* Another magic from vendor. */ 771 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 772 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 773 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 774 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1); 775 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | 776 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB; 777 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 778 } 779 } 780 781 static void 782 alc_phy_reset(struct alc_softc *sc) 783 { 784 785 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 786 alc_phy_reset_816x(sc); 787 else 788 alc_phy_reset_813x(sc); 789 } 790 791 static void 792 alc_phy_reset_813x(struct alc_softc *sc) 793 { 794 uint16_t data; 795 796 /* Reset magic from Linux. */ 797 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 798 CSR_READ_2(sc, ALC_GPHY_CFG); 799 DELAY(10 * 1000); 800 801 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 802 GPHY_CFG_SEL_ANA_RESET); 803 CSR_READ_2(sc, ALC_GPHY_CFG); 804 DELAY(10 * 1000); 805 806 /* DSP fixup, Vendor magic. */ 807 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B) { 808 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 809 ALC_MII_DBG_ADDR, 0x000A); 810 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 811 ALC_MII_DBG_DATA); 812 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 813 ALC_MII_DBG_DATA, data & 0xDFFF); 814 } 815 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 816 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 817 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 818 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) { 819 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 820 ALC_MII_DBG_ADDR, 0x003B); 821 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 822 ALC_MII_DBG_DATA); 823 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 824 ALC_MII_DBG_DATA, data & 0xFFF7); 825 DELAY(20 * 1000); 826 } 827 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151) { 828 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 829 ALC_MII_DBG_ADDR, 0x0029); 830 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 831 ALC_MII_DBG_DATA, 0x929D); 832 } 833 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8131 || 834 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8132 || 835 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 836 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) { 837 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 838 ALC_MII_DBG_ADDR, 0x0029); 839 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 840 ALC_MII_DBG_DATA, 0xB6DD); 841 } 842 843 /* Load DSP codes, vendor magic. */ 844 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 845 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 846 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 847 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 848 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 849 ALC_MII_DBG_DATA, data); 850 851 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 852 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 853 ANA_SERDES_EN_LCKDT; 854 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 855 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 856 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 857 ALC_MII_DBG_DATA, data); 858 859 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 860 ANA_LONG_CABLE_TH_100_MASK) | 861 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 862 ANA_SHORT_CABLE_TH_100_SHIFT) | 863 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 864 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 865 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 866 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 867 ALC_MII_DBG_DATA, data); 868 869 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 870 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 871 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 872 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 873 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 874 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 875 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 876 ALC_MII_DBG_DATA, data); 877 878 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 879 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 880 ANA_OEN_125M; 881 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 882 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 883 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 884 ALC_MII_DBG_DATA, data); 885 DELAY(1000); 886 887 /* Disable hibernation. */ 888 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 889 0x0029); 890 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 891 ALC_MII_DBG_DATA); 892 data &= ~0x8000; 893 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 894 data); 895 896 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 897 0x000B); 898 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 899 ALC_MII_DBG_DATA); 900 data &= ~0x8000; 901 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 902 data); 903 } 904 905 static void 906 alc_phy_reset_816x(struct alc_softc *sc) 907 { 908 uint32_t val; 909 910 val = CSR_READ_4(sc, ALC_GPHY_CFG); 911 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 912 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON | 913 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB); 914 val |= GPHY_CFG_SEL_ANA_RESET; 915 #ifdef notyet 916 val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET; 917 #else 918 /* Disable PHY hibernation. */ 919 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN); 920 #endif 921 CSR_WRITE_4(sc, ALC_GPHY_CFG, val); 922 DELAY(10); 923 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); 924 DELAY(800); 925 926 /* Vendor PHY magic. */ 927 #ifdef notyet 928 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT); 929 alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT); 930 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS, 931 EXT_VDRVBIAS_DEFAULT); 932 #else 933 /* Disable PHY hibernation. */ 934 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, 935 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB); 936 alc_miidbg_writereg(sc, MII_DBG_HIBNEG, 937 DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE)); 938 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT); 939 #endif 940 941 /* XXX Disable EEE. */ 942 val = CSR_READ_4(sc, ALC_LPI_CTL); 943 val &= ~LPI_CTL_ENB; 944 CSR_WRITE_4(sc, ALC_LPI_CTL, val); 945 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0); 946 947 /* PHY power saving. */ 948 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT); 949 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT); 950 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT); 951 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT); 952 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 953 val &= ~DBG_GREENCFG2_GATE_DFSE_EN; 954 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 955 956 /* RTL8139C, 120m issue. */ 957 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78, 958 ANEG_NLP78_120M_DEFAULT); 959 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 960 ANEG_S3DIG10_DEFAULT); 961 962 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) { 963 /* Turn off half amplitude. */ 964 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3); 965 val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT; 966 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val); 967 /* Turn off Green feature. */ 968 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 969 val |= DBG_GREENCFG2_BP_GREEN; 970 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 971 /* Turn off half bias. */ 972 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5); 973 val |= EXT_CLDCTL5_BP_VD_HLFBIAS; 974 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val); 975 } 976 } 977 978 static void 979 alc_phy_down(struct alc_softc *sc) 980 { 981 uint32_t gphy; 982 983 switch (sc->alc_ident->deviceid) { 984 case PCI_PRODUCT_ATTANSIC_AR8161: 985 case PCI_PRODUCT_ATTANSIC_E2200: 986 case PCI_PRODUCT_ATTANSIC_AR8162: 987 case PCI_PRODUCT_ATTANSIC_AR8171: 988 case PCI_PRODUCT_ATTANSIC_AR8172: 989 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 990 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 991 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); 992 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 993 GPHY_CFG_SEL_ANA_RESET; 994 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 995 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 996 break; 997 case PCI_PRODUCT_ATTANSIC_AR8151: 998 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 999 case PCI_PRODUCT_ATTANSIC_AR8152_B: 1000 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 1001 /* 1002 * GPHY power down caused more problems on AR8151 v2.0. 1003 * When driver is reloaded after GPHY power down, 1004 * accesses to PHY/MAC registers hung the system. Only 1005 * cold boot recovered from it. I'm not sure whether 1006 * AR8151 v1.0 also requires this one though. I don't 1007 * have AR8151 v1.0 controller in hand. 1008 * The only option left is to isolate the PHY and 1009 * initiates power down the PHY which in turn saves 1010 * more power when driver is unloaded. 1011 */ 1012 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 1013 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 1014 break; 1015 default: 1016 /* Force PHY down. */ 1017 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 1018 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 1019 GPHY_CFG_PWDOWN_HW); 1020 DELAY(1000); 1021 break; 1022 } 1023 } 1024 1025 static void 1026 alc_aspm(struct alc_softc *sc, int init, int media) 1027 { 1028 1029 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1030 alc_aspm_816x(sc, init); 1031 else 1032 alc_aspm_813x(sc, media); 1033 } 1034 1035 static void 1036 alc_aspm_813x(struct alc_softc *sc, int media) 1037 { 1038 uint32_t pmcfg; 1039 uint16_t linkcfg; 1040 1041 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1042 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 1043 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 1044 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 1045 PCIE_LCSR); 1046 else 1047 linkcfg = 0; 1048 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 1049 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 1050 pmcfg |= PM_CFG_MAC_ASPM_CHK; 1051 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 1052 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1053 1054 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1055 /* Disable extended sync except AR8152 B v1.0 */ 1056 linkcfg &= ~0x80; 1057 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B && 1058 sc->alc_rev == ATHEROS_AR8152_B_V10) 1059 linkcfg |= 0x80; 1060 CSR_WRITE_2(sc, sc->alc_expcap + PCIE_LCSR, 1061 linkcfg); 1062 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 1063 PM_CFG_HOTRST); 1064 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 1065 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1066 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1067 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 1068 PM_CFG_PM_REQ_TIMER_SHIFT); 1069 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 1070 } 1071 1072 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1073 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 1074 pmcfg |= PM_CFG_ASPM_L0S_ENB; 1075 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1076 pmcfg |= PM_CFG_ASPM_L1_ENB; 1077 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1078 if (sc->alc_ident->deviceid == 1079 PCI_PRODUCT_ATTANSIC_AR8152_B) 1080 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 1081 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 1082 PM_CFG_SERDES_PLL_L1_ENB | 1083 PM_CFG_SERDES_BUDS_RX_L1_ENB); 1084 pmcfg |= PM_CFG_CLK_SWH_L1; 1085 if (media == IFM_100_TX || media == IFM_1000_T) { 1086 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 1087 switch (sc->alc_ident->deviceid) { 1088 case PCI_PRODUCT_ATTANSIC_AR8152_B: 1089 pmcfg |= (7 << 1090 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1091 break; 1092 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 1093 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 1094 pmcfg |= (4 << 1095 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1096 break; 1097 default: 1098 pmcfg |= (15 << 1099 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1100 break; 1101 } 1102 } 1103 } else { 1104 pmcfg |= PM_CFG_SERDES_L1_ENB | 1105 PM_CFG_SERDES_PLL_L1_ENB | 1106 PM_CFG_SERDES_BUDS_RX_L1_ENB; 1107 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 1108 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1109 } 1110 } else { 1111 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 1112 PM_CFG_SERDES_PLL_L1_ENB); 1113 pmcfg |= PM_CFG_CLK_SWH_L1; 1114 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1115 pmcfg |= PM_CFG_ASPM_L1_ENB; 1116 } 1117 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1118 } 1119 1120 static void 1121 alc_aspm_816x(struct alc_softc *sc, int init) 1122 { 1123 uint32_t pmcfg; 1124 1125 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1126 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK; 1127 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT; 1128 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1129 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT; 1130 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK; 1131 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT; 1132 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV; 1133 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S | 1134 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB | 1135 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 1136 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB | 1137 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST); 1138 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1139 (sc->alc_rev & 0x01) != 0) 1140 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB; 1141 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1142 /* Link up, enable both L0s, L1s. */ 1143 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1144 PM_CFG_MAC_ASPM_CHK; 1145 } else { 1146 if (init != 0) 1147 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1148 PM_CFG_MAC_ASPM_CHK; 1149 else if ((sc->sc_ec.ec_if.if_flags & IFF_RUNNING) != 0) 1150 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; 1151 } 1152 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1153 } 1154 1155 static void 1156 alc_attach(device_t parent, device_t self, void *aux) 1157 { 1158 1159 struct alc_softc *sc = device_private(self); 1160 struct pci_attach_args *pa = aux; 1161 pci_chipset_tag_t pc = pa->pa_pc; 1162 pci_intr_handle_t ih; 1163 const char *intrstr; 1164 struct ifnet *ifp; 1165 pcireg_t memtype; 1166 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 1167 uint16_t burst; 1168 int base, mii_flags, state, error = 0; 1169 uint32_t cap, ctl, val; 1170 char intrbuf[PCI_INTRSTR_LEN]; 1171 1172 sc->alc_ident = alc_find_ident(pa); 1173 1174 aprint_naive("\n"); 1175 aprint_normal(": %s\n", sc->alc_ident->name); 1176 1177 sc->sc_dev = self; 1178 sc->sc_dmat = pa->pa_dmat; 1179 sc->sc_pct = pa->pa_pc; 1180 sc->sc_pcitag = pa->pa_tag; 1181 1182 /* 1183 * Allocate IO memory 1184 */ 1185 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ALC_PCIR_BAR); 1186 switch (memtype) { 1187 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1188 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 1189 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1190 break; 1191 default: 1192 aprint_error_dev(self, "invalid base address register\n"); 1193 break; 1194 } 1195 1196 if (pci_mapreg_map(pa, ALC_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 1197 &sc->sc_mem_bh, NULL, &sc->sc_mem_size)) { 1198 aprint_error_dev(self, "could not map mem space\n"); 1199 return; 1200 } 1201 1202 if (pci_intr_map(pa, &ih) != 0) { 1203 printf(": can't map interrupt\n"); 1204 goto fail; 1205 } 1206 1207 /* 1208 * Allocate IRQ 1209 */ 1210 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf)); 1211 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, alc_intr, sc); 1212 if (sc->sc_irq_handle == NULL) { 1213 printf(": could not establish interrupt"); 1214 if (intrstr != NULL) 1215 printf(" at %s", intrstr); 1216 printf("\n"); 1217 goto fail; 1218 } 1219 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 1220 1221 /* Set PHY address. */ 1222 sc->alc_phyaddr = ALC_PHY_ADDR; 1223 1224 /* Initialize DMA parameters. */ 1225 sc->alc_dma_rd_burst = 0; 1226 sc->alc_dma_wr_burst = 0; 1227 sc->alc_rcb = DMA_CFG_RCB_64; 1228 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 1229 &base, NULL)) { 1230 sc->alc_flags |= ALC_FLAG_PCIE; 1231 sc->alc_expcap = base; 1232 burst = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1233 base + PCIE_DCSR) >> 16; 1234 sc->alc_dma_rd_burst = (burst & 0x7000) >> 12; 1235 sc->alc_dma_wr_burst = (burst & 0x00e0) >> 5; 1236 if (alcdebug) { 1237 printf("%s: Read request size : %u bytes.\n", 1238 device_xname(sc->sc_dev), 1239 alc_dma_burst[sc->alc_dma_rd_burst]); 1240 printf("%s: TLP payload size : %u bytes.\n", 1241 device_xname(sc->sc_dev), 1242 alc_dma_burst[sc->alc_dma_wr_burst]); 1243 } 1244 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 1245 sc->alc_dma_rd_burst = 3; 1246 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 1247 sc->alc_dma_wr_burst = 3; 1248 1249 /* Clear data link and flow-control protocol error. */ 1250 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 1251 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 1252 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 1253 1254 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1255 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 1256 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 1257 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 1258 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 1259 PCIE_PHYMISC_FORCE_RCV_DET); 1260 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B && 1261 sc->alc_rev == ATHEROS_AR8152_B_V10) { 1262 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 1263 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 1264 PCIE_PHYMISC2_SERDES_TH_MASK); 1265 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 1266 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 1267 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 1268 } 1269 /* Disable ASPM L0S and L1. */ 1270 cap = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1271 base + PCIE_LCAP) >> 16; 1272 if ((cap & 0x00000c00) != 0) { 1273 ctl = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1274 base + PCIE_LCSR) >> 16; 1275 if ((ctl & 0x08) != 0) 1276 sc->alc_rcb = DMA_CFG_RCB_128; 1277 if (alcdebug) 1278 printf("%s: RCB %u bytes\n", 1279 device_xname(sc->sc_dev), 1280 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 1281 state = ctl & 0x03; 1282 if (state & 0x01) 1283 sc->alc_flags |= ALC_FLAG_L0S; 1284 if (state & 0x02) 1285 sc->alc_flags |= ALC_FLAG_L1S; 1286 if (alcdebug) 1287 printf("%s: ASPM %s %s\n", 1288 device_xname(sc->sc_dev), 1289 aspm_state[state], 1290 state == 0 ? "disabled" : "enabled"); 1291 alc_disable_l0s_l1(sc); 1292 } else { 1293 aprint_debug_dev(sc->sc_dev, "no ASPM support\n"); 1294 } 1295 } else { 1296 val = CSR_READ_4(sc, ALC_PDLL_TRNS1); 1297 val &= ~PDLL_TRNS1_D3PLLOFF_ENB; 1298 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); 1299 val = CSR_READ_4(sc, ALC_MASTER_CFG); 1300 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1301 (sc->alc_rev & 0x01) != 0) { 1302 if ((val & MASTER_WAKEN_25M) == 0 || 1303 (val & MASTER_CLK_SEL_DIS) == 0) { 1304 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS; 1305 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1306 } 1307 } else { 1308 if ((val & MASTER_WAKEN_25M) == 0 || 1309 (val & MASTER_CLK_SEL_DIS) != 0) { 1310 val |= MASTER_WAKEN_25M; 1311 val &= ~MASTER_CLK_SEL_DIS; 1312 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1313 } 1314 } 1315 } 1316 alc_aspm(sc, 1, IFM_UNKNOWN); 1317 } 1318 1319 /* Reset PHY. */ 1320 alc_phy_reset(sc); 1321 1322 /* Reset the ethernet controller. */ 1323 alc_stop_mac(sc); 1324 alc_reset(sc); 1325 1326 /* 1327 * One odd thing is AR8132 uses the same PHY hardware(F1 1328 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 1329 * the PHY supports 1000Mbps but that's not true. The PHY 1330 * used in AR8132 can't establish gigabit link even if it 1331 * shows the same PHY model/revision number of AR8131. 1332 */ 1333 switch (sc->alc_ident->deviceid) { 1334 case PCI_PRODUCT_ATTANSIC_AR8161: 1335 if (PCI_SUBSYS_ID(pci_conf_read( 1336 sc->sc_pct, sc->sc_pcitag, PCI_SUBSYS_ID_REG)) == 0x0091 && 1337 sc->alc_rev == 0) 1338 sc->alc_flags |= ALC_FLAG_LINK_WAR; 1339 /* FALLTHROUGH */ 1340 case PCI_PRODUCT_ATTANSIC_E2200: 1341 case PCI_PRODUCT_ATTANSIC_AR8171: 1342 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY; 1343 break; 1344 case PCI_PRODUCT_ATTANSIC_AR8162: 1345 case PCI_PRODUCT_ATTANSIC_AR8172: 1346 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY; 1347 break; 1348 case PCI_PRODUCT_ATTANSIC_AR8152_B: 1349 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 1350 sc->alc_flags |= ALC_FLAG_APS; 1351 /* FALLTHROUGH */ 1352 case PCI_PRODUCT_ATTANSIC_AR8132: 1353 sc->alc_flags |= ALC_FLAG_FASTETHER; 1354 break; 1355 case PCI_PRODUCT_ATTANSIC_AR8151: 1356 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 1357 sc->alc_flags |= ALC_FLAG_APS; 1358 /* FALLTHROUGH */ 1359 default: 1360 break; 1361 } 1362 sc->alc_flags |= ALC_FLAG_JUMBO; 1363 1364 /* 1365 * It seems that AR813x/AR815x has silicon bug for SMB. In 1366 * addition, Atheros said that enabling SMB wouldn't improve 1367 * performance. However I think it's bad to access lots of 1368 * registers to extract MAC statistics. 1369 */ 1370 sc->alc_flags |= ALC_FLAG_SMB_BUG; 1371 /* 1372 * Don't use Tx CMB. It is known to have silicon bug. 1373 */ 1374 sc->alc_flags |= ALC_FLAG_CMB_BUG; 1375 sc->alc_rev = PCI_REVISION(pa->pa_class); 1376 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 1377 MASTER_CHIP_REV_SHIFT; 1378 if (alcdebug) { 1379 printf("%s: PCI device revision : 0x%04x\n", 1380 device_xname(sc->sc_dev), sc->alc_rev); 1381 printf("%s: Chip id/revision : 0x%04x\n", 1382 device_xname(sc->sc_dev), sc->alc_chip_rev); 1383 printf("%s: %u Tx FIFO, %u Rx FIFO\n", device_xname(sc->sc_dev), 1384 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 1385 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 1386 } 1387 1388 error = alc_dma_alloc(sc); 1389 if (error) 1390 goto fail; 1391 1392 callout_init(&sc->sc_tick_ch, 0); 1393 callout_setfunc(&sc->sc_tick_ch, alc_tick, sc); 1394 1395 /* Load station address. */ 1396 alc_get_macaddr(sc); 1397 1398 aprint_normal_dev(self, "Ethernet address %s\n", 1399 ether_sprintf(sc->alc_eaddr)); 1400 1401 ifp = &sc->sc_ec.ec_if; 1402 ifp->if_softc = sc; 1403 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1404 ifp->if_init = alc_init; 1405 ifp->if_ioctl = alc_ioctl; 1406 ifp->if_start = alc_start; 1407 ifp->if_stop = alc_stop; 1408 ifp->if_watchdog = alc_watchdog; 1409 ifp->if_baudrate = IF_Gbps(1); 1410 IFQ_SET_MAXLEN(&ifp->if_snd, ALC_TX_RING_CNT - 1); 1411 IFQ_SET_READY(&ifp->if_snd); 1412 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1413 1414 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 1415 1416 #ifdef ALC_CHECKSUM 1417 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1418 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1419 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 1420 #endif 1421 1422 #if NVLAN > 0 1423 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 1424 #endif 1425 1426 /* 1427 * XXX 1428 * It seems enabling Tx checksum offloading makes more trouble. 1429 * Sometimes the controller does not receive any frames when 1430 * Tx checksum offloading is enabled. I'm not sure whether this 1431 * is a bug in Tx checksum offloading logic or I got broken 1432 * sample boards. To safety, don't enable Tx checksum offloading 1433 * by default but give chance to users to toggle it if they know 1434 * their controllers work without problems. 1435 * Fortunately, Tx checksum offloading for AR816x family 1436 * seems to work. 1437 */ 1438 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1439 ifp->if_capenable &= ~IFCAP_CSUM_IPv4_Tx; 1440 ifp->if_capabilities &= ~ALC_CSUM_FEATURES; 1441 } 1442 1443 /* Set up MII bus. */ 1444 sc->sc_miibus.mii_ifp = ifp; 1445 sc->sc_miibus.mii_readreg = alc_miibus_readreg; 1446 sc->sc_miibus.mii_writereg = alc_miibus_writereg; 1447 sc->sc_miibus.mii_statchg = alc_miibus_statchg; 1448 1449 sc->sc_ec.ec_mii = &sc->sc_miibus; 1450 ifmedia_init(&sc->sc_miibus.mii_media, 0, alc_mediachange, 1451 alc_mediastatus); 1452 mii_flags = 0; 1453 if ((sc->alc_flags & ALC_FLAG_JUMBO) != 0) 1454 mii_flags |= MIIF_DOPAUSE; 1455 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 1456 MII_OFFSET_ANY, mii_flags); 1457 1458 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 1459 printf("%s: no PHY found!\n", device_xname(sc->sc_dev)); 1460 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 1461 0, NULL); 1462 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 1463 } else 1464 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 1465 1466 if_attach(ifp); 1467 ether_ifattach(ifp, sc->alc_eaddr); 1468 1469 if (!pmf_device_register(self, NULL, NULL)) 1470 aprint_error_dev(self, "couldn't establish power handler\n"); 1471 else 1472 pmf_class_network_register(self, ifp); 1473 1474 return; 1475 fail: 1476 alc_dma_free(sc); 1477 if (sc->sc_irq_handle != NULL) { 1478 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 1479 sc->sc_irq_handle = NULL; 1480 } 1481 if (sc->sc_mem_size) { 1482 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 1483 sc->sc_mem_size = 0; 1484 } 1485 } 1486 1487 static int 1488 alc_detach(device_t self, int flags) 1489 { 1490 struct alc_softc *sc = device_private(self); 1491 struct ifnet *ifp = &sc->sc_ec.ec_if; 1492 int s; 1493 1494 s = splnet(); 1495 alc_stop(ifp, 0); 1496 splx(s); 1497 1498 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 1499 1500 /* Delete all remaining media. */ 1501 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 1502 1503 ether_ifdetach(ifp); 1504 if_detach(ifp); 1505 alc_dma_free(sc); 1506 1507 alc_phy_down(sc); 1508 if (sc->sc_irq_handle != NULL) { 1509 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 1510 sc->sc_irq_handle = NULL; 1511 } 1512 if (sc->sc_mem_size) { 1513 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 1514 sc->sc_mem_size = 0; 1515 } 1516 1517 return (0); 1518 } 1519 1520 static int 1521 alc_dma_alloc(struct alc_softc *sc) 1522 { 1523 struct alc_txdesc *txd; 1524 struct alc_rxdesc *rxd; 1525 int nsegs, error, i; 1526 1527 /* 1528 * Create DMA stuffs for TX ring 1529 */ 1530 error = bus_dmamap_create(sc->sc_dmat, ALC_TX_RING_SZ, 1, 1531 ALC_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_tx_ring_map); 1532 if (error) { 1533 sc->alc_cdata.alc_tx_ring_map = NULL; 1534 return (ENOBUFS); 1535 } 1536 1537 /* Allocate DMA'able memory for TX ring */ 1538 error = bus_dmamem_alloc(sc->sc_dmat, ALC_TX_RING_SZ, 1539 ETHER_ALIGN, 0, &sc->alc_rdata.alc_tx_ring_seg, 1, 1540 &nsegs, BUS_DMA_NOWAIT); 1541 if (error) { 1542 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 1543 device_xname(sc->sc_dev)); 1544 return error; 1545 } 1546 1547 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_tx_ring_seg, 1548 nsegs, ALC_TX_RING_SZ, (void **)&sc->alc_rdata.alc_tx_ring, 1549 BUS_DMA_NOWAIT); 1550 if (error) 1551 return (ENOBUFS); 1552 1553 /* Load the DMA map for Tx ring. */ 1554 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 1555 sc->alc_rdata.alc_tx_ring, ALC_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 1556 if (error) { 1557 printf("%s: could not load DMA'able memory for Tx ring.\n", 1558 device_xname(sc->sc_dev)); 1559 bus_dmamem_free(sc->sc_dmat, 1560 &sc->alc_rdata.alc_tx_ring_seg, 1); 1561 return error; 1562 } 1563 1564 sc->alc_rdata.alc_tx_ring_paddr = 1565 sc->alc_cdata.alc_tx_ring_map->dm_segs[0].ds_addr; 1566 1567 /* 1568 * Create DMA stuffs for RX ring 1569 */ 1570 error = bus_dmamap_create(sc->sc_dmat, ALC_RX_RING_SZ, 1, 1571 ALC_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_ring_map); 1572 if (error) 1573 return (ENOBUFS); 1574 1575 /* Allocate DMA'able memory for RX ring */ 1576 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RX_RING_SZ, 1577 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rx_ring_seg, 1, 1578 &nsegs, BUS_DMA_NOWAIT); 1579 if (error) { 1580 printf("%s: could not allocate DMA'able memory for Rx ring.\n", 1581 device_xname(sc->sc_dev)); 1582 return error; 1583 } 1584 1585 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rx_ring_seg, 1586 nsegs, ALC_RX_RING_SZ, (void **)&sc->alc_rdata.alc_rx_ring, 1587 BUS_DMA_NOWAIT); 1588 if (error) 1589 return (ENOBUFS); 1590 1591 /* Load the DMA map for Rx ring. */ 1592 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 1593 sc->alc_rdata.alc_rx_ring, ALC_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 1594 if (error) { 1595 printf("%s: could not load DMA'able memory for Rx ring.\n", 1596 device_xname(sc->sc_dev)); 1597 bus_dmamem_free(sc->sc_dmat, 1598 &sc->alc_rdata.alc_rx_ring_seg, 1); 1599 return error; 1600 } 1601 1602 sc->alc_rdata.alc_rx_ring_paddr = 1603 sc->alc_cdata.alc_rx_ring_map->dm_segs[0].ds_addr; 1604 1605 /* 1606 * Create DMA stuffs for RX return ring 1607 */ 1608 error = bus_dmamap_create(sc->sc_dmat, ALC_RR_RING_SZ, 1, 1609 ALC_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rr_ring_map); 1610 if (error) 1611 return (ENOBUFS); 1612 1613 /* Allocate DMA'able memory for RX return ring */ 1614 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RR_RING_SZ, 1615 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rr_ring_seg, 1, 1616 &nsegs, BUS_DMA_NOWAIT); 1617 if (error) { 1618 printf("%s: could not allocate DMA'able memory for Rx " 1619 "return ring.\n", device_xname(sc->sc_dev)); 1620 return error; 1621 } 1622 1623 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rr_ring_seg, 1624 nsegs, ALC_RR_RING_SZ, (void **)&sc->alc_rdata.alc_rr_ring, 1625 BUS_DMA_NOWAIT); 1626 if (error) 1627 return (ENOBUFS); 1628 1629 /* Load the DMA map for Rx return ring. */ 1630 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 1631 sc->alc_rdata.alc_rr_ring, ALC_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 1632 if (error) { 1633 printf("%s: could not load DMA'able memory for Rx return ring." 1634 "\n", device_xname(sc->sc_dev)); 1635 bus_dmamem_free(sc->sc_dmat, 1636 &sc->alc_rdata.alc_rr_ring_seg, 1); 1637 return error; 1638 } 1639 1640 sc->alc_rdata.alc_rr_ring_paddr = 1641 sc->alc_cdata.alc_rr_ring_map->dm_segs[0].ds_addr; 1642 1643 /* 1644 * Create DMA stuffs for CMB block 1645 */ 1646 error = bus_dmamap_create(sc->sc_dmat, ALC_CMB_SZ, 1, 1647 ALC_CMB_SZ, 0, BUS_DMA_NOWAIT, 1648 &sc->alc_cdata.alc_cmb_map); 1649 if (error) 1650 return (ENOBUFS); 1651 1652 /* Allocate DMA'able memory for CMB block */ 1653 error = bus_dmamem_alloc(sc->sc_dmat, ALC_CMB_SZ, 1654 ETHER_ALIGN, 0, &sc->alc_rdata.alc_cmb_seg, 1, 1655 &nsegs, BUS_DMA_NOWAIT); 1656 if (error) { 1657 printf("%s: could not allocate DMA'able memory for " 1658 "CMB block\n", device_xname(sc->sc_dev)); 1659 return error; 1660 } 1661 1662 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_cmb_seg, 1663 nsegs, ALC_CMB_SZ, (void **)&sc->alc_rdata.alc_cmb, 1664 BUS_DMA_NOWAIT); 1665 if (error) 1666 return (ENOBUFS); 1667 1668 /* Load the DMA map for CMB block. */ 1669 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 1670 sc->alc_rdata.alc_cmb, ALC_CMB_SZ, NULL, 1671 BUS_DMA_WAITOK); 1672 if (error) { 1673 printf("%s: could not load DMA'able memory for CMB block\n", 1674 device_xname(sc->sc_dev)); 1675 bus_dmamem_free(sc->sc_dmat, 1676 &sc->alc_rdata.alc_cmb_seg, 1); 1677 return error; 1678 } 1679 1680 sc->alc_rdata.alc_cmb_paddr = 1681 sc->alc_cdata.alc_cmb_map->dm_segs[0].ds_addr; 1682 1683 /* 1684 * Create DMA stuffs for SMB block 1685 */ 1686 error = bus_dmamap_create(sc->sc_dmat, ALC_SMB_SZ, 1, 1687 ALC_SMB_SZ, 0, BUS_DMA_NOWAIT, 1688 &sc->alc_cdata.alc_smb_map); 1689 if (error) 1690 return (ENOBUFS); 1691 1692 /* Allocate DMA'able memory for SMB block */ 1693 error = bus_dmamem_alloc(sc->sc_dmat, ALC_SMB_SZ, 1694 ETHER_ALIGN, 0, &sc->alc_rdata.alc_smb_seg, 1, 1695 &nsegs, BUS_DMA_NOWAIT); 1696 if (error) { 1697 printf("%s: could not allocate DMA'able memory for " 1698 "SMB block\n", device_xname(sc->sc_dev)); 1699 return error; 1700 } 1701 1702 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_smb_seg, 1703 nsegs, ALC_SMB_SZ, (void **)&sc->alc_rdata.alc_smb, 1704 BUS_DMA_NOWAIT); 1705 if (error) 1706 return (ENOBUFS); 1707 1708 /* Load the DMA map for SMB block */ 1709 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 1710 sc->alc_rdata.alc_smb, ALC_SMB_SZ, NULL, 1711 BUS_DMA_WAITOK); 1712 if (error) { 1713 printf("%s: could not load DMA'able memory for SMB block\n", 1714 device_xname(sc->sc_dev)); 1715 bus_dmamem_free(sc->sc_dmat, 1716 &sc->alc_rdata.alc_smb_seg, 1); 1717 return error; 1718 } 1719 1720 sc->alc_rdata.alc_smb_paddr = 1721 sc->alc_cdata.alc_smb_map->dm_segs[0].ds_addr; 1722 1723 1724 /* Create DMA maps for Tx buffers. */ 1725 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1726 txd = &sc->alc_cdata.alc_txdesc[i]; 1727 txd->tx_m = NULL; 1728 txd->tx_dmamap = NULL; 1729 error = bus_dmamap_create(sc->sc_dmat, ALC_TSO_MAXSIZE, 1730 ALC_MAXTXSEGS, ALC_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 1731 &txd->tx_dmamap); 1732 if (error) { 1733 printf("%s: could not create Tx dmamap.\n", 1734 device_xname(sc->sc_dev)); 1735 return error; 1736 } 1737 } 1738 1739 /* Create DMA maps for Rx buffers. */ 1740 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 1741 BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_sparemap); 1742 if (error) { 1743 printf("%s: could not create spare Rx dmamap.\n", 1744 device_xname(sc->sc_dev)); 1745 return error; 1746 } 1747 1748 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1749 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1750 rxd->rx_m = NULL; 1751 rxd->rx_dmamap = NULL; 1752 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1753 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 1754 if (error) { 1755 printf("%s: could not create Rx dmamap.\n", 1756 device_xname(sc->sc_dev)); 1757 return error; 1758 } 1759 } 1760 1761 return (0); 1762 } 1763 1764 1765 static void 1766 alc_dma_free(struct alc_softc *sc) 1767 { 1768 struct alc_txdesc *txd; 1769 struct alc_rxdesc *rxd; 1770 int i; 1771 1772 /* Tx buffers */ 1773 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1774 txd = &sc->alc_cdata.alc_txdesc[i]; 1775 if (txd->tx_dmamap != NULL) { 1776 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 1777 txd->tx_dmamap = NULL; 1778 } 1779 } 1780 /* Rx buffers */ 1781 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1782 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1783 if (rxd->rx_dmamap != NULL) { 1784 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 1785 rxd->rx_dmamap = NULL; 1786 } 1787 } 1788 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1789 bus_dmamap_destroy(sc->sc_dmat, sc->alc_cdata.alc_rx_sparemap); 1790 sc->alc_cdata.alc_rx_sparemap = NULL; 1791 } 1792 1793 /* Tx ring. */ 1794 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1795 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map); 1796 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1797 sc->alc_rdata.alc_tx_ring != NULL) 1798 bus_dmamem_free(sc->sc_dmat, 1799 &sc->alc_rdata.alc_tx_ring_seg, 1); 1800 sc->alc_rdata.alc_tx_ring = NULL; 1801 sc->alc_cdata.alc_tx_ring_map = NULL; 1802 1803 /* Rx ring. */ 1804 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1805 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map); 1806 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1807 sc->alc_rdata.alc_rx_ring != NULL) 1808 bus_dmamem_free(sc->sc_dmat, 1809 &sc->alc_rdata.alc_rx_ring_seg, 1); 1810 sc->alc_rdata.alc_rx_ring = NULL; 1811 sc->alc_cdata.alc_rx_ring_map = NULL; 1812 1813 /* Rx return ring. */ 1814 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1815 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map); 1816 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1817 sc->alc_rdata.alc_rr_ring != NULL) 1818 bus_dmamem_free(sc->sc_dmat, 1819 &sc->alc_rdata.alc_rr_ring_seg, 1); 1820 sc->alc_rdata.alc_rr_ring = NULL; 1821 sc->alc_cdata.alc_rr_ring_map = NULL; 1822 1823 /* CMB block */ 1824 if (sc->alc_cdata.alc_cmb_map != NULL) 1825 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_cmb_map); 1826 if (sc->alc_cdata.alc_cmb_map != NULL && 1827 sc->alc_rdata.alc_cmb != NULL) 1828 bus_dmamem_free(sc->sc_dmat, 1829 &sc->alc_rdata.alc_cmb_seg, 1); 1830 sc->alc_rdata.alc_cmb = NULL; 1831 sc->alc_cdata.alc_cmb_map = NULL; 1832 1833 /* SMB block */ 1834 if (sc->alc_cdata.alc_smb_map != NULL) 1835 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_smb_map); 1836 if (sc->alc_cdata.alc_smb_map != NULL && 1837 sc->alc_rdata.alc_smb != NULL) 1838 bus_dmamem_free(sc->sc_dmat, 1839 &sc->alc_rdata.alc_smb_seg, 1); 1840 sc->alc_rdata.alc_smb = NULL; 1841 sc->alc_cdata.alc_smb_map = NULL; 1842 } 1843 1844 static int 1845 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 1846 { 1847 struct alc_txdesc *txd, *txd_last; 1848 struct tx_desc *desc; 1849 struct mbuf *m; 1850 bus_dmamap_t map; 1851 uint32_t cflags, poff, vtag; 1852 int error, idx, nsegs, prod; 1853 #if NVLAN > 0 1854 struct m_tag *mtag; 1855 #endif 1856 1857 m = *m_head; 1858 cflags = vtag = 0; 1859 poff = 0; 1860 1861 prod = sc->alc_cdata.alc_tx_prod; 1862 txd = &sc->alc_cdata.alc_txdesc[prod]; 1863 txd_last = txd; 1864 map = txd->tx_dmamap; 1865 1866 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1867 1868 if (error == EFBIG) { 1869 error = 0; 1870 1871 *m_head = m_pullup(*m_head, MHLEN); 1872 if (*m_head == NULL) { 1873 printf("%s: can't defrag TX mbuf\n", 1874 device_xname(sc->sc_dev)); 1875 return ENOBUFS; 1876 } 1877 1878 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1879 BUS_DMA_NOWAIT); 1880 1881 if (error != 0) { 1882 printf("%s: could not load defragged TX mbuf\n", 1883 device_xname(sc->sc_dev)); 1884 m_freem(*m_head); 1885 *m_head = NULL; 1886 return error; 1887 } 1888 } else if (error) { 1889 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 1890 return (error); 1891 } 1892 1893 nsegs = map->dm_nsegs; 1894 1895 if (nsegs == 0) { 1896 m_freem(*m_head); 1897 *m_head = NULL; 1898 return (EIO); 1899 } 1900 1901 /* Check descriptor overrun. */ 1902 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 1903 bus_dmamap_unload(sc->sc_dmat, map); 1904 return (ENOBUFS); 1905 } 1906 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1907 BUS_DMASYNC_PREWRITE); 1908 1909 m = *m_head; 1910 desc = NULL; 1911 idx = 0; 1912 #if NVLAN > 0 1913 /* Configure VLAN hardware tag insertion. */ 1914 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m))) { 1915 vtag = htons(VLAN_TAG_VALUE(mtag)); 1916 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 1917 cflags |= TD_INS_VLAN_TAG; 1918 } 1919 #endif 1920 /* Configure Tx checksum offload. */ 1921 if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 1922 cflags |= TD_CUSTOM_CSUM; 1923 /* Set checksum start offset. */ 1924 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 1925 TD_PLOAD_OFFSET_MASK; 1926 } 1927 for (; idx < nsegs; idx++) { 1928 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1929 desc->len = 1930 htole32(TX_BYTES(map->dm_segs[idx].ds_len) | vtag); 1931 desc->flags = htole32(cflags); 1932 desc->addr = htole64(map->dm_segs[idx].ds_addr); 1933 sc->alc_cdata.alc_tx_cnt++; 1934 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 1935 } 1936 /* Update producer index. */ 1937 sc->alc_cdata.alc_tx_prod = prod; 1938 1939 /* Finally set EOP on the last descriptor. */ 1940 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 1941 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1942 desc->flags |= htole32(TD_EOP); 1943 1944 /* Swap dmamap of the first and the last. */ 1945 txd = &sc->alc_cdata.alc_txdesc[prod]; 1946 map = txd_last->tx_dmamap; 1947 txd_last->tx_dmamap = txd->tx_dmamap; 1948 txd->tx_dmamap = map; 1949 txd->tx_m = m; 1950 1951 return (0); 1952 } 1953 1954 static void 1955 alc_start(struct ifnet *ifp) 1956 { 1957 struct alc_softc *sc = ifp->if_softc; 1958 struct mbuf *m_head; 1959 int enq; 1960 1961 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1962 return; 1963 1964 /* Reclaim transmitted frames. */ 1965 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 1966 alc_txeof(sc); 1967 1968 enq = 0; 1969 for (;;) { 1970 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1971 if (m_head == NULL) 1972 break; 1973 1974 /* 1975 * Pack the data into the transmit ring. If we 1976 * don't have room, set the OACTIVE flag and wait 1977 * for the NIC to drain the ring. 1978 */ 1979 if (alc_encap(sc, &m_head)) { 1980 if (m_head == NULL) 1981 break; 1982 ifp->if_flags |= IFF_OACTIVE; 1983 break; 1984 } 1985 enq = 1; 1986 1987 /* 1988 * If there's a BPF listener, bounce a copy of this frame 1989 * to him. 1990 */ 1991 bpf_mtap(ifp, m_head); 1992 } 1993 1994 if (enq) { 1995 /* Sync descriptors. */ 1996 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 1997 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 1998 BUS_DMASYNC_PREWRITE); 1999 /* Kick. Assume we're using normal Tx priority queue. */ 2000 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 2001 (sc->alc_cdata.alc_tx_prod << 2002 MBOX_TD_PROD_LO_IDX_SHIFT) & 2003 MBOX_TD_PROD_LO_IDX_MASK); 2004 /* Set a timeout in case the chip goes out to lunch. */ 2005 ifp->if_timer = ALC_TX_TIMEOUT; 2006 } 2007 } 2008 2009 static void 2010 alc_watchdog(struct ifnet *ifp) 2011 { 2012 struct alc_softc *sc = ifp->if_softc; 2013 2014 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 2015 printf("%s: watchdog timeout (missed link)\n", 2016 device_xname(sc->sc_dev)); 2017 ifp->if_oerrors++; 2018 alc_init_backend(ifp, false); 2019 return; 2020 } 2021 2022 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 2023 ifp->if_oerrors++; 2024 alc_init_backend(ifp, false); 2025 2026 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2027 alc_start(ifp); 2028 } 2029 2030 static int 2031 alc_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2032 { 2033 struct alc_softc *sc = ifp->if_softc; 2034 int s, error = 0; 2035 2036 s = splnet(); 2037 2038 error = ether_ioctl(ifp, cmd, data); 2039 if (error == ENETRESET) { 2040 if (ifp->if_flags & IFF_RUNNING) 2041 alc_iff(sc); 2042 error = 0; 2043 } 2044 2045 splx(s); 2046 return (error); 2047 } 2048 2049 static void 2050 alc_mac_config(struct alc_softc *sc) 2051 { 2052 struct mii_data *mii; 2053 uint32_t reg; 2054 2055 mii = &sc->sc_miibus; 2056 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2057 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2058 MAC_CFG_SPEED_MASK); 2059 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 2060 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 2061 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 2062 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 2063 /* Reprogram MAC with resolved speed/duplex. */ 2064 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2065 case IFM_10_T: 2066 case IFM_100_TX: 2067 reg |= MAC_CFG_SPEED_10_100; 2068 break; 2069 case IFM_1000_T: 2070 reg |= MAC_CFG_SPEED_1000; 2071 break; 2072 } 2073 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2074 reg |= MAC_CFG_FULL_DUPLEX; 2075 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2076 reg |= MAC_CFG_TX_FC; 2077 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2078 reg |= MAC_CFG_RX_FC; 2079 } 2080 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2081 } 2082 2083 static void 2084 alc_stats_clear(struct alc_softc *sc) 2085 { 2086 struct smb sb, *smb; 2087 uint32_t *reg; 2088 int i; 2089 2090 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2091 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2092 sc->alc_cdata.alc_smb_map->dm_mapsize, 2093 BUS_DMASYNC_POSTREAD); 2094 smb = sc->alc_rdata.alc_smb; 2095 /* Update done, clear. */ 2096 smb->updated = 0; 2097 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2098 sc->alc_cdata.alc_smb_map->dm_mapsize, 2099 BUS_DMASYNC_PREWRITE); 2100 } else { 2101 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2102 reg++) { 2103 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2104 i += sizeof(uint32_t); 2105 } 2106 /* Read Tx statistics. */ 2107 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2108 reg++) { 2109 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2110 i += sizeof(uint32_t); 2111 } 2112 } 2113 } 2114 2115 static void 2116 alc_stats_update(struct alc_softc *sc) 2117 { 2118 struct ifnet *ifp = &sc->sc_ec.ec_if; 2119 struct alc_hw_stats *stat; 2120 struct smb sb, *smb; 2121 uint32_t *reg; 2122 int i; 2123 2124 stat = &sc->alc_stats; 2125 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2126 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2127 sc->alc_cdata.alc_smb_map->dm_mapsize, 2128 BUS_DMASYNC_POSTREAD); 2129 smb = sc->alc_rdata.alc_smb; 2130 if (smb->updated == 0) 2131 return; 2132 } else { 2133 smb = &sb; 2134 /* Read Rx statistics. */ 2135 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2136 reg++) { 2137 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2138 i += sizeof(uint32_t); 2139 } 2140 /* Read Tx statistics. */ 2141 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2142 reg++) { 2143 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2144 i += sizeof(uint32_t); 2145 } 2146 } 2147 2148 /* Rx stats. */ 2149 stat->rx_frames += smb->rx_frames; 2150 stat->rx_bcast_frames += smb->rx_bcast_frames; 2151 stat->rx_mcast_frames += smb->rx_mcast_frames; 2152 stat->rx_pause_frames += smb->rx_pause_frames; 2153 stat->rx_control_frames += smb->rx_control_frames; 2154 stat->rx_crcerrs += smb->rx_crcerrs; 2155 stat->rx_lenerrs += smb->rx_lenerrs; 2156 stat->rx_bytes += smb->rx_bytes; 2157 stat->rx_runts += smb->rx_runts; 2158 stat->rx_fragments += smb->rx_fragments; 2159 stat->rx_pkts_64 += smb->rx_pkts_64; 2160 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2161 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2162 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2163 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2164 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2165 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2166 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2167 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2168 stat->rx_rrs_errs += smb->rx_rrs_errs; 2169 stat->rx_alignerrs += smb->rx_alignerrs; 2170 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2171 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2172 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2173 2174 /* Tx stats. */ 2175 stat->tx_frames += smb->tx_frames; 2176 stat->tx_bcast_frames += smb->tx_bcast_frames; 2177 stat->tx_mcast_frames += smb->tx_mcast_frames; 2178 stat->tx_pause_frames += smb->tx_pause_frames; 2179 stat->tx_excess_defer += smb->tx_excess_defer; 2180 stat->tx_control_frames += smb->tx_control_frames; 2181 stat->tx_deferred += smb->tx_deferred; 2182 stat->tx_bytes += smb->tx_bytes; 2183 stat->tx_pkts_64 += smb->tx_pkts_64; 2184 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2185 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2186 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2187 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2188 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2189 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2190 stat->tx_single_colls += smb->tx_single_colls; 2191 stat->tx_multi_colls += smb->tx_multi_colls; 2192 stat->tx_late_colls += smb->tx_late_colls; 2193 stat->tx_excess_colls += smb->tx_excess_colls; 2194 stat->tx_abort += smb->tx_abort; 2195 stat->tx_underrun += smb->tx_underrun; 2196 stat->tx_desc_underrun += smb->tx_desc_underrun; 2197 stat->tx_lenerrs += smb->tx_lenerrs; 2198 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2199 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2200 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2201 2202 /* Update counters in ifnet. */ 2203 ifp->if_opackets += smb->tx_frames; 2204 2205 ifp->if_collisions += smb->tx_single_colls + 2206 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2207 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 2208 2209 /* 2210 * XXX 2211 * tx_pkts_truncated counter looks suspicious. It constantly 2212 * increments with no sign of Tx errors. This may indicate 2213 * the counter name is not correct one so I've removed the 2214 * counter in output errors. 2215 */ 2216 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 2217 smb->tx_underrun; 2218 2219 ifp->if_ipackets += smb->rx_frames; 2220 2221 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2222 smb->rx_runts + smb->rx_pkts_truncated + 2223 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2224 smb->rx_alignerrs; 2225 2226 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2227 /* Update done, clear. */ 2228 smb->updated = 0; 2229 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2230 sc->alc_cdata.alc_smb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2231 } 2232 } 2233 2234 static int 2235 alc_intr(void *arg) 2236 { 2237 struct alc_softc *sc = arg; 2238 struct ifnet *ifp = &sc->sc_ec.ec_if; 2239 uint32_t status; 2240 2241 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2242 if ((status & ALC_INTRS) == 0) 2243 return (0); 2244 2245 /* Acknowledge and disable interrupts. */ 2246 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 2247 2248 if (ifp->if_flags & IFF_RUNNING) { 2249 if (status & INTR_RX_PKT) { 2250 int error; 2251 2252 error = alc_rxintr(sc); 2253 if (error) { 2254 alc_init_backend(ifp, false); 2255 return (0); 2256 } 2257 } 2258 2259 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 2260 INTR_TXQ_TO_RST)) { 2261 if (status & INTR_DMA_RD_TO_RST) 2262 printf("%s: DMA read error! -- resetting\n", 2263 device_xname(sc->sc_dev)); 2264 if (status & INTR_DMA_WR_TO_RST) 2265 printf("%s: DMA write error! -- resetting\n", 2266 device_xname(sc->sc_dev)); 2267 if (status & INTR_TXQ_TO_RST) 2268 printf("%s: TxQ reset! -- resetting\n", 2269 device_xname(sc->sc_dev)); 2270 alc_init_backend(ifp, false); 2271 return (0); 2272 } 2273 2274 alc_txeof(sc); 2275 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2276 alc_start(ifp); 2277 } 2278 2279 /* Re-enable interrupts. */ 2280 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 2281 return (1); 2282 } 2283 2284 static void 2285 alc_txeof(struct alc_softc *sc) 2286 { 2287 struct ifnet *ifp = &sc->sc_ec.ec_if; 2288 struct alc_txdesc *txd; 2289 uint32_t cons, prod; 2290 int prog; 2291 2292 if (sc->alc_cdata.alc_tx_cnt == 0) 2293 return; 2294 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 2295 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 2296 BUS_DMASYNC_POSTREAD); 2297 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2298 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2299 sc->alc_cdata.alc_cmb_map->dm_mapsize, 2300 BUS_DMASYNC_POSTREAD); 2301 prod = sc->alc_rdata.alc_cmb->cons; 2302 } else 2303 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 2304 /* Assume we're using normal Tx priority queue. */ 2305 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 2306 MBOX_TD_CONS_LO_IDX_SHIFT; 2307 cons = sc->alc_cdata.alc_tx_cons; 2308 /* 2309 * Go through our Tx list and free mbufs for those 2310 * frames which have been transmitted. 2311 */ 2312 for (prog = 0; cons != prod; prog++, 2313 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 2314 if (sc->alc_cdata.alc_tx_cnt <= 0) 2315 break; 2316 prog++; 2317 ifp->if_flags &= ~IFF_OACTIVE; 2318 sc->alc_cdata.alc_tx_cnt--; 2319 txd = &sc->alc_cdata.alc_txdesc[cons]; 2320 if (txd->tx_m != NULL) { 2321 /* Reclaim transmitted mbufs. */ 2322 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 2323 m_freem(txd->tx_m); 2324 txd->tx_m = NULL; 2325 } 2326 } 2327 2328 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2329 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2330 sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2331 sc->alc_cdata.alc_tx_cons = cons; 2332 /* 2333 * Unarm watchdog timer only when there is no pending 2334 * frames in Tx queue. 2335 */ 2336 if (sc->alc_cdata.alc_tx_cnt == 0) 2337 ifp->if_timer = 0; 2338 } 2339 2340 static int 2341 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd, bool init) 2342 { 2343 struct mbuf *m; 2344 bus_dmamap_t map; 2345 int error; 2346 2347 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 2348 if (m == NULL) 2349 return (ENOBUFS); 2350 MCLGET(m, init ? M_WAITOK : M_DONTWAIT); 2351 if (!(m->m_flags & M_EXT)) { 2352 m_freem(m); 2353 return (ENOBUFS); 2354 } 2355 2356 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 2357 2358 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2359 sc->alc_cdata.alc_rx_sparemap, m, BUS_DMA_NOWAIT); 2360 2361 if (error != 0) { 2362 if (!error) { 2363 bus_dmamap_unload(sc->sc_dmat, 2364 sc->alc_cdata.alc_rx_sparemap); 2365 error = EFBIG; 2366 printf("%s: too many segments?!\n", 2367 device_xname(sc->sc_dev)); 2368 } 2369 m_freem(m); 2370 2371 if (init) 2372 printf("%s: can't load RX mbuf\n", device_xname(sc->sc_dev)); 2373 2374 return (error); 2375 } 2376 2377 if (rxd->rx_m != NULL) { 2378 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2379 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2380 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2381 } 2382 map = rxd->rx_dmamap; 2383 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 2384 sc->alc_cdata.alc_rx_sparemap = map; 2385 rxd->rx_m = m; 2386 rxd->rx_desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 2387 return (0); 2388 } 2389 2390 static int 2391 alc_rxintr(struct alc_softc *sc) 2392 { 2393 struct ifnet *ifp = &sc->sc_ec.ec_if; 2394 struct rx_rdesc *rrd; 2395 uint32_t nsegs, status; 2396 int rr_cons, prog; 2397 2398 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2399 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2400 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2401 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2402 rr_cons = sc->alc_cdata.alc_rr_cons; 2403 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0;) { 2404 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 2405 status = le32toh(rrd->status); 2406 if ((status & RRD_VALID) == 0) 2407 break; 2408 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 2409 if (nsegs == 0) { 2410 /* This should not happen! */ 2411 if (alcdebug) 2412 printf("%s: unexpected segment count -- " 2413 "resetting\n", device_xname(sc->sc_dev)); 2414 return (EIO); 2415 } 2416 alc_rxeof(sc, rrd); 2417 /* Clear Rx return status. */ 2418 rrd->status = 0; 2419 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 2420 sc->alc_cdata.alc_rx_cons += nsegs; 2421 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 2422 prog += nsegs; 2423 } 2424 2425 if (prog > 0) { 2426 /* Update the consumer index. */ 2427 sc->alc_cdata.alc_rr_cons = rr_cons; 2428 /* Sync Rx return descriptors. */ 2429 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2430 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 2431 BUS_DMASYNC_PREWRITE); 2432 /* 2433 * Sync updated Rx descriptors such that controller see 2434 * modified buffer addresses. 2435 */ 2436 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2437 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 2438 BUS_DMASYNC_PREWRITE); 2439 /* 2440 * Let controller know availability of new Rx buffers. 2441 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 2442 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 2443 * only when Rx buffer pre-fetching is required. In 2444 * addition we already set ALC_RX_RD_FREE_THRESH to 2445 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 2446 * it still seems that pre-fetching needs more 2447 * experimentation. 2448 */ 2449 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 2450 sc->alc_cdata.alc_rx_cons); 2451 } 2452 2453 return (0); 2454 } 2455 2456 /* Receive a frame. */ 2457 static void 2458 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 2459 { 2460 struct ifnet *ifp = &sc->sc_ec.ec_if; 2461 struct alc_rxdesc *rxd; 2462 struct mbuf *mp, *m; 2463 uint32_t rdinfo, status; 2464 int count, nsegs, rx_cons; 2465 2466 status = le32toh(rrd->status); 2467 rdinfo = le32toh(rrd->rdinfo); 2468 rx_cons = RRD_RD_IDX(rdinfo); 2469 nsegs = RRD_RD_CNT(rdinfo); 2470 2471 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 2472 if (status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) { 2473 /* 2474 * We want to pass the following frames to upper 2475 * layer regardless of error status of Rx return 2476 * ring. 2477 * 2478 * o IP/TCP/UDP checksum is bad. 2479 * o frame length and protocol specific length 2480 * does not match. 2481 * 2482 * Force network stack compute checksum for 2483 * errored frames. 2484 */ 2485 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 2486 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 2487 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 2488 return; 2489 } 2490 2491 for (count = 0; count < nsegs; count++, 2492 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 2493 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 2494 mp = rxd->rx_m; 2495 /* Add a new receive buffer to the ring. */ 2496 if (alc_newbuf(sc, rxd, false) != 0) { 2497 ifp->if_iqdrops++; 2498 /* Reuse Rx buffers. */ 2499 if (sc->alc_cdata.alc_rxhead != NULL) 2500 m_freem(sc->alc_cdata.alc_rxhead); 2501 break; 2502 } 2503 2504 /* 2505 * Assume we've received a full sized frame. 2506 * Actual size is fixed when we encounter the end of 2507 * multi-segmented frame. 2508 */ 2509 mp->m_len = sc->alc_buf_size; 2510 2511 /* Chain received mbufs. */ 2512 if (sc->alc_cdata.alc_rxhead == NULL) { 2513 sc->alc_cdata.alc_rxhead = mp; 2514 sc->alc_cdata.alc_rxtail = mp; 2515 } else { 2516 mp->m_flags &= ~M_PKTHDR; 2517 sc->alc_cdata.alc_rxprev_tail = 2518 sc->alc_cdata.alc_rxtail; 2519 sc->alc_cdata.alc_rxtail->m_next = mp; 2520 sc->alc_cdata.alc_rxtail = mp; 2521 } 2522 2523 if (count == nsegs - 1) { 2524 /* Last desc. for this frame. */ 2525 m = sc->alc_cdata.alc_rxhead; 2526 m->m_flags |= M_PKTHDR; 2527 /* 2528 * It seems that L1C/L2C controller has no way 2529 * to tell hardware to strip CRC bytes. 2530 */ 2531 m->m_pkthdr.len = 2532 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 2533 if (nsegs > 1) { 2534 /* Set last mbuf size. */ 2535 mp->m_len = sc->alc_cdata.alc_rxlen - 2536 (nsegs - 1) * sc->alc_buf_size; 2537 /* Remove the CRC bytes in chained mbufs. */ 2538 if (mp->m_len <= ETHER_CRC_LEN) { 2539 sc->alc_cdata.alc_rxtail = 2540 sc->alc_cdata.alc_rxprev_tail; 2541 sc->alc_cdata.alc_rxtail->m_len -= 2542 (ETHER_CRC_LEN - mp->m_len); 2543 sc->alc_cdata.alc_rxtail->m_next = NULL; 2544 m_freem(mp); 2545 } else { 2546 mp->m_len -= ETHER_CRC_LEN; 2547 } 2548 } else 2549 m->m_len = m->m_pkthdr.len; 2550 m->m_pkthdr.rcvif = ifp; 2551 #if NVLAN > 0 2552 /* 2553 * Due to hardware bugs, Rx checksum offloading 2554 * was intentionally disabled. 2555 */ 2556 if (status & RRD_VLAN_TAG) { 2557 u_int32_t vtag = RRD_VLAN(le32toh(rrd->vtag)); 2558 VLAN_INPUT_TAG(ifp, m, ntohs(vtag), ); 2559 } 2560 #endif 2561 2562 bpf_mtap(ifp, m); 2563 2564 /* Pass it on. */ 2565 (*ifp->if_input)(ifp, m); 2566 } 2567 } 2568 /* Reset mbuf chains. */ 2569 ALC_RXCHAIN_RESET(sc); 2570 } 2571 2572 static void 2573 alc_tick(void *xsc) 2574 { 2575 struct alc_softc *sc = xsc; 2576 struct mii_data *mii = &sc->sc_miibus; 2577 int s; 2578 2579 s = splnet(); 2580 mii_tick(mii); 2581 alc_stats_update(sc); 2582 splx(s); 2583 2584 callout_schedule(&sc->sc_tick_ch, hz); 2585 } 2586 2587 static void 2588 alc_osc_reset(struct alc_softc *sc) 2589 { 2590 uint32_t reg; 2591 2592 reg = CSR_READ_4(sc, ALC_MISC3); 2593 reg &= ~MISC3_25M_BY_SW; 2594 reg |= MISC3_25M_NOTO_INTNL; 2595 CSR_WRITE_4(sc, ALC_MISC3, reg); 2596 2597 reg = CSR_READ_4(sc, ALC_MISC); 2598 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) { 2599 /* 2600 * Restore over-current protection default value. 2601 * This value could be reset by MAC reset. 2602 */ 2603 reg &= ~MISC_PSW_OCP_MASK; 2604 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT); 2605 reg &= ~MISC_INTNLOSC_OPEN; 2606 CSR_WRITE_4(sc, ALC_MISC, reg); 2607 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 2608 reg = CSR_READ_4(sc, ALC_MISC2); 2609 reg &= ~MISC2_CALB_START; 2610 CSR_WRITE_4(sc, ALC_MISC2, reg); 2611 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); 2612 2613 } else { 2614 reg &= ~MISC_INTNLOSC_OPEN; 2615 /* Disable isolate for revision A devices. */ 2616 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 2617 reg &= ~MISC_ISO_ENB; 2618 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 2619 CSR_WRITE_4(sc, ALC_MISC, reg); 2620 } 2621 2622 DELAY(20); 2623 } 2624 2625 static void 2626 alc_reset(struct alc_softc *sc) 2627 { 2628 uint32_t pmcfg, reg; 2629 int i; 2630 2631 pmcfg = 0; 2632 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2633 /* Reset workaround. */ 2634 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); 2635 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 2636 (sc->alc_rev & 0x01) != 0) { 2637 /* Disable L0s/L1s before reset. */ 2638 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 2639 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 2640 != 0) { 2641 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB | 2642 PM_CFG_ASPM_L1_ENB); 2643 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 2644 } 2645 } 2646 } 2647 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2648 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 2649 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2650 2651 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2652 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2653 DELAY(10); 2654 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) 2655 break; 2656 } 2657 if (i == 0) 2658 printf("%s: MAC reset timeout!\n", device_xname(sc->sc_dev)); 2659 } 2660 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2661 DELAY(10); 2662 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 2663 break; 2664 } 2665 if (i == 0) 2666 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 2667 2668 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2669 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 2670 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC | 2671 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 2672 break; 2673 DELAY(10); 2674 } 2675 if (i == 0) 2676 printf("%s: reset timeout(0x%08x)!\n", 2677 device_xname(sc->sc_dev), reg); 2678 2679 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2680 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 2681 (sc->alc_rev & 0x01) != 0) { 2682 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2683 reg |= MASTER_CLK_SEL_DIS; 2684 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2685 /* Restore L0s/L1s config. */ 2686 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 2687 != 0) 2688 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 2689 } 2690 2691 alc_osc_reset(sc); 2692 reg = CSR_READ_4(sc, ALC_MISC3); 2693 reg &= ~MISC3_25M_BY_SW; 2694 reg |= MISC3_25M_NOTO_INTNL; 2695 CSR_WRITE_4(sc, ALC_MISC3, reg); 2696 reg = CSR_READ_4(sc, ALC_MISC); 2697 reg &= ~MISC_INTNLOSC_OPEN; 2698 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 2699 reg &= ~MISC_ISO_ENB; 2700 CSR_WRITE_4(sc, ALC_MISC, reg); 2701 DELAY(20); 2702 } 2703 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 2704 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 2705 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2) 2706 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 2707 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 2708 SERDES_PHY_CLK_SLOWDOWN); 2709 } 2710 2711 static int 2712 alc_init(struct ifnet *ifp) 2713 { 2714 2715 return alc_init_backend(ifp, true); 2716 } 2717 2718 static int 2719 alc_init_backend(struct ifnet *ifp, bool init) 2720 { 2721 struct alc_softc *sc = ifp->if_softc; 2722 struct mii_data *mii; 2723 uint8_t eaddr[ETHER_ADDR_LEN]; 2724 bus_addr_t paddr; 2725 uint32_t reg, rxf_hi, rxf_lo; 2726 int error; 2727 2728 /* 2729 * Cancel any pending I/O. 2730 */ 2731 alc_stop(ifp, 0); 2732 /* 2733 * Reset the chip to a known state. 2734 */ 2735 alc_reset(sc); 2736 2737 /* Initialize Rx descriptors. */ 2738 error = alc_init_rx_ring(sc, init); 2739 if (error != 0) { 2740 printf("%s: no memory for Rx buffers.\n", device_xname(sc->sc_dev)); 2741 alc_stop(ifp, 0); 2742 return (error); 2743 } 2744 alc_init_rr_ring(sc); 2745 alc_init_tx_ring(sc); 2746 alc_init_cmb(sc); 2747 alc_init_smb(sc); 2748 2749 /* Enable all clocks. */ 2750 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2751 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | 2752 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB | 2753 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB | 2754 CLK_GATING_RXMAC_ENB); 2755 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) 2756 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, 2757 IDLE_DECISN_TIMER_DEFAULT_1MS); 2758 } else 2759 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 2760 2761 2762 /* Reprogram the station address. */ 2763 memcpy(eaddr, CLLADDR(ifp->if_sadl), sizeof(eaddr)); 2764 CSR_WRITE_4(sc, ALC_PAR0, 2765 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2766 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 2767 /* 2768 * Clear WOL status and disable all WOL feature as WOL 2769 * would interfere Rx operation under normal environments. 2770 */ 2771 CSR_READ_4(sc, ALC_WOL_CFG); 2772 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2773 /* Set Tx descriptor base addresses. */ 2774 paddr = sc->alc_rdata.alc_tx_ring_paddr; 2775 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2776 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2777 /* We don't use high priority ring. */ 2778 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 2779 /* Set Tx descriptor counter. */ 2780 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 2781 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 2782 /* Set Rx descriptor base addresses. */ 2783 paddr = sc->alc_rdata.alc_rx_ring_paddr; 2784 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2785 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2786 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2787 /* We use one Rx ring. */ 2788 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 2789 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 2790 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 2791 } 2792 /* Set Rx descriptor counter. */ 2793 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 2794 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 2795 2796 /* 2797 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 2798 * if it do not fit the buffer size. Rx return descriptor holds 2799 * a counter that indicates how many fragments were made by the 2800 * hardware. The buffer size should be multiple of 8 bytes. 2801 * Since hardware has limit on the size of buffer size, always 2802 * use the maximum value. 2803 * For strict-alignment architectures make sure to reduce buffer 2804 * size by 8 bytes to make room for alignment fixup. 2805 */ 2806 sc->alc_buf_size = RX_BUF_SIZE_MAX; 2807 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 2808 2809 paddr = sc->alc_rdata.alc_rr_ring_paddr; 2810 /* Set Rx return descriptor base addresses. */ 2811 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2812 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2813 /* We use one Rx return ring. */ 2814 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 2815 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 2816 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 2817 }\ 2818 /* Set Rx return descriptor counter. */ 2819 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 2820 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 2821 paddr = sc->alc_rdata.alc_cmb_paddr; 2822 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2823 paddr = sc->alc_rdata.alc_smb_paddr; 2824 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2825 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2826 2827 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B) { 2828 /* Reconfigure SRAM - Vendor magic. */ 2829 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 2830 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 2831 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 2832 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 2833 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 2834 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 2835 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 2836 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 2837 } 2838 2839 /* Tell hardware that we're ready to load DMA blocks. */ 2840 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 2841 2842 /* Configure interrupt moderation timer. */ 2843 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 2844 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 2845 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 2846 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) 2847 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 2848 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 2849 /* 2850 * We don't want to automatic interrupt clear as task queue 2851 * for the interrupt should know interrupt status. 2852 */ 2853 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2854 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2855 reg |= MASTER_SA_TIMER_ENB; 2856 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 2857 reg |= MASTER_IM_RX_TIMER_ENB; 2858 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 && 2859 ALC_USECS(sc->alc_int_tx_mod) != 0) 2860 reg |= MASTER_IM_TX_TIMER_ENB; 2861 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2862 /* 2863 * Disable interrupt re-trigger timer. We don't want automatic 2864 * re-triggering of un-ACKed interrupts. 2865 */ 2866 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 2867 /* Configure CMB. */ 2868 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2869 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); 2870 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, 2871 ALC_USECS(sc->alc_int_tx_mod)); 2872 } else { 2873 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2874 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 2875 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 2876 } else 2877 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 2878 } 2879 /* 2880 * Hardware can be configured to issue SMB interrupt based 2881 * on programmed interval. Since there is a callout that is 2882 * invoked for every hz in driver we use that instead of 2883 * relying on periodic SMB interrupt. 2884 */ 2885 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 2886 /* Clear MAC statistics. */ 2887 alc_stats_clear(sc); 2888 2889 /* 2890 * Always use maximum frame size that controller can support. 2891 * Otherwise received frames that has larger frame length 2892 * than alc(4) MTU would be silently dropped in hardware. This 2893 * would make path-MTU discovery hard as sender wouldn't get 2894 * any responses from receiver. alc(4) supports 2895 * multi-fragmented frames on Rx path so it has no issue on 2896 * assembling fragmented frames. Using maximum frame size also 2897 * removes the need to reinitialize hardware when interface 2898 * MTU configuration was changed. 2899 * 2900 * Be conservative in what you do, be liberal in what you 2901 * accept from others - RFC 793. 2902 */ 2903 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 2904 2905 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2906 /* Disable header split(?) */ 2907 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 2908 2909 /* Configure IPG/IFG parameters. */ 2910 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 2911 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & 2912 IPG_IFG_IPGT_MASK) | 2913 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & 2914 IPG_IFG_MIFG_MASK) | 2915 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & 2916 IPG_IFG_IPG1_MASK) | 2917 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & 2918 IPG_IFG_IPG2_MASK)); 2919 /* Set parameters for half-duplex media. */ 2920 CSR_WRITE_4(sc, ALC_HDPX_CFG, 2921 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2922 HDPX_CFG_LCOL_MASK) | 2923 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2924 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2925 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2926 HDPX_CFG_ABEBT_MASK) | 2927 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2928 HDPX_CFG_JAMIPG_MASK)); 2929 } 2930 2931 /* 2932 * Set TSO/checksum offload threshold. For frames that is 2933 * larger than this threshold, hardware wouldn't do 2934 * TSO/checksum offloading. 2935 */ 2936 reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 2937 TSO_OFFLOAD_THRESH_MASK; 2938 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2939 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB; 2940 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); 2941 /* Configure TxQ. */ 2942 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 2943 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 2944 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 2945 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 2946 reg >>= 1; 2947 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 2948 TXQ_CFG_TD_BURST_MASK; 2949 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB; 2950 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 2951 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2952 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT | 2953 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT | 2954 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT | 2955 HQTD_CFG_BURST_ENB); 2956 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); 2957 reg = WRR_PRI_RESTRICT_NONE; 2958 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT | 2959 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT | 2960 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT | 2961 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT); 2962 CSR_WRITE_4(sc, ALC_WRR, reg); 2963 } else { 2964 /* Configure Rx free descriptor pre-fetching. */ 2965 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 2966 ((RX_RD_FREE_THRESH_HI_DEFAULT << 2967 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) | 2968 ((RX_RD_FREE_THRESH_LO_DEFAULT << 2969 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK)); 2970 } 2971 2972 /* 2973 * Configure flow control parameters. 2974 * XON : 80% of Rx FIFO 2975 * XOFF : 30% of Rx FIFO 2976 */ 2977 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2978 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 2979 reg &= SRAM_RX_FIFO_LEN_MASK; 2980 reg *= 8; 2981 if (reg > 8 * 1024) 2982 reg -= RX_FIFO_PAUSE_816X_RSVD; 2983 else 2984 reg -= RX_BUF_SIZE_MAX; 2985 reg /= 8; 2986 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 2987 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2988 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2989 (((RX_FIFO_PAUSE_816X_RSVD / 8) << 2990 RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2991 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2992 } else if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8131 || 2993 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8132) { 2994 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 2995 rxf_hi = (reg * 8) / 10; 2996 rxf_lo = (reg * 3) / 10; 2997 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 2998 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2999 RX_FIFO_PAUSE_THRESH_LO_MASK) | 3000 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 3001 RX_FIFO_PAUSE_THRESH_HI_MASK)); 3002 } 3003 3004 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3005 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 3006 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 3007 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 3008 } 3009 3010 /* Configure RxQ. */ 3011 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 3012 RXQ_CFG_RD_BURST_MASK; 3013 reg |= RXQ_CFG_RSS_MODE_DIS; 3014 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3015 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT << 3016 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) & 3017 RXQ_CFG_816X_IDT_TBL_SIZE_MASK; 3018 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 && 3019 sc->alc_ident->deviceid != PCI_PRODUCT_ATTANSIC_AR8151_V2) 3020 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M; 3021 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3022 3023 /* Configure DMA parameters. */ 3024 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 3025 reg |= sc->alc_rcb; 3026 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3027 reg |= DMA_CFG_CMB_ENB; 3028 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 3029 reg |= DMA_CFG_SMB_ENB; 3030 else 3031 reg |= DMA_CFG_SMB_DIS; 3032 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 3033 DMA_CFG_RD_BURST_SHIFT; 3034 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 3035 DMA_CFG_WR_BURST_SHIFT; 3036 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 3037 DMA_CFG_RD_DELAY_CNT_MASK; 3038 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 3039 DMA_CFG_WR_DELAY_CNT_MASK; 3040 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3041 switch (AR816X_REV(sc->alc_rev)) { 3042 case AR816X_REV_A0: 3043 case AR816X_REV_A1: 3044 reg |= DMA_CFG_RD_CHNL_SEL_1; 3045 break; 3046 case AR816X_REV_B0: 3047 /* FALLTHROUGH */ 3048 default: 3049 reg |= DMA_CFG_RD_CHNL_SEL_3; 3050 break; 3051 } 3052 } 3053 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3054 3055 /* 3056 * Configure Tx/Rx MACs. 3057 * - Auto-padding for short frames. 3058 * - Enable CRC generation. 3059 * Actual reconfiguration of MAC for resolved speed/duplex 3060 * is followed after detection of link establishment. 3061 * AR813x/AR815x always does checksum computation regardless 3062 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 3063 * have bug in protocol field in Rx return structure so 3064 * these controllers can't handle fragmented frames. Disable 3065 * Rx checksum offloading until there is a newer controller 3066 * that has sane implementation. 3067 */ 3068 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 3069 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 3070 MAC_CFG_PREAMBLE_MASK); 3071 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3072 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 3073 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 3074 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 3075 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3076 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 3077 reg |= MAC_CFG_SPEED_10_100; 3078 else 3079 reg |= MAC_CFG_SPEED_1000; 3080 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3081 3082 /* Set up the receive filter. */ 3083 alc_iff(sc); 3084 alc_rxvlan(sc); 3085 3086 /* Acknowledge all pending interrupts and clear it. */ 3087 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 3088 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3089 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3090 3091 sc->alc_flags &= ~ALC_FLAG_LINK; 3092 /* Switch to the current media. */ 3093 mii = &sc->sc_miibus; 3094 mii_mediachg(mii); 3095 3096 callout_schedule(&sc->sc_tick_ch, hz); 3097 3098 ifp->if_flags |= IFF_RUNNING; 3099 ifp->if_flags &= ~IFF_OACTIVE; 3100 3101 return (0); 3102 } 3103 3104 static void 3105 alc_stop(struct ifnet *ifp, int disable) 3106 { 3107 struct alc_softc *sc = ifp->if_softc; 3108 struct alc_txdesc *txd; 3109 struct alc_rxdesc *rxd; 3110 uint32_t reg; 3111 int i; 3112 3113 callout_stop(&sc->sc_tick_ch); 3114 3115 /* 3116 * Mark the interface down and cancel the watchdog timer. 3117 */ 3118 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3119 ifp->if_timer = 0; 3120 3121 sc->alc_flags &= ~ALC_FLAG_LINK; 3122 3123 alc_stats_update(sc); 3124 3125 mii_down(&sc->sc_miibus); 3126 3127 /* Disable interrupts. */ 3128 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 3129 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3130 3131 /* Disable DMA. */ 3132 reg = CSR_READ_4(sc, ALC_DMA_CFG); 3133 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 3134 reg |= DMA_CFG_SMB_DIS; 3135 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3136 DELAY(1000); 3137 3138 /* Stop Rx/Tx MACs. */ 3139 alc_stop_mac(sc); 3140 3141 /* Disable interrupts which might be touched in taskq handler. */ 3142 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3143 3144 /* Disable L0s/L1s */ 3145 alc_aspm(sc, 0, IFM_UNKNOWN); 3146 3147 /* Reclaim Rx buffers that have been processed. */ 3148 if (sc->alc_cdata.alc_rxhead != NULL) 3149 m_freem(sc->alc_cdata.alc_rxhead); 3150 ALC_RXCHAIN_RESET(sc); 3151 /* 3152 * Free Tx/Rx mbufs still in the queues. 3153 */ 3154 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3155 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3156 if (rxd->rx_m != NULL) { 3157 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 3158 m_freem(rxd->rx_m); 3159 rxd->rx_m = NULL; 3160 } 3161 } 3162 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3163 txd = &sc->alc_cdata.alc_txdesc[i]; 3164 if (txd->tx_m != NULL) { 3165 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 3166 m_freem(txd->tx_m); 3167 txd->tx_m = NULL; 3168 } 3169 } 3170 } 3171 3172 static void 3173 alc_stop_mac(struct alc_softc *sc) 3174 { 3175 uint32_t reg; 3176 int i; 3177 3178 alc_stop_queue(sc); 3179 /* Disable Rx/Tx MAC. */ 3180 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3181 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 3182 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 3183 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3184 } 3185 for (i = ALC_TIMEOUT; i > 0; i--) { 3186 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3187 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0) 3188 break; 3189 DELAY(10); 3190 } 3191 if (i == 0) 3192 printf("%s: could not disable Rx/Tx MAC(0x%08x)!\n", 3193 device_xname(sc->sc_dev), reg); 3194 } 3195 3196 static void 3197 alc_start_queue(struct alc_softc *sc) 3198 { 3199 uint32_t qcfg[] = { 3200 0, 3201 RXQ_CFG_QUEUE0_ENB, 3202 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 3203 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 3204 RXQ_CFG_ENB 3205 }; 3206 uint32_t cfg; 3207 3208 /* Enable RxQ. */ 3209 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 3210 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3211 cfg &= ~RXQ_CFG_ENB; 3212 cfg |= qcfg[1]; 3213 } else 3214 cfg |= RXQ_CFG_QUEUE0_ENB; 3215 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 3216 /* Enable TxQ. */ 3217 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 3218 cfg |= TXQ_CFG_ENB; 3219 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 3220 } 3221 3222 static void 3223 alc_stop_queue(struct alc_softc *sc) 3224 { 3225 uint32_t reg; 3226 int i; 3227 3228 /* Disable RxQ. */ 3229 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 3230 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3231 if ((reg & RXQ_CFG_ENB) != 0) { 3232 reg &= ~RXQ_CFG_ENB; 3233 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3234 } 3235 } else { 3236 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) { 3237 reg &= ~RXQ_CFG_QUEUE0_ENB; 3238 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3239 } 3240 } 3241 /* Disable TxQ. */ 3242 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 3243 if ((reg & TXQ_CFG_ENB) != 0) { 3244 reg &= ~TXQ_CFG_ENB; 3245 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 3246 } 3247 DELAY(40); 3248 for (i = ALC_TIMEOUT; i > 0; i--) { 3249 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3250 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3251 break; 3252 DELAY(10); 3253 } 3254 if (i == 0) 3255 printf("%s: could not disable RxQ/TxQ (0x%08x)!\n", 3256 device_xname(sc->sc_dev), reg); 3257 } 3258 3259 static void 3260 alc_init_tx_ring(struct alc_softc *sc) 3261 { 3262 struct alc_ring_data *rd; 3263 struct alc_txdesc *txd; 3264 int i; 3265 3266 sc->alc_cdata.alc_tx_prod = 0; 3267 sc->alc_cdata.alc_tx_cons = 0; 3268 sc->alc_cdata.alc_tx_cnt = 0; 3269 3270 rd = &sc->alc_rdata; 3271 memset(rd->alc_tx_ring, 0, ALC_TX_RING_SZ); 3272 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3273 txd = &sc->alc_cdata.alc_txdesc[i]; 3274 txd->tx_m = NULL; 3275 } 3276 3277 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 3278 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3279 } 3280 3281 static int 3282 alc_init_rx_ring(struct alc_softc *sc, bool init) 3283 { 3284 struct alc_ring_data *rd; 3285 struct alc_rxdesc *rxd; 3286 int i; 3287 3288 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 3289 rd = &sc->alc_rdata; 3290 memset(rd->alc_rx_ring, 0, ALC_RX_RING_SZ); 3291 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3292 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3293 rxd->rx_m = NULL; 3294 rxd->rx_desc = &rd->alc_rx_ring[i]; 3295 if (alc_newbuf(sc, rxd, init) != 0) 3296 return (ENOBUFS); 3297 } 3298 3299 /* 3300 * Since controller does not update Rx descriptors, driver 3301 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 3302 * is enough to ensure coherence. 3303 */ 3304 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 3305 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3306 /* Let controller know availability of new Rx buffers. */ 3307 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 3308 3309 return (0); 3310 } 3311 3312 static void 3313 alc_init_rr_ring(struct alc_softc *sc) 3314 { 3315 struct alc_ring_data *rd; 3316 3317 sc->alc_cdata.alc_rr_cons = 0; 3318 ALC_RXCHAIN_RESET(sc); 3319 3320 rd = &sc->alc_rdata; 3321 memset(rd->alc_rr_ring, 0, ALC_RR_RING_SZ); 3322 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 3323 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3324 } 3325 3326 static void 3327 alc_init_cmb(struct alc_softc *sc) 3328 { 3329 struct alc_ring_data *rd; 3330 3331 rd = &sc->alc_rdata; 3332 memset(rd->alc_cmb, 0, ALC_CMB_SZ); 3333 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 3334 sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3335 } 3336 3337 static void 3338 alc_init_smb(struct alc_softc *sc) 3339 { 3340 struct alc_ring_data *rd; 3341 3342 rd = &sc->alc_rdata; 3343 memset(rd->alc_smb, 0, ALC_SMB_SZ); 3344 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 3345 sc->alc_cdata.alc_smb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3346 } 3347 3348 static void 3349 alc_rxvlan(struct alc_softc *sc) 3350 { 3351 uint32_t reg; 3352 3353 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3354 if (sc->sc_ec.ec_capenable & ETHERCAP_VLAN_HWTAGGING) 3355 reg |= MAC_CFG_VLAN_TAG_STRIP; 3356 else 3357 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3358 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3359 } 3360 3361 static void 3362 alc_iff(struct alc_softc *sc) 3363 { 3364 struct ethercom *ec = &sc->sc_ec; 3365 struct ifnet *ifp = &ec->ec_if; 3366 struct ether_multi *enm; 3367 struct ether_multistep step; 3368 uint32_t crc; 3369 uint32_t mchash[2]; 3370 uint32_t rxcfg; 3371 3372 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 3373 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3374 ifp->if_flags &= ~IFF_ALLMULTI; 3375 3376 /* 3377 * Always accept broadcast frames. 3378 */ 3379 rxcfg |= MAC_CFG_BCAST; 3380 3381 if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 3382 ifp->if_flags |= IFF_ALLMULTI; 3383 if (ifp->if_flags & IFF_PROMISC) 3384 rxcfg |= MAC_CFG_PROMISC; 3385 else 3386 rxcfg |= MAC_CFG_ALLMULTI; 3387 mchash[0] = mchash[1] = 0xFFFFFFFF; 3388 } else { 3389 /* Program new filter. */ 3390 memset(mchash, 0, sizeof(mchash)); 3391 3392 ETHER_FIRST_MULTI(step, ec, enm); 3393 while (enm != NULL) { 3394 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3395 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3396 ETHER_NEXT_MULTI(step, enm); 3397 } 3398 } 3399 3400 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 3401 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 3402 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 3403 } 3404 3405 MODULE(MODULE_CLASS_DRIVER, if_alc, "pci"); 3406 3407 #ifdef _MODULE 3408 #include "ioconf.c" 3409 #endif 3410 3411 static int 3412 if_alc_modcmd(modcmd_t cmd, void *opaque) 3413 { 3414 int error = 0; 3415 3416 switch (cmd) { 3417 case MODULE_CMD_INIT: 3418 #ifdef _MODULE 3419 error = config_init_component(cfdriver_ioconf_if_alc, 3420 cfattach_ioconf_if_alc, cfdata_ioconf_if_alc); 3421 #endif 3422 return error; 3423 case MODULE_CMD_FINI: 3424 #ifdef _MODULE 3425 error = config_fini_component(cfdriver_ioconf_if_alc, 3426 cfattach_ioconf_if_alc, cfdata_ioconf_if_alc); 3427 #endif 3428 return error; 3429 default: 3430 return ENOTTY; 3431 } 3432 } 3433
Indexes created Fri Sep 26 08:10:20 GMT 2025